L3
L3
L3
Theory
Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design,
Addison-Wesley, 3/e, 2004
Outline
MOS Structure
Vgs = Vg Vs
Vgd = Vg Vd
Vg
+
Vgd
-
+
Vgs
Vs
Vds
Vd
No channel
Ids = 0
Channel forms
Current flows from D to S
e- from S to D
Ids increases with Vds
Similar to linear
resistor
pMOS Transistor
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11
Channel Charge
C = Cg = oxWL/tox = coxWL
cox = ox / tox
12
Carrier velocity
t=L/v
13
Now we know
W
= Cox
L
V V Vds V
gs t
ds
2
V
Vgs Vt ds Vds
2
14
Vgs Vt
2
Vdsat
Vdsat
15
Vgs Vt
Vds
I ds Vgs Vt
Vds Vds Vdsat
Vgs Vt
Vds Vdsat
cutoff
linear
saturation
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17
Example
0.6 m process from AMI Semiconductor
tox = 100
2.5
= 350 cm2/V*s
Vt = 0.7 V
Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2
Vgs = 5
2
Ids (mA)
1.5
Vgs = 4
Vgs = 3
0.5
0
Vgs = 2
Vgs = 1
Vds
W
W
120
A /V 2
L
L
18
Vgs Vt
V
I ds Vgs Vt ds Vds Vds Vdsat
2
Vgs Vt
Vds Vdsat
cutoff
linear
saturation
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Gate Capacitance
Gate Capacitance
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Linear
Saturation
Cgb (total)
C0
Cgd (total)
CoxWLD
C0/2 + CoxWLD
CoxWLD
Cgs (total)
CoxWLD
C0/2 + CoxWLD
25
Diffusion Capacitance
Csb, Cdb
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27
29
Body Effect
Vsb
Process
Doping
Temperature
31
Subthreshold Conduction
Junction Leakage
33
Tunneling
34
Temperature dependence
Geometry Dependence
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37
Pass Transistors
Called a degraded 1
Approach degraded value slowly (low Ids)
Called a degraded 0
Approach degraded value slowly (low Ids)
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Tri-state Inverter
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Ids = Vds/R
RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2)
or maybe 1 m wide device
Doesnt matter as long as you are consistent
43
RC Delay Models
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45
delay = 6RC
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Summary
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