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    Design of Sense Amplifier

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    pooja112
    This project presentation summarizes the design of a sense amplifier for SRAM. It introduces SRAM and how sense amplifiers are used to detect small voltage differences on bit lines and amplify them. The objectives are to reduce sense delay, find a tradeoff between sense offset, and reduce power consumption by sizing transistors. It describes two types of sense amplifiers and design metrics like sensing delay and offset. The designed circuit uses a voltage latched sense amplifier with a self-closing bit line module to separate input and output nodes, reducing capacitance and power consumption while quickly amplifying signals. The conclusion is that this technique is suitable for low power applications requiring stability at high speeds.

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    © All Rights Reserved
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    Design of Sense Amplifier

    Uploaded by

    pooja112
    152 views17 pages
    This project presentation summarizes the design of a sense amplifier for SRAM. It introduces SRAM and how sense amplifiers are used to detect small voltage differences on bit lines and amplify them. The objectives are to reduce sense delay, find a tradeoff between sense offset, and reduce power consumption by sizing transistors. It describes two types of sense amplifiers and design metrics like sensing delay and offset. The designed circuit uses a voltage latched sense amplifier with a self-closing bit line module to separate input and output nodes, reducing capacitance and power consumption while quickly amplifying signals. The conclusion is that this technique is suitable for low power applications requiring stability at high speeds.

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    Design of sense amplifier using Hspice

    Original Title

    Design of sense amplifier

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    This project presentation summarizes the design of a sense amplifier for SRAM. It introduces SRAM and how sense amplifiers are used to detect small voltage differences on bit lines and amplify them. The objectives are to reduce sense delay, find a tradeoff between sense offset, and reduce power consumption by sizing transistors. It describes two types of sense amplifiers and design metrics like sensing delay and offset. The designed circuit uses a voltage latched sense amplifier with a self-closing bit line module to separate input and output nodes, reducing capacitance and power consumption while quickly amplifying signals. The conclusion is that this technique is suitable for low power applications requiring stability at high speeds.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    152 views17 pages

    Design of Sense Amplifier

    Uploaded by

    pooja112
    This project presentation summarizes the design of a sense amplifier for SRAM. It introduces SRAM and how sense amplifiers are used to detect small voltage differences on bit lines and amplify them. The objectives are to reduce sense delay, find a tradeoff between sense offset, and reduce power consumption by sizing transistors. It describes two types of sense amplifiers and design metrics like sensing delay and offset. The designed circuit uses a voltage latched sense amplifier with a self-closing bit line module to separate input and output nodes, reducing capacitance and power consumption while quickly amplifying signals. The conclusion is that this technique is suitable for low power applications requiring stability at high speeds.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 17

    A

    Project Presentation
    On
    Design of Sense Amplifier for SRAM
    By
    Manjul Nikumbh
    Exam Seat No.:10812
    Under The Guidance of

    Prof. S.S. Chopade

    OUTLINE
    INTRODUCTION
    SRAM CELL
    SENSE AMPLIFIER
    WRITE CYCLE
    READ CYCLE
    OBJECTIVE
    TYPES OF SENSE AMPLIFIERS
    DESIGN & DESIGN METRICS
    RESULTS
    CONCLUSION

    INTRODUCTION
    SRAM area is expected to exceed 90% of overall chip
    area.
    To increase memory density, memory bit-cells are
    scaled to reduce their area by 50% each technology.

    INTRODUCTION
    SRAM ARRAY
    Row Decoder
    Pre-Charge Circuit
    Write Circuit
    Sense Amplifier

    SRAM CELL
    6T-SRAM CELL
    Write Line (WL)
    Data line (BL)
    Data line bar (BLB)
    Cross coupled inverter

    SENSE AMPLIFIER

    Need of Sense Amplifier


    Sense amplifiers are a part of SRAMs and are used to
    find minute differentials in voltages or currents on the
    bit-lines and enlarge them to distinct levels prior to the
    signals are charged or discharged. They can be
    1. Voltage Sense Amplifiers
    2. Current Sense Amplifiers

    WRITE CYCLE IN SRAM


    WL HIGH STATUS
    BL HIGH (to write 1)
    Q - DATA WRITTEN

    WRITE CYCLE IN SRAM

    READ CYCLE
    Pre-Charge of the BL & BLB lines.
    Sense the difference at the BL & BLB lines
    Give the result on the data lines

    OBJECTIVE
    The objective of project is to implement a Sense Amplifier with:

    Reduction in sense delay


    Decide a trade-off between Sense offset
    Sizing of Transistors to reduce power consumption

    SENSE AMPLIFIER TYPES


    There are two types of sense amplifier:

    Conventional Voltage Latched Sense Amplifier


    Conventional Current Latched Sense Amplifier

    DESIGN METRICS
    Sensing delay is defined as the delay between the
    instant the sense amplifier enable signal is applied and
    the instant when a stable l or 0 signal is sensed.
    Sensing offset in a differential SA can be defined as
    the minimum voltage/current difference required
    between the bit-lines so that the SA can correctly sense
    the output.

    DESIGN
    The circuit is mainly based on VLSA style, and added
    self-closing bit-lines module which is consist of MOS
    transistors M6, M7, M10 and M11. The self-closing
    bit-line module is used for transmission and turning
    off the voltage.

    RESULTS

    RESULTS

    Conclusion
    New voltage latched sense amplifier uses an automatic-closing bitline module new technique, which makes the output and input
    nodes separate and thus decreasing the total capacitance, while
    also reducing the total static power consumption of the circuit. The
    circuit design also has the ability to rapidly amplify small differential
    voltage signal present on the bit-lines (bit b, bit) to the maximum
    voltage swing without the requirement of a larger input voltage.
    This voltage latched sense amplifier helps reduce both sensing
    delay and power consumption and, especially in large sized SRAM
    operational design. Thus it can be concluded that the automaticclosing bit-line module, new technique is suitable for applications
    where low power, low voltage, stability at higher speed of operation
    and high speed are design considerations.

    Thank You

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