Computer Organisation and Design
Computer Organisation and Design
Computer Organisation and Design
Memory It’s an
ADD
operation
Op code
Control
110010?????????? Unit
Read instruction
from memory
Operands
(data)
15 0
Processor register
(Accumulator AC)
300 1350
457 Operand
1350 Operand
+ +
AC AC
15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC
List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
Adder E
and
logic
AC 4 Computer Registers
LD INR CLR Common Bus System
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
3x8
decoder
7 6543 210
D0
I
D7 Control Control
logic outputs
gates
T15
T0
15 14 . . . . 2 1 0
4 x 16
Sequence decoder
T0
T1
T2
T3
T4
D3
CLR
SC
T1 S2
T0 S1 Bus
S0
Memory
7
unit
Address
Read
AR 1
LD
PC 2
INR
IR 5
LD Clock
Common bus
CO208: Computer Architecture 40
Start DETERMINE THE TYPE OF INSTRUCTION
SC 0
T0
AR PC
T1
IR M[AR], PC PC + 1
T2
Decode Opcode in IR(12-14),
AR IR(0-11), I IR(15)
T3 T3 T3 T3
Execute Execute AR M[AR] Nothing
input-output register-reference
instruction instruction
SC 0 SC 0 Execute T4
memory-reference
instruction
SC 0
D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
Operation
Symbol Symbolic Description
Decoder
AND D0 AC AC M[AR]
ADD D1 AC AC + M[AR], E Cout
LDA D2 AC M[AR]
STA D3 M[AR] AC
BUN D4 PC AR
BSA D5 M[AR] PC, PC AR + 1
ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to be completed in a CPU cycle
- The execution of MR Instruction starts with T4
AND to AC
D0T4: DR M[AR] Read operand
D0T5: AC AC DR, SC 0 AND with AC
ADD to AC
D1T4: DR M[AR] Read operand
D1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E
CO208: Computer Architecture 43
MEMORY REFERENCE INSTRUCTIONScont.
LDA: Load to AC
D2T4: DR M[AR]
D2T5: AC DR, SC 0
STA: Store AC
D3T4: M[AR] AC, SC 0
BUN: Branch Unconditionally
D4T4: PC AR, SC 0
BSA: Branch and Save Return Address
M[AR] PC, PC AR + 1
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
Return address: PC = 21 Next instruction 21 Next instruction
AR = 135 135 21
136 Subroutine PC = 136 Subroutine
D0 T 4 D1 T 4 D2 T 4 D 3T 4
D0 T 5 D1 T 5 D2 T 5
AC AC DR AC AC + DR AC DR
SC <- 0 E Cout SC 0
SC 0
D4 T 4 D5 T 4 D6 T 4
PC AR M[AR] PC DR M[AR]
SC 0 AR AR + 1
D5 T 5 D6 T 5
PC AR DR DR + 1
SC 0
D6 T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0
AC
Transmitter
Keyboard interface INPR FGI
Execute =0
IEN
instructions
=1 Branch to location 1
PC 1
=1
FGI
=0
=1 IEN 0
FGO R 0
=0
R1
Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program
1 BUN 0 1 BUN 0
T2
write
Memory 7
Address
CLR
PC 2
INR
Register transfers
LD
TR 6
for the Interrupt
Cycle
AR 1
CLR
0 IEN
J
CLR SC R
0 J
Clock
Interrupt:
T0’T1’T2’(IEN)(FGI + FGO): R1
RT0: AR 0, TR PC
RT1: M[AR] TR, PC 0
RT2: PC PC + 1, IEN 0, R 0, SC 0
Memory-Reference:
AND D0T4: DR M[AR]
D0T5: AC AC . DR, SC 0
ADD D1T4: DR M[AR]
D1T5: AC AC + DR, E Cout, SC 0
LDA D2T4: DR M[AR]
D2T5: AC DR, SC 0
STA D3T4: M[AR] AC, SC 0
BUN D4T4: PC AR, SC 0
BSA D5T4: M[AR] PC, AR AR + 1
D5T5: PC AR, SC 0
ISZ D6T4: DR M[AR]
D6T5: DR DR + 1
D6T6: M[AR] DR, if(DR=0) then (PC PC + 1), SC 0
CO208: Computer Architecture 70
5-8 Complete Computer
Register-Reference:
Descriptioncont.
D7I’T3 = r (Common to all register-reference instructions)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC 0
CLA rB11: AC 0
CLE rB10: E0
CMA rB9: AC AC’
CME rB8: E E’
CIR rB7: AC shr AC, AC(15) E, E AC(0)
CIL rB6: AC shl AC, AC(0) E, E AC(15)
INC rB5: AC AC + 1
SPA rB4: If(AC(15) =0) then (PC PC + 1)
SNA rB3: If(AC(15) =1) then (PC PC + 1) Table 5-6
SZA rB2: If(AC = 0) then (PC PC + 1)
SZE rB1: If(E=0) then (PC PC + 1)
HLT rB0: S0
Input-Output:
D7IT3 = p (Common to all input-output instructions)
IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC 0
INP pB11: AC(0-7) INPR, FGI 0
OUT pB10: OUTR AC(0-7), FGO 0
SKI pB9: If(FGI=1) then (PC PC + 1)
SKO pB8: If(FGO=1) then (PC PC + 1)
ION pB7: IEN 1
IOF pB6: IEN 0
CO208: Computer Architecture 71
5-9 Design of Basic Computer
1. A memory unit: 4096 x 16.
2. Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR,
and SC
3. Flip-Flops (Status): I, S, E, R, IEN, FGI, and
FGO
4. Decoders:
1. a 3x8 Opcode decoder
2. a 4x16 timing decoder
5. Common bus: 16 bits
6. Control logic gates
7. Adder and Logic circuit: Connected to AC
CO208: Computer Architecture 72
5-9 Design of Basic
Computercont.
• The control logic gates are used to
control:
– Inputs of the nine registers
– Read and Write inputs of memory
– Set, Clear, or Complement inputs of the flip-
flops
– S2, S1, S0 that select a register for the bus
– AC Adder and Logic circuit
B6
K
R
T2
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q’(t)
JK FF Characteristic Table CO208: Computer Architecture 78
5-9 Design of Basic
Computercont.
• Control of Common bus is accomplished
by placing an encoder at the inputs of the
bus selection logic and implementing the
logic for each encoder input
x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7
8 circuit To bus
From INPR
Control
gates
AND
Ci ADD LD
FA Ii J Q
LDA AC(i)
C i+1
INPR K
From
INPR
bit(i)
COM
SHR
AC(i+1)
SHL
AC(i-1)