Scribd
Upload
58 views23 pages

Unit 2 - Over View + DE

This document covers combinational circuits and their applications. It discusses half adders, full adders, 4-bit ripple carry adders and subtractors. It then motivates carry lookahead adders by explaining their faster propagation delay compared to ripple carry adders. Carry lookahead adders use carry propagate and generate signals to calculate carries in parallel rather than series. The document also covers BCD adders, magnitude comparators using 1-bit and 2-bit inputs, and multiplexers including 2:1 and 4:1 MUX. It concludes with a summary of Units 1 and 2 covering logic gates, Boolean algebra, mapping specifications, and combinational circuits.

Uploaded by

Jaswanth Suggula
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
Download as pptx, pdf, or txt
58 views23 pages

Unit 2 - Over View + DE

This document covers combinational circuits and their applications. It discusses half adders, full adders, 4-bit ripple carry adders and subtractors. It then motivates carry lookahead adders by explaining their faster propagation delay compared to ripple carry adders. Carry lookahead adders use carry propagate and generate signals to calculate carries in parallel rather than series. The document also covers BCD adders, magnitude comparators using 1-bit and 2-bit inputs, and multiplexers including 2:1 and 4:1 MUX. It concludes with a summary of Units 1 and 2 covering logic gates, Boolean algebra, mapping specifications, and combinational circuits.

Uploaded by

Jaswanth Suggula
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
Download as pptx, pdf, or txt
Download as pptx, pdf, or txt
You are on page 1/ 23

Unit 2- Combinational Circuit

Design
Logic Gates:
Overview of unit 1:
UNIT 2
Combinational Circuits:
Half Adder and Full Adder:
4 bit Adder circuit (Ripple carry Adder):
4 bit Subtractor circuit:
Binary Parallel Adder/Subtractor:

M = 1subtractor ;
M = 0adder.
Motivation for Carry look Ahead Adder:
• Ripple carry adder or binary parallel adder causes a unstable factor on carry bit, and
produces a longest propagation delay.
• Carry Propagate Pi = Ai ⊕ Bi steady state value
• Carry Generate Gi = AiBi steady state value
Carry Look Ahead Adder:
• Output sum and carry
Si = Pi ⊕ Ci
Ci+1 = Gi + PiCi
C0 = input carry

C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

• C3 does not have to wait for C2 and C1 to propagate.


Logic diagram of Carry look-ahead generator :

• C3 is propagated at the same time as C2 and C1.

12
4-Bit Carry look-ahead Adder:
BCD Adder:
• BCD adder can’t exceed 9 on each input digit. K is the carry.
Implementation of BCD adder
• When the binary sum is
greater than 1001, we
obtain a non-valid BCD
representation.

• The addition of binary


6(0110) to the binary
If =1 sum converts it to the
correct BCD
representation and also
0 1 1 0 produces an output carry
as required.
Magnitude Comparator:
1-bit Magnitude Comparator:

Inputs Outputs
(A > B) ≡ A’ B
A B A>B A<B A=B

0 0 0 0 1 (A < B) ≡ A B’

0 1 0 1 0
(A = B) ≡ A’ B’ + A B = A ⊙ B
1 0 1 0 0

1 1 0 0 1
2 -bit Magnitude Comparator
Input A Input B Outputs Input A Input B Outputs
A1 A0 B1 B0 A>B A<B A=B A1 A0 B1 B0 A>B A<B A=B

0 0 0 0 0 0 1 1 0 0 0 1 0 0
0 0 0 1 0 1 0 1 0 0 1 1 0 0
0 0 1 0 0 1 0 1 0 1 0 0 0 1
0 0 1 1 0 1 0 1 0 1 1 0 1 0
0 1 0 0 1 0 0 1 1 0 0 1 0 0
0 1 0 1 0 0 1 1 1 0 1 1 0 0
0 1 1 0 0 1 0 1 1 1 0 1 0 0
0 1 1 1 0 1 0 1 1 1 1 0 0 1
2 -bit Magnitude Comparator
A>B A<B A=B
B1B0 B1B0 B1B0

A1 A0 00 01 11 10 A1 A0 00 01 11 10 A1 A0 00 01 11 10

00 0 0 0 0 00 0 1 1 1 00 1 0 0 0

01 1 0 0 0 01 0 0 1 1 01 0 1 0 0

11 1 1 0 1 11 0 0 0 0 11 0 0 1 0

10 1 1 0 0 10 0 0 1 0 10 0 0 0 1
2: 1 MUX:
4:1 MUX:
Unit 1 and 2 Summary:

• Logic Gates

• Boolean Algebra

• Map Specification

• Combinational Circuits
Thank You

You might also like