Definitions

Asynchronous circuits: within large synchronous systems, it is often

desirable to allow certain subsystems to operate asynchronously
to reduce delay and power consumption

Total state: combination of signals that appear at the primary input and
delay outputs

x1 z1
Input state: combination of input signals Level
inputs xl
Level
outputs
Combinational zm
x1, x2, …, xl logic

y1 Y1
Secondary or internal state: combination D
y2 Y2
of signals at the delay outputs y1, y2, …, yk D

yk Yk
D
Secondary or internal variables: y1, y2, …, yk

Excitation variables: Y1, Y2, …, Yk

1
Modes of Operation
Stable state: for a given input state, the circuit is said to be in a stable state
if and only if yi = Yi for i = 1, 2, …, k
• In response to a change in the input state: the combinational logic
produces a new set of values for the excitation variables, entering an
unstable state
• When the secondary variables assume their new values (when y’s
become equal to the corresponding Y’s): the circuit enters its next stable
state
– Thus, a transition from one stable state to another occurs only in
response to a change in the input state

Fundamental mode: when a change in input values has occurred, no other

change in any input value occurs until the circuit enters a stable
state
• Single-input change (SIC) fundamental mode: a single input value is
allowed to change at a time
• Multiple-input change (MIC) fundamental mode: multiple input values can
change at a time
2
Hazards
Two type of hazards (glitches): logic and function
• Logic hazards: caused by noninstantaneous changes in circuit signals
• Function hazards: inherent in the functional specification

Hazards pose a fundamental problem: a glitch may be misunderstood by

another part of the circuit as a valid transition and cause incorrect
behavior

3
Design of SIC Hazard-free Circuits
Example: T(x,y,z) =  (2,3,5,7)
• Static-1 logic hazard (SIC)
x
xy G1 y 1
z x
00 01 11 10 y 1 x 1 T
0 1 z 1
T
G2 y 1 1
1 1 1 1 x z 1
z 1
(a) Map for T = x y + xz. (b) Gate network. (c) SIC hazard-free network

Adjacent combinations: differ in the value of a single variable

• E.g., x’yz and xyz

SIC static logic hazard: transition between a pair of adjacent input

combinations, which correspond to identical output values, that may
generate a momentary spurious output value
• Occurs when no cube in the K-map contains both combinations
– Solution: cover both combinations with a cube
4
Transition/Required Cubes
Transition cube [m1,m2]: set of all minterms that can be reached from
minterm m1 and ending at minterm m2

Example: Transition cube [010,100] contains: 000, 010, 100, 110

Required cube: transition cube that must be included in some product of

the sum-of-products realization in order to get rid of the static-1
logic hazard

Example: Required cube is [011,111]

xy
z 00 01 11 10

0 1

1 1 1 1

5
Static-0/Dynamic Hazard
Since in the sum-of-products realization of a function: no cube for any
product term can contain either of the two input combinations
involved in a 0->0 output transition, a static-0 logic hazard can
only occur if a product term has both xi and xi’ as input literals
• Since there is no need to include such products: such hazards can be
trivially avoided

During a 0->1 output transition: if the 0 may change to 1 and then 0 and
finally stabilize at 1, then the sum-of-products realization is said to
have a dynamic 0->1 logic hazard
• Dynamic 1->0 logic hazard is similarly defined

Based on above reasoning: a dynamic 0->1 and 1->0 logic hazard is also
trivially avoidable in the SIC scenario

6
Design of MIC Hazard-free Circuits
MIC scenario: several inputs change values monotonically, i.e., at most
once
• If in this process, the function changes values more than once: the
transition is said to have a function hazard

Example: Function hazard: dotted arrow; static-1 logic hazard: solid arrow

wx
yz 00 01 11 10
x
00 1 y 1

w 1
01 1 1 x
f
11 1 1 1 y 1
z

10 1 1 1 1 w 1
z

7
Getting Rid of the Static-1 Logic Hazard

Example (contd.): cover the solid arrow with a cube to get rid of the static-1
logic hazard

wx
yz x
00 01 11 10
y 1
00 1
w 1
x
01 1 1
y 1 1
z
11 1 1 1
w 1
z
10 1 1 1 1
w 1 1
y 1

Avoiding a static-0 logic hazard is trivial: just as in the SIC case

8
MIC Dynamic Hazards
Example: solid arrow

wx
yz 00 01 11 10 x 0 0
y 1
00 1
w
x 1
01 1 1
y 1
z f
11 1 1 1
G1
w
10 1 1 1 1 z

w
y 1

Necessary condition for the dynamic transition to be hazard-free

• Make sure each of its 1->1 subtransitions is also hazard-free: ensured by
including these subtransitions in some product of the sum-of-products
realization
• Subtransitions: [1110,1111], [1110,0110] – called required cubes of the
dynamic transition
– Necessary condition met in this example for these required cubes 9
 Getting Rid of the Dynamic Hazard
Ensure that no AND gate turns on during the MIC transition
• G1 temporarily turns on because product wz intersects the dynamic
transition 1110 -> 0111: called illegal intersection
• Dynamic transition called a privileged cube
• During this transition: inputs could be momentarily at 1111, which is a
minterm of wz
• Disallow illegal intersections of privileged cubes: reduce wz to wy’z

wx x 0 0
wx x 0 0
yz yz 00 01 11 10 y 1
00 01 11 10 y 1
00 1 w 00 1 w
x 1 x 1
01 1 1 01 1 1 y 1
y 1 f
z f z
11 1 1 1 G1 11 1 1 1
w w 0 0
y
z z
10 1 1 1 1 10 1 1 1 1
w w
y 1 y 1

10
Eliminating Hazards for an MIC Transition

1->1 MIC transition: must be completely covered by a product term

0->0 MIC transition: does not lead to a hazard

1->0 (0->1) MIC transition: ensure that every product term that intersects
the MIC transition also contains its starting (end) point

To obtain a hazard-free sum-of-products implementation H of function f,

ensure:
• Each required cube is contained in some implicant of H
• No implicant of H illegally intersects any specified dynamic transition
– Such an implicant is called a dynamic-hazard-free implicant
(dhf-implicant)
– A dhf-prime implicant is a dhf-implicant not contained in any other dhf-
implicant
• This problem requires that we only make use of dhf-prime implicants while
covering every required cube in sum-of-products minimization
– Similar to Quine-McCluskey minimization 11
 Deriving a Hazard-free Sum-of-products

Example:
wx wx wx
yz 00 01 11 10 yz 00 01 11 10 yz 00 01 11 10

00 0 0 1 1 00 0 0 1 1 00 0 0 1 1

01 0 1 1 1 01 0 1 1 1 01 0 1 1 1

11 1 1 1 1 11 1 1 1 1 11 1 1 1 1

10 1 0 1 1 10 1 0 1 1 10 1 0 1 1

(a) Required cubes. (b) Privileged cubes. (c) Prime implicants with no
illegal intersections.
wx wx
yz 00 01 11 10 yz 00 01 11 10

00 0 0 1 1 00 0 0 1 1

01 0 1 1 1 01 0 1 1 1

11 1 1 1 1 11 1 1 1 1

10 1 0 1 1 10 1 0 1 1
Hazard-free sum-of-products:
(d) Prime implicant xz has an (e) Prime implicant xz reduced to w + yz + x’y + xy’z
illegal intersection. dhf-prime implicant xy z.
12
Hazard-non-increasing Logic
Transformations
Hazard-non-increasing logic transformations: used to derived hazard-free
multi-level realization from hazard-free two-level realization
• If the initial circuit is hazard-free: so is the final multi-level circuit
• Associative law and its dual: (x + y) + z  x + (y + z); (xy)z  x(yz)
• De Morgan’s theorem and its dual: (x + y)’  x’y’; (xy)’  x’ + y’
• Distributive law: xy + xz => x(y + z)
• Absorption law: x + xy => x
• x + x’y => x + y law
• Insertion of inverters at primary inputs and circuit output
Example: AND-OR realization free of dynamic hazard for 1110 -> 0111
• So is the multi-level realization: x’y + wx + yz’ + wy’z + wy = (x’ + z’ + w)y
+ wx + wy’z
x 0 0
wx y 1 x
yz z
00 01 11 10 w
w
1
00 1 x 1 y

y 1 w 0
01 1 1 z f y f
z
w 0 0
11 1 1 1 y w
z x
w 13
10 1 1 1 1
y 1
Synthesis of SIC Fundamental-mode
Circuits
Flow table: analogous to the state table

Example: Consider a sequential circuit with two inputs x1 and x2 and one
output z. The initial input state is x1 = x2 = 0. The output value is
to be 1 if and only if the input state is x1 = x2 = 1 and the
preceding input state is x1 = 0, x2 = 1
x1 10
x2 10
z 10
1 2 4 5 2 3
Input-output sequences

14
Partial flow table Primitive flow table
 Reduction of Flow Tables
Reduction of primitive flow table has two functions:
• Elimination of redundant stable states
• Merging those stable states which are distinguishable by input states

Example: Rewrite primitive flow table like a state table

1

5 2

4 3
Merger graph
Maximal compatibles: {(123), (145)}

Reduced flow tables

15
Specifying the Output Symbols
Assignment of output values to the unstable states in the reduced flow
table
• When the circuit is to go from one stable state to another stable state
associated with the same output value: assign the same output value to
the unstable state en route to avoid a momentary opposite value
• When the state changes from one stable state with a given output value to
another stable state with a different output value: the transition may be
associated with either of these output values
– When the relative timing of the output value change is of no
importance: choose the output value so as to minimize logic

16
Excitation and Output Tables
Example: Reduced flow table Excitation and output table

x1 x2
Y = x1x2’ + x1y
z = x1x2y’ Y
D
y

17
Synthesis Procedure
Synthesis procedure for SIC fundamental-mode asynchronous circuits:
1. Construct a primitive flow table from the verbal description: specify only
those output values that are associated with stable states
2. Obtain a minimum-row reduced flow table: use either the merger graph or
merger table for this purpose
3. Assign secondary variables to the rows of the reduced flow table and
construct excitation and output tables: specify output values associated
with unstable states according to design requirements
4. Derive excitation and output functions, and the corresponding hazard-free
circuit

18
Synthesis Example
Example: Design an asynchronous sequential circuit with two inputs, x1
and x2, and two outputs, G and R, as follows.
• Initially, both input values and both output values are 0
• Whenever G = 0 and either x1 or x2 becomes 1, G becomes 1
• When the second input becomes 1, R becomes 1
• The first input value that changes from 1 to 0 turns G equal to 0
• R becomes 0 when G is 0 and either input value changes from 1 to 0

19
Synthesis Example (Contd.)
Merger graph Reduced flow table Excitation and output table

1
6 2

5 3
4

Y = (x1 + x2)y + x1x2

G = (x1 + x2)y’ + x1x2
R = y + x1x2

20
Races and Cycles
Assignment of the secondary variable values to the rows of the reduced flow
table should be such that: the circuit will operate correctly even if
different delays are associated with the secondary elements
Race: where a change of more than one secondary variable is required
• Noncritical race: the final state does not depend on the order in which the
secondary variables change
• Critical race: the final state reached depends on the order in which the
secondary variables change – must always be avoided
• Races can sometimes be avoided by directing the circuit through
intermediate unstable states
– Cycle: circuit goes through a unique sequence of unstable states

Y1Y2
y1y2 x1x2
00 01 11 10

00 11 00 10 01
01 11 00 11 01
11 11 00 10 11
10 11 10 10 11

21
Illustration of races and cycles Valid assignment that eliminates critical races
Methods of Secondary Assignment
Valid state assignment: avoids critical races and undesired cycles

Adjacent states: states whose assignments differ in only one variable

Example: Flow table Transition diagram

(10) (00)

c (11) b

Column 00: Row b must be adjacent to row a

Column 01: Rows a and b must be adjacent to row c
Column 11: Row c must be adjacent to row b
Column 10: Row c must be adjacent to row a
If noncritical races are permitted: column 01 requirement may be eliminated 22
Secondary Assignment (Contd.)
Avoiding all races: not possible when the transition diagram is a triangle
• Use augmented flow table
Y1Y2 Y1Y2
y1y2 x1x2 y1y2 x1x2
00 01 11 10 00 01 11 10

a 00 00 10 00 00 a 00 00 01 00 00
b 01 00 11 01 01 b 01 00 11 01 01
c 11 11 11 01 10 c 11 11 11 01 10
c 10 10 10 11 00 10 -- -- -- 00

(a) Two assignments to row c. (b) Utilizing an unspecified

entry as an unstable state.
Example: Augmentation of the flow table may require an increase in the
number of secondary variables yyy xx
State
1 2
1 2 3
00 01 11 10
y1y2
(11) y3 00 01 11 10 a 000 1 2 4 6
a b b 001 1 3 4 7
0 a c d d 011
(01) (01) c 010 1 2 5 8
(10) 1 b d 110 5
c d 111
(11) 101 3
d 100 1 3 5 6
23
Flow table Transition diagram Race-free flow table
Synthesis of Burst-mode Circuits
MIC fundamental-mode machines: several inputs change in a narrow time
interval and no further inputs change values until the machine has
stabilized
• Narrow time interval: still quite restrictive
Burst-mode machines: also allow several inputs to change values
concurrently
• However, all the changes need not occur in a narrow time interval
• They can monotonically change in any order at any time within a given
input burst and respond with a set of output value changes, called the
output burst
Burst-mode specification: initial values of inputs and outputs can be
specified or just assumed to have a default value of 0

A
x1+,x2+/ x1-/z2-
z1+,z2+

B D

x1+,x2-/
x1-/z2- 24
z1-,z2+
C
Burst-mode Specification Restrictions

Restrictions on burst-mode specifications:

• Non-empty input bursts: if no input undergoes a transition, the machine
remains in its current state
• Maximal set property: no input burst on an outgoing arc from any state
must be a subset of an input burst on another outgoing arc from the same
state
• Unique entry point: each state should have a unique set of input and
output values through which it is entered

Example: Assume in starting state A, x1x2 = 00 and z1z2 = 00

• B: 11/11
A
• C: 01/10 x1+,x2+/ x1-/z2-
• D: 10/01 z1+,z2+

B D

x1+,x2-/
x1-/z2-
z1-,z2+
C

25
Flow Table
Example (contd.): Specification Flow table

A
x1+,x2+/ x1-/z2-
z1+,z2+

B D

x1+,x2-/
x1-/z2-
z1-,z2+
C

Complete state: the state the machine goes to and corresponding output
values
Flow table for a burst-mode specification does not have any function
hazards: since the complete state does not change until the full
input burst has arrived
• It is always possible to obtain a hazard-free sum-of-products realization H
for each secondary variable and output: since for each such variable, the
required cube can be included in some product of H and no product of H
illegally intersects any privileged cube because all transitions in any row of
the flow table have the same complete start state which will be included in
the required cubes for these transitions 26
Synthesis Example
Example: Specification Transition diagram State assignment
y1
A y2 0 1
A D
x1+,x2+/ x1-/z2-
z1+,z2+ 0 A D

B D 1 B C
B C
x1+,x2-/
x1-/z2-
z1-,z2+
C

Excitation and output table

27
Synthesis Example (Contd.)
x1x2 dhf-prime Required cubes
Y1,Y2: y1y2 00 01 11 10 implicants x1x2y2 y1y2 x1x2y1

00 0 0 0 0 x1y2

x2y2
01 1 0
y1y2

11 1 1 1 1 x1y1

10 0 1 x2y1

Minimal hazard-free sum-of-products

Y1 map Y1 = x1y2 + y1y2 + x1y1

x1x2 dhf-prime Required cubes

y1y2 00 01 11 10 implicants x1x2y1 x2y1y2 x1x2y2 x2y1y2 x1y1y2

1 0 x1x2y1
00 0 0
y1y2
01 1 1
x1y2

11 1 1 1 0 x2y2

10 0 0 x2y1

Minimal hazard-free sum-of-products 28

Y2 map Y2 = x1x2y1 + x1y2 + x2y2
Synthesis Example (Contd.)
z1,z2: x1x2
y1y2 00 01 11 10

00 0 0 1 0

01 1 1
Minimal hazard-free sum-of-products
z1 = Y2 = x1x2y1 + x1y2 + x2y2
11 1 1 1 0

10 0 0

z1 map

x1x2
y1y2 00 01 11 10 dhf-prime Required cubes
implicants x1x2y1 x1x2y1
00 0 0 1 0
x1x2y1
01 0 1 x1y1y2

0 0 0 1 x1x2y1
11
x1y1y2
10 0 1
x1x2y2

z2 map 29
Minimal hazard-free sum-of-products
z2 = x1x2y1 + x1x2y1
Synthesis Example (Contd.)
Synthesized circuit:
x1 x2
z1

Y2 y2
D

Y1 y1
D

z2

30