Lecture 52: Asynchronous Sequential Circuits (Part 1)

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
 Introduction
• Asynchronous circuits do not rely on clock; rather they exploit the delays of the
gates and other circuit elements for their operation.
• Within larger synchronous systems, it is often desirable to allow certain
subsystems to operate asynchronously to reduce delay and power
consumption.
• Structure of an asynchronous circuit:
– Delay elements in place of flip-flops.
– The combination of signals that appear at the primary input and delay outputs
define the total state.

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 X1 Z1
X2 Z2 • Input state:
Combinational  combination of input signals X1, X2,
Xl Zm …, Xl.
Circuit
• Secondary or internal state:
 combination of signals at the
Next outputs of the delay elements y1,
Current State
State y2, …, yk.
delay • Secondary or internal variables:
y1 Y1
 y1, y2, …, yk
y2 delay Y2
• Excitation variables:
 Y1, Y2, …, Yk
yk delay Yk

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 Definition
• Stable state:
– For a given input state, the circuit is said to be in a stable state if and only if yi = Yi
for i = 1, 2, …, k.
• In response to a change in the input state, the combinational logic produces a
new set of values for the excitation variables, entering an unstable state.
• When the secondary variables assume their new values (when y’s become
equal to the corresponding Y’s), the circuit enters its next stable state.
• Thus, a transition from one stable state to another occurs only in response to a
change in the input state.

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 Modes of Operation
• Fundamental mode of operation:
– When a change in input values has occurred, no other change in any input value
occurs until the circuit enters a stable state.
• Two types:
– Single-input change (SIC) fundamental mode: a single input value is allowed to
change at a time.
– Multiple-input change (MIC) fundamental mode: multiple input values can change
at a time.

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 Hazards
• Hazards (glitches) cause some unwanted transition(s) in the output(s) before
settling down to stable value(s).
• Two types of hazards:
a) Logic hazard: caused by non-instantaneous changes in circuit signals.
b) Function hazard: inherent in the functional specification.
• Can result in erroneous behaviour:
– The glitches when fed to some other circuit may result in incorrect behaviour.

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 Design of SIC Hazard-Free Circuits
• Example: T(x,y,z) = Σ (2,3,5,7)
– Static-1 logic hazard (SIC).
x
xy x G1 y 1
z 00 01 11 10
y 1
x 1 T
0 1 z 1
T
1 1 1 1 G2 y 1 1
x z 1
z 1
(a) Map for T = x y + xz.
(b) Gate network. (c) SIC hazard-free network

• Adjacent combinations: differ in the value of a single variable.

– For example, x’yz and xyz.

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• SIC Static Logic Hazard:
– Transition between a pair of adjacent input combinations, which correspond to
identical output values, that may generate a momentary spurious output value.
– Occurs when no cube in the K-map contains both combinations.
• Solution: cover both combinations with a cube.

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 Transition and Required Cubes
• Transition cube [m1,m2] is a set of all minterms that can be reached from
minterm m1 and ending at minterm m2.
– Example: Transition cube [010,100] contains minterms: 000, 010, 100, 110
• Required cube is a transition cube that must be included in some product of
the sum-of-products realization in order to get rid of the static-1 logic hazard.
– Example: Required cube is [011,111]. z
xy
00 01 11 10

0 1

1 1 1 1

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 Static-0 / Dynamic Hazard
• Since in the sum-of-products realization of a function, no cube for any product
term can contain either of the two input combinations involved in a 0 → 0
output transition, a static-0 logic hazard can only occur if a product term has
both xi and xi’ as input literals.
– Since there is no need to include such products, such hazards can be avoided.
• During a 0 → 1 output transition, if the 0 may change to 1 and then 0 and
finally stabilize at 1, then the sum-of-products realization is said to have a
dynamic 0 → 1 logic hazard.
– A dynamic 1 → 0 hazard can be similarly defined.
– Dynamic hazards are not possible under the SIC scenario.

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END OF LECTURE 52

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