Lecture-6: VLSI Physical Design Automation

Lecture-6
VLSI Physical Design

Automation
Introduction to Routing
• In the placement phase,
 the exact locations of circuit blocks and
 pins are determined.
• A netlist is also generated which specifies the
required interconnections.
• Space not occupied by the blocks can be viewed as
a collection of regions.
• These regions are used for routing and are called
as routing regions.
• The process of finding the geometric layouts of all
the nets is called routing.
• Nets must be routed within the routing regions. In
addition, nets must not short-circuit, that is, nets
must not intersect each other.
The inputs to the
general routing problem
•
. Netlist,
1
• 2. Timing budget for nets, typically for

critical nets only,
• 3. Placement information including
location of blocks, locations of pins on
the block boundary as well as on top due to
ATM model (sea-of-pins model), location of I/O
pins on the chip boundary
• 4. RC delay per unit length on each metal
layer, as well as RC delay for each type
of via.
Objective of the routing
problem
• dependent on the nature of the chip.
• For general purpose chips, it is sufficient
to minimize the total wire length, while
completing all the connections.
• For high performance chips, it is important
to route each net such that it meets its
timing budget. Usually routing involves
special treatment of such nets as clock
nets, power nets and ground nets.
• In fact, these nets are routed separately by
special routers.
Computationally hard
problem
• A VLSI chip may contain several
million transistors.
• As a result, tens of thousands of nets
have to be routed to complete the
layout.
• In addition, there may be several
hundreds of possible routes for each
net.
• This makes the routing problem
computationally hard.
One Phase Routing
• One approach to the general routing
problem is called Area Routing
• It is a single phase routing technique.
This technique routes one net at a time
considering all the routing regions.
• However, this technique is
computationally infeasible for an entire
VLSI chip.
• It is typically used for specialized
problems, and smaller routing regions.
Two phases of Routing
• The first phase is called global

routing
• generates a ‘loose’ route for
each net
• In fact it assigns a list of
routing regions to each net
without specifying the actual
geometric layout of wires
detailed routing
• The second phase, which is

called detailed routing,
• finds the actual geometric
layout of each net within the
assigned routing regions
Global routing: three
distinct phases
• Region definition,
• Region Assignment, and
• Pin assignment.
• The first phase: partition the entire routing
space into routing regions.
• This includes spaces between blocks and
above blocks.
• Between blocks there are two types of
routing regions: channels and 2D-
switchboxes.
• Above blocks, the entire routing space is
available, however, we partition it into
smaller regions called 3D-switchboxes.
Capacity of a channel
• Each routing region has a capacity, which
is the maximum number of nets that can
pass through that region.
• The capacity of a region is a function of
the design rules and dimensions of the
routing regions and wires.
• A channel is a rectangular area bounded by
two opposite sides by the blocks.
• Capacity of a channel is a function of the
number of layers (l), height (h)
The
two
phase
routing
flow
Basics of Headlock
Hadlock observed that the length of a path (P)
connecting source and target can be given by M(s, t)
+2d(P) , where M(s, t) is Manhattan distance between
source and target and (P) is the number of vertices on
path P that are directed away from the target. The
length of P is minimized if and only if d is minimized
as M(s, t) is constant for given pair of source and
target. This is the essence of Hadlock’s algorithm.
The exploration phase, instead of labeling the
wavefront by a number corresponding to the distance
from the source, uses the detour number. The detour
number of a path is the number of times that the path
has turned away from the target.
Example of Headlock
Example of HeadLock’s
Router
Two phases of Routing

Lecture-6: VLSI Physical Design Automation

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Lecture-6: VLSI Physical Design Automation

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Lecture-6

VLSI Physical Design

• 2. Timing budget for nets, typically for

• The first phase is called global

• The second phase, which is

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