Routing: by Manjunatha Naik V Asst. Professor Dept. of ECE, RNSIT

ROUTING
By
Manjunatha Naik V
Asst. professor
Dept. of ECE, RNSIT
Routing :
• Once the designer has floorplanned a chip and the logic cells within the
flexible blocks have been placed, it is time to make the connections by
routing the chip.
• This is still a hard problem that is made easier by dividing it into smaller
problems.
• Routing is usually split into global routing followed by detailed routing .
Global Routing
• The input to the global router is a floorplan that includes the locations
of all the fixed and flexible blocks.
• The placement information for flexible blocks and the locations of all
the logic cells.
Goals :
• The goal of global routing is to provide complete instructions to the
detailed router on where to route every net.
Objectives of global routing :
• Minimize the total interconnect length.
• Maximize the probability that the detailed router can complete the
routing.
• Minimize the critical path delay.
Routing methods
• Algorithms can be classified into sequential and concurrent approaches,
• Sequential global routing Perhaps the most straightforward strategy for
routing is to select a specific net order and then to route nets sequentially
in that order.
• However, this sequential approach often leads to a poor routing result,
because an earlier routed net might block the routing for its subsequent
nets. Therefore, the quality of the routing solution greatly depends on the
net ordering.
Sequential routing
• One of the approach for global routing picks up each
net in turn and calculates the shortest path using tree
algorithms also known as Sequential routing
• As this algorithm proceeds, some channels will become
more congested since they hold more nets than others.
• There are two different ways that a global router
handles this congestion problem.
1. Using order-independent and
2. Order-dependent routing.
Routing for different net orderings,
(a) One layer routing case with two two-pin nets 1 and 2,
(b) Net ordering of 1 followed by 2 and it is inferior solution,
(c) A better solution by net ordering 2 followed by 1.
There are some popular net-ordering schemes as follows:
(1) Order the nets in the ascending order according to the number of
pins within their bounding boxes.
(2) Order the nets in the ascending or descending order of their
lengths if routability is the most critical issue.
Research shows that routing shorter nets first often leads to better
routability.
(3) Order the nets on the basis of their timing criticality.
Other method hierarchical (top down and bottom up)

Concurrent routing
• The major drawback of the sequential approach is that it suffers from the
net ordering problem.
• In any net ordering scheme, it is more difficult to route the nets that are
processed later, because they are subjected to more blockages.
• Moreover, when the sequential routing does find a feasible solution, we do
not know whether or not this solution is optimal or how far it is from the
optimal solution.
• One popular concurrent approach is to formulate global routing as a 0-1
integer linear programming algorithm
Global Routing Between Blocks
Global routing for a cell-based ASIC formulated as a graph problem.

(a) A cell-based ASIC with numbered channels.
(b) The channels form the edges of a graph.
(c) The channel-intersection graph. Each channel corresponds to an edge on a
graph whose weight corresponds to the channel length.
Back-annotation
• Used in connection to netlist simulations and STA where the
propagation delay(s) through each cell in the netlist is overridden by
the delay value(s) specified in a special file called sdf (synopsys delay
format) file.
• The process of putting delays from a given source for the cells in a
netlist during netlist simulation is called Back Annotation.
• Normally the values of the delays corresponding to each cell in the
netlist would come from the simulation library
i.e verilogmodel of library cells.
• But those delays are not the actual delays of cells, as each of them is
instantiated in a netlist in different surroundings, different physical
locations, different loads, different fan in.
• The delay of two similar cells in the netlist at two different physical
locations in a chip can be significantly different depending upon above said
factors.
• Therefore in order to have actual delays for the cells in your netlist, an SDF
is written out, by a EDA tool can be a synthesis tool or a layout tool etc..
• which contains the delays of each instance of each library cell in the
netlist, under the circumstances the cell is in.
• During simulations or Static Timing Analysis, each cell in the netlist gets its
correponding delay read, or more technically 'annotated' from the SDF
file.
Detailed Routing
• The global routing step determines the channels to be used
for each interconnect.
• Using this information the detailed router decides the exact
location and layers for each interconnect.
• Various Rules used to determine the m1 routing pitch ( track
pitch , track spacing , or just pitch ). We can set the m1 pitch to
one of three values:
1. via-to-via ( VTV ) pitch (or spacing),
2. via-to-line ( VTL or line-to-via ) pitch, or
3. line-to-line ( LTL ) pitch.
The metal routing pitch.
(a) An example of metal design rules for m1 and via1 (m1/m2 via).
(b) Via-to-via pitch for adjacent vias.
(c) Via-to-line (or line-to-via) pitch for nonadjacent vias.
(d) Line-to-line pitch with no vias.
Goals and Objectives
Goal:
To complete all the connections between logic cells
Objectives:
1. The total interconnect length and area
2. The number of layer changes that the connections have to make
3. The delay of critical paths
Measurement of Channel Density
The definitions of local channel density and global channel density.

Lines represent the m1 and m2 interconnect in the channel to
simplify the drawing.
Left-Edge Algorithm
Left-edge algorithm.
(a) Sorted list of segments.
(b) Assignment to tracks.
(c) Completed channel route
(with m1 and m2 interconnect
represented by lines).
Routing graphs.
(a) Channel with a global density of 4.
(b) The vertical constraint graph.
If two nets occupy the same column,
the net at the top of the channel
imposes a vertical constraint on the net
at the bottom.
For example, net 2 imposes a vertical
constraint on net 4. Thus the
interconnect for net 4 must use a track
above net 2.
(c) Horizontal-constraint graph.
If the segments of two nets overlap,
they are connected in the horizontal-
constraint graph. This graph determines
the global channel density.
The addition of a dogleg, an extra trunk, in the wiring of a
net can resolve cyclic vertical constraints.
Area-Routing Algorithms
The Lee maze-running algorithm:
• The algorithm finds a path from source (X) to target (Y) by emitting
a wave from both the source and the target at the same time.
• Successive outward moves are marked in each bin.
• Once the target is reached, the path is found by backtracking (if
there is a choice of bins with equal labeled values, we choose the
bin that avoids changing direction).
Hightower area-routing algorithm
(a) Escape lines are constructed from source (X) and target (Y) toward each
other until they hit obstacles.
(b) An escape point is found on the escape line so that the next escape line
perpendicular to the original misses the next obstacle.
The path is complete when escape lines from source and target meet.
Timing-Driven Detailed Routing
• the global router has already set the path the interconnect will follow and
little can be done to improve timing
• reduce the number of vias
• alter the interconnect width to optimize delay
• minimize overlap capacitance
• gains are small
• high-frequency clock nets are chamfered (rounded) to match impedances
at branches and control reflections at corners.
Special Routing
Clock Routing
• clock-tree synthesis • clock-buffer insertion • activity-induced
• clock skew
Clock routing.
(a) A clock network for a cell-based ASIC.
(b) Equalizing the interconnect segments between CLK and all destinations (by
including jogs if necessary) minimizes clock skew.
Power Routing
• Power-bus sizing
• Metal electro migration
• Power simulation
• Mean time to failure (MTTF)
• Metallization reliability rules
• Maximum metal-width rules (fat-metal rules)
• die attach
• power grid
• end-cap cells
• routing bias
Circuit Extraction and DRC
• standard parasitic format (SPF) • regular SPF • reduced SPF • detailed SPF
The regular and reduced standard parasitic format (SPF)
models for interconnect.
(a) An example of an interconnect network with fanout.
The driving-point admittance of the
interconnect network is Y(s).
(b) The SPF model of the interconnect.
(c) The lumped-capacitance interconnect model.
(d) The lumped-RC interconnect model.
(e) The PI segment interconnect model
(notice the capacitor nearest the output node is labeled
C2 rather than C1).
The values of C, R, C1, and C2 are calculated so that
Y1(s), Y2(s),
and Y3(s) are the first-, second-, and third-order Taylor-
series approximations to Y(s).
Design Checks
• Design-rule check (DRC)
1. Phantom-level DRC
2. Hard layout
3. Dracula deck
• Layout versus schematic (LVS)

Routing: by Manjunatha Naik V Asst. Professor Dept. of ECE, RNSIT

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Routing: by Manjunatha Naik V Asst. Professor Dept. of ECE, RNSIT

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ROUTING

Other method hierarchical (top down and bottom up)

Global routing for a cell-based ASIC formulated as a graph problem.

The definitions of local channel density and global channel density.

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