DMA CONTROLLER 8257/8237

INTRODUCTION

❏In microprocessors, efficient data transfer is vital hence various ways to

improve this have been developed eg DMA controllers

❏In cases where we may have faster peripheral devices, we employ the
use of the DMA controller and disconnect the microprocessor during a
DMA operation
 INTRODUCTION

❏This is important, especially for systems that prioritize speed as it allows for
high-speed data transfer and frees up the microprocessor to perform other
tasks while the DMA controller handles data transfer between memory and
I/O devices
❏The DMA controller in a sense, is a second processor in the system but it is
dedicated to an I/O function.
❏A DMA controller temporarily borrows the address bus, data bus and
control bus from the microprocessor, and transfers the data bytes directly
from the IO ports to a series of memory locations or vice versa.
 Direct Memory Access

❏ What is DMA?

❏ Direct memory access (DMA) is an operation in which data is copied

(transported) from one resource to another resource in a computer
system without the involvement of the CPU.
 Direct Memory Access:Sequence of events

❏ A device (peripheral, CPU) requests a controller to transfer information;

❏The controller request control over the buses from the CPU by asserting
the HOLD signal;
❏The CPU upon receiving the HOLD signal will respond in a few clock cycles
by suspending program execution, placing all buses in high impedance
state, and acknowledging the request by asserting HLDA;
❏The DMA controller has control over the buses
 Functional Behaviour of the DMA Controller

1) DMA Initialization - DMA controllers require initialization by software

hence microprocessor sends the following information to the DMA
controller:
(a) Beginning address in memory
(b) Block length (number of words to transfer)
(c) Direction (memory-to-device or device-to-memory)
(d) Port ID
(e) End of block action (interrupt request or no interrupt request)
Functional Behaviour of the DMA Controller

2. The processor delegates data transfer to the DMA controller and

resumes other tasks.
3. The DMA controller synchronizes memory access with the processor
by either disabling the processor immediately, requesting a halt and
waiting for acknowledgement, or timing the access to the processor's
idle cycle.
4. The DMA controller uses the same control signals as the processor
when accessing I/O ports or memory. Dedicated lines can be used for I/O
port activity without synchronization.
Functional Behaviour of the DMA Controller

5. Upon completing the block transfer, the DMA controller raises an

interrupt request or indicates completion in its status register,
depending on interrupt settings.

6. The processor recognizes I/O completion through an interrupt or

by reading the status register and proceeds with post-completion
activities typical for any I/O port.
DMA Controller 8257
Pin Configuration of 8257
 Pin description of 8257

❏ CLK - Clock input to 8257

❏ CS– Is a logic low input chip select signal during the programming mode.
❏ RESET - Reset input to 8257 connected to the system reset, when the RESET signal
goes high all the internal registers are cleared.
❏ READY - Ready input signal which when low, the 8257 enters a wait state. This is used
to get extra time in DMA machine cycles to transfer data between slow memory and
IO devices.
❏ HRQ - Hold request output signal. It is the hold request signal sent to the processor
HOLD pin to make a request for the bus to perform a DMA transfer.
❏ HLDA - Hold acknowledge input signal. The hold acknowledge signal sent by the
processor to inform the acceptance of a hold request.

❏ DREQ0 - DREQ3 - DMA request inputs (Four channel inputs). Used by IO devices to
request DMA transfer

❏ DACK0 - DACK3 - DMA acknowledge output signals. These are active low-output signals
from 8257 to the IO devices to inform the acceptance of a DMA request

❏ D0 - D7 - Data bus lines. Used for data transfer between the processor and the DMA
controller during the programming mode. During the DMA mode, these lines are used
as multiplexed high-order address and data lines.
❏IOR - Bidirectional IO read control signal. It is the input control signal for reading DMA
controller during the programming mode and the output control signal for reading IO
device during the DMA (memory) write cycle. Is active low

❏IOW - Bidirectional IO writes control signal. It is the input control signal for writing the
DMA controller during the programming mode and output control signal for writing the IO
device during the DMA (memory) read cycle. Is active low

❏TC - Terminal count. This output notifies the currently selected peripheral that the
present DMA cycle should be the last cycle for this data block

❏ MARK - Modulo-128 mark. This signal is sent by the DMA controller after every 128-
byte of data transfer.
❏A3 to A0 - Four bidirectional address lines. Used as input address during
programming mode to select internal registers. During DMA mode the low-order four
bits of memory address are output by 8257 on these lines.

❏A7 to A4 - Four unidirectional address lines. Used to output the memory address bits
A7 to A3 during the DMA mode.

❏AEN - Address enable output signal. It is used to enable the address latch connected
to D7 - D0 pins of 8257. It is also used to disable any buffers in the system connected to
the processor.

❏ADSTB - Address strobe output signal. It is used to latch the high-byte memory
address issued through D7 - D0 lines by 8257 during the DMA mode into an external
latch.
►MEMR - Memory read control signal. It is an output control signal issued during the
DMA read operation. Is active low

►MEMW - Memory write control signal. It is an output control signal issued during the
DMA write operation. Is active low
 Functional Block Diagram of 8257

► The block diagram of 8257 is shown below and consists of the following parts:

1. DMA channels 4. Control logic

2. Data bus buffer 5. Priority resolver

3. Read/write logic 6. Mode set register

7. Status registers.
► DMA channels – has 4 channels each with two programmable 16-bit registers.

► One register (DMA Address register) is used to program the starting address of the memory
location for DMA data transfer. Its format is as shown below:

► Another register (terminal count register is used to program a 14-bit count value and a 2-bit
code for the type of DMA transfer (Read/Write/Verify transfer). Its format is as shown
below:

 The address in the address register is automatically incremented after every

read/write/verify transfer.
 Data Bus Buffer:
❏The Data Bus Buffer is an 8-bit buffer that interfaces the 8257 DMA controller to
the system data bus.
❏In slave mode, it acts as the Do-D7 data lines.
❏In master mode, it functions as the higher-order address lines A8-A15.
Read/Write Logic:
❏The Read/Write Logic handles the communication between the microprocessor
and the 8257 DMA controller.
❏In slave mode, it accepts I/O read (IOR) or I/O write (IOW) signals, decodes the
address bits, and performs read or write operations on the addressed registers.
❏In master mode, it generates the necessary I/O read and memory write or I/O
write and memory read signals for data transfer with the peripheral device
granted the DMA cycle
► Control Logic:
• In master mode, the Control Logic is responsible for managing the sequence of
operations during all DMA cycles.
• It generates the necessary control signals and addresses to specify the memory
location to be accessed.
• In slave mode, the Control Logic is disabled as the DMA controller acts as a
slave device on the system bus.
► Priority Resolver:
• The Priority Resolver is a logic circuit within the DMA controller.
• Its role is to resolve the priority of each DMA channel.
• The priority of the channels can be set as fixed (default priority) or rotating
priority.
• The mode set register is used to configure and define the desired priority
scheme for the channels.
Mode set register
► When set, the various bits in the mode set register enable each of the four DMA
channels, and allow four different options for the 8257 as shown below:

► The Mode Set Register is cleared by the reset input.

► Clearing the register disables all operating modes and channels of the 8257, preventing
bus conflicts during power-up.
► It is crucial not to leave a channel enabled unless the DMA address and terminal count
registers contain valid values.
► Enabling a channel without valid values could lead to unintended DMA requests from
peripherals, initiating a DMA cycle that could potentially corrupt memory data.
►Status register - The status register indicates which channels have reached
a terminal count condition.
►Terminal count (TC) status bits are set when the terminal count output is
activated for a specific channel.
►The TC status bits remain set until the status register is read or the 8257
DMA controller is reset.
►The update flag, separate from the TC status bits, can be cleared in several
ways: resetting the 8257, changing to the non-auto load mode, or allowing
it to clear itself at the end of the update cycle
►The status register serves as a valuable resource for monitoring channel
status and ensuring proper data block transfers within the DMA system.
 PROGRAMMING AND READING THE 8257
REGISTERS
❑The microprocessor generates read or write signal (IOR or IOW) and places a
16 bit address on the system address bus.
❑12 address bits A4-A15 are decoded to produce the chip select input to the
8257.
❑Address line A3 specifies whether a channel register or status register is to
be accessed.
•A3= 0 → channel register
•A3=1 → status register/mode set register.
PROGRAMMING AND READING THE 8257
REGISTERS
❑Address line A0 indicates whether channel register is being accessed or
terminal count register.
A0 = 0 → channel register
A0 = 1 → terminal count register
❑A1 and A2 will specify one of the four channels.

❑Note that A0-A2 are all zeros when accessing the status or mode set
register.
PROGRAMMING AND READING THE 8257
REGISTERS
❑Since channel registers are 16 bits, two cycles are required to read or
write and hence there is a first/last flip-flop(F/L) which indicate whether
the upper or lower byte of register operation is taking place.

• F/L=1 →MSB
• F/L=0 → LSB
PROGRAMMING AND READING THE 8257
REGISTERS
DMA OPERATIONS
DATA TRANSFER
DATA TRANSFER
1. Input device sends a DRQ signal
2. DMA sends HRQ signal to the microprocessor
3. Microprocessor generates HOLDA connected to HOLDA of DMA
4. DMA takes over the bus. DMA generates the control signals and
address signals
5. DMA sends DACK signal to the I/O device
6. When I/O device receives DACK signal and transfers data.
7. DRQ is dropped after completion of data. This causes the HRQ signal
to be dropped as well as the HOLDA signal of the microprocessor.
 SINGLE BYTE TRANSFER
❑ Single byte transfer is initiated by I/O device raising the DRQ line of one
channel of the 8257.If channel is enabled ,HRQ is output to the CPU and the
8257 waits for HOLDA signal of the microprocessor.

❑Once HOLDA is received, the DACK line is activated and the 8257 generates
the read or write command after which byte transfer occurs between the I/O
and memory
CONSECUTIVE TRANSFERS
❑If more than one channel requests service simultaneously the transfer
will occur as a burst does.

❑In burst mode transfer,a low priority channel will be overridden by a

higher priority request.Once the higher priority transfer has
completed,control will return to the lower priority channel.

❑No extra cycles are needed to execute this sequence

CONTROL OVERRIDE
❑The continuous DMA transfer mode can be interrupted by an external
device by lowering the HLDA line.
❑After each DMA transfer,the 8257 samples HLDA to ensure it is still
active.If it is not active,the current transfer by 8257 is completed,lowers
the HRQ line and returns in the idle state
NOT READY
❑Ready pin is used to interface memory or I/O devices that cannot meet
the bus setup times required by 8257.

❑The ready pin in 8257 is sampled and if it is low,the 8257 enters a wait
state.When ready becomes high,the 8257 proceeds to complete the
transfer
OPERATION OF DMA CYCLE: TIMING
DIAGRAM OF 8257
OPERATION OF DMA CYCLE
❑State 1: 8257 places lower byte of memory address on A0-A7 lines and
higher bytes of memory address on D0-D7 lines. It activates AEN signal
at the falling edge and ADSTB signal at the rising edge of S1.

❑State 2:It activates MEMR(DMA read) or IOR(DMA write) at the rising

edge of S2.DACK is activated at the falling edge of S2.
 OPERATION OF DMA CYCLE
❑State 3:Here,the ready signal is sampled. If it is low, a wait state is added
between S3 and S4 otherwise enters into S4.Note that the ready signal is
not sampled during the DMA verify cycle

❑State 4:MEMR,MEMW,IOR and IOW and DACK signals are disabled. It

disables the TC and MARK signals in appropriate DMA cycle. HLDA and
DRQ are sampled. When it finds both HLDA and DRQ high, it resolves
priority of the channels and executes the next DMA cycle for the highest
priority otherwise it enters state 1.
THE 8237 DMA
CONTROLLER
 INTRODUCTION: 8237A DMA CONROLLER
• It is the peripheral interface circuit for microprocessor
systems.
• Designed to allow external devices to transfer information
directly from the system memory.
• Compared to 8257 DMA controller, the 8237 provides the
capability for memory to memory transfer.
• Designed to be used with an external 8-bit address latch, &
• It contains 4 independent channels.
• Each channel, following the EOP(End of Process) can
be programmed to auto-initiate to its initial state.

• Each address has 64Kb address and word count

capability.
 8237 block diagram
• The 8237 has got three logic blocks of control logic.
These are:
- timing control logic,
- the program command control block,
- priority encoder block.
8237 PIN Diagram
• Vcc– it is a 5V supply.
• Vss(GND) –the ground
• CLK input - :Clock Input controls the internal operations of the 8237A
and its rate of data transfers. The input may be driven at up to 5 MHz
for the 8237A-5.
• CS input - chip Select is an active low input used to select the 8237A
as an I/O device during the Idle cycle. This allows CPU communication
on the data bus.
• RESET – is an active high input, it clears the command, status, request,
and temporary registers.
• Ready input – it is used to extend the memory read/write pulses in
8237A so as to accommodate for slow devices.
• HLDA input – (HOLD acknowledge). HLDA input from the cpu indicates
that the cpu has relinquished the control of system buses.
• DREQ0 –DREQ3 input – they are asynchronous channel requests inputs
used by the peripheral devices to obtain DMA services. On fixed priority,
DREQ0 has the highest priority, and DREQ3 has the lowest priority.
• DB0 – DB7 – the data bus lines are bidirectional three state signals
connected to the data bus. The outputs are disabled and the inputs are
read during an I/O Write cycle when the CPU is programming the 8237A
control registers.
• IOR input /output- I/O Read is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to read the
control registers. In the Active cycle, it is an output control signal used by
the 8237A to access data from a peripheral during a DMA Write transfer.
• IOW - Write is a bidirectional active low three-state line. In the Idle
cycle, it is an input control signal used by the CPU to load information
into the 8237A. In the Active cycle, it is an output control signal used by
the 8237A to load data to the peripheral during a DMA Read transfer.
• EOP (input/output) - End of Process is an active low bidirectional
signal. Information concerning the completion of DMA services is
available at the bidirectional EOP pin. The 8237A allows an external
signal to terminate an active DMA service.
• A0 –A3: the four least significant address lines are bidirectional 3 state
signals. In idle state, they are used as inputs by CPU to address the
register to be loaded.
• A4 – A7: Four most significant address lines are three-state outputs and
provide 4 bits of address. These lines are enabled only during the DMA
service.
• HRQ output – is a hold request to the cpu, and is used to request control
of the system buses. If the corresponding mask bit is clear, the presence
of any valid DREQ causes 8237A to issue the HRQ.
• DACK0 – DACK3: Used to notify the individual peripherals when one has
been granted a DMA cycle. The sense of these lines is programmable.
Reset initializes them to active low.
• AEN output: - :Address Enable enables the 8-bit latch containing the
upper 8 address bits onto the system address bus. AEN can also be used
to disable other system bus drivers during DMA transfers. AEN is active
HIGH.
• ADSTB output – (Address strobe). It is used to strobe the upper address
byte into an external latch.
• MEMR/output - The Memory Read signal is an active low three-state
output used to access data from the selected memory location during a
DMA Read or a memory-to-memory transfer.
• MEMW output – it is an active low three-state output used to write
data to the selected memory location during a DMA Write or a
memory-to-memory transfer.
• PIN 5 input - This pin should always be at a logic HIGH level. An
internal pull-up resistor will establish a logic high when the pin is left
floating. It is recommended however, that PIN5 be connected to VCC

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 The timing control block
• The timing control block derives the internal timings
from the clock input
• In the 8237/8257 systems, the internal timings are
provided for by the 8224/8284A systems

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 8237 registers
• In the 8237 DMA controller, there is a total of 24 registers. They
include:
- 4, 16 bit base address register,
- 4, 16 bit base counter register.
- 4, 16 bit current address and
- 4, 16 bit current word count register.
- 1, temporary address register
- 1, 16 bit, temporary word count register
- 1, 8 bit status register
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- 1, 8 bit, command register.
- 1, 8 bit, temporary register.
- 1, 6 bit mode register
- Request register

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 Current address register
• Each of the our channel has its own current address
register
• It hold the values of memory address, during the
Direct Memory Access Transfer.
• After each transfer, the address is automatically
incremented, or decremented, then the intermediate
values of of the address are stored in the current
address register.
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 Current word register
• Each of the four channels have their own current word count
registers.
• It determines the number of transfers to be performs.
• After each transfer, word count is decremented. And during the
transfer, intermediate value of the word count is stored.
• At the end, when the desired number of bytes is transferred, a
Terminal Controller(TC) will be

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Base address, and Base word count register
• Each channel has a pair of base address and base word count register.
They store the original starting address, and the original number of
bytes to be transferred.
• Base registers are written simultaneously with their corresponding
current registers in 8 bit bytes in the program condition by the
microprocessor. Registers cannot be read by the microprocessor.

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 Command register
• Is an 8 bit register that controls the operation of the 8237A.
• It is programmed by the microprocessor, and cleared by reset or a
master clear instruction.

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 Mode Register
• Each of the channels has a 6-bit mode register associated with it.
When the register is being written by the microprocessor in the
program condition, bits 0 and 1 determines which channel modes
register is to be written.

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 Request Register
• The 8237A can respond to requests for DNA services which are
initiated by the software as well as by a DREQ.
• For each channel, there’s a request bit in the 4-bit request register.
They are non maskable, and prioritized by the priority resolver.
• Each register bit is set or reset separately under software control or, it
is cleared upon generation of a TC or external EOP.

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 Mask Register
• It is a write only, 8-bit register.
• Each channel has a mask which can be set to disable the incoming
DREQ.
• The mask in each channel is set when its associated channel produces
an EOP if the channel is not programmed for auto-initialization.
• The entire register can also be set by a rest. This disables all DMA
requests until clear mask register instruction allows them to occue.

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5/19/2023
• It is an 8-bit read only register.
• It indicates which of the channels have reached terminal count and
which of the channels have pending DMA requests.
• Bits 0 – 3 are set every time TC is reached by that channel, or an
external EOP is applied.
• These bits are cleared upon reset, and each status read.
• Bits 4-7 are set whenever their corresponding channel is requesting
for the service.

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Temporary Register
• The temporary register is used to hold data during the memory to
memory transfers.
• After the completion of the transfers, the last word moved can be
read by the microprocessor in the program condition.
• It always contains the last byte transferred in the previous memory-
memory operation, unless cleared by the reset.

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 DMA CYCLES

● The 8237 is designed to operate in two major cycles. These are called Idle and Active
cycles. Each
● device cycle is made up of a number of states. The 8237A can assume seven separate
states, each composed of one full clock period.
● State I (SI) is the inactive state. It is entered when the 8237A has no valid DMA requests
pending. While in SI, the DMA controller is inactive but being programmed by the
processor.
● State S0 (S0) is the first state of a DMA service. The 8237A has requested a hold but the
processor has not yet returned an acknowledge

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 ❏ S1, S2, S3 and S4 are the working states of the DMA service.

❏ If more time is needed to complete a transfer than is available with normal timing,
wait states (SW) can be inserted between S2 or S3 and S4 by the use of the Ready line
on the 8237.

❏ Memory-to-memory transfers require a read-from and a write-to-memory to

complete each transfer.

❏ The first four states (S11, S12, S13, S14) are used for the read from-memory half and
the last four states (S21, S22, S23, S24) for the write-to-memory half of the transfer.

65 DMA OPERATING MODES 5/19/2023

 DMA CYCLES

1.IDLE CYCLE
When no channel is requesting service, the 8237 will enter the Idle cycle and
perform ‘‘SI’’ states. In this cycle the 8237 will sample the DREQ lines every clock
cycle to determine if any channel is requesting a DMA service. The device will also
sample CS, looking for an attempt by the microprocessor to write or read the
internal registers of the 8237.
When CS is low and HLDA is low, the 8237 enters the Program Condition.
 2.ACTIVE CYCLE
When the 8237A is in the Idle cycle and a non-masked channel requests a DMA service,
the device will output an HRQ to the microprocessor and enter the Active cycle. In this
cycle that the DMA service will take place, in one of four modes:

67 DMA OPERATING MODES 5/19/2023

 DMA Operating modes
DMA can operate in 4 modes i.e:
1. Single transfer mode
2. Block transfer mode
3. Demand transfer mode
4. Cascade mode

68 DMA OPERATING MODES 5/19/2023

 1. Single Transfer mode
In this only one channel is used, means only a single DMAC is connected to the bus system.

69 DMA OPERATING MODES 5/19/2023

 2.Block transfer mode

• Once the DMA controller is granted access to the system bus by the CPU, it transfers all
bytes of data in the data block before releasing control of the system buses back to the
CPU, but renders the CPU inactive for relatively long periods of time.
• Data transfer is activated by DREQ to continue making transfer during the service until a
TC or an external EOP is encountered.

70 DMA OPERATING MODES 5/19/2023

 3.Demand Transfer Mode

• Number of bytes to be transferred is controlled by IO

• DMA is programmed for continuous transfer or until DREQ goes active.
• Transfer continues until the IO device has exhausted its data capacity.
• When DREQ signal is disabled the 8237 stores intermediate values of count and address
in count and registers respectively.

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 4. Cascade Mode

• In this multiple channels are used, we can further cascade more number of DMACs.

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 TRANSFER MODES
8237 provides two basic types of transfers:
1. Peripheral Transfer

2. Memory to memory transfer

1. Peripheral Transfer
i. DMA read-transfers data from memory to an I/O device by activating
MEMR and IOW
ii. DMA Write- moves data from an I/O device to the memory by activating
MEMW and IOR
iii. DMA Verify-transfers are pseudo transfers. Ready input is ignored in the
verify mode
2. Memory to memory transfer

• The 8237 transfer data from source memory location to destination memory
location.

• Only channel 0 and 1 are used.

• The address of the source memory is specified by channel 0 address register

whereas destination memory address is specified by the address register of
the channel 1
OPERATING MODES OF 8237
1. Auto-initialize mode-the original values of the current address and current word
count registers are automatically restored from the base address and base word
count registers of that channel following EOP.

2. Priority mode- fixed priority fixes the channel in priority order based upon
descending value of their numbers.

3.Rotating priority –the last channel to get service becomes the lowest priority channel
with the others rotating accordingly.

4.Normal Mode- is the default mode of 8237. Read( IOR and MEMR) pulses are activated
during S3 and S4 and write pulse is activated during S4

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OPERATING MODES OF 8237;ctd

4. Extended write Mode- in this mode write (IOW and MEMR) and read (IOW and
MEMR) pulses are activated during S3 and S4. The minimum length of DMA cycle is S3.

5. Compressed Timing- the 8237A can compress the transfer time to two clock cycles.
State S3 is used to extend the access time of the read pulse. By removing state S3, the
read pulse width is made equal to the write pulse width and a transfer consists only of
state S2 to change the address and state S4 to perform the read/write.

76
INTERFACING OF DMA CONTROLLER
 REFERENCES
1. Mathur Sunil. (2011). Microprocessor 8086 : Architecture, Programming and
Interfacing. PHI Learning Pvt. Ltd.
2. Microprocessor - 8257 DMA Controller. (2023). Tutorialspoint.com.
https://www.tutorialspoint.com/microprocessor/microprocessor_8257_dma_
controller.htm