MOSFET – Device Structure (NMOS Transistor)

• The figure below shows the physical structure of the n-channel enhancement-type MOSFET

1
Creating a Channel for Current Flow
• Figure shows an enhancement-type NMOS with a positive voltage applied to the gate

• The source and the drain have been grounded

• Since the source is grounded, the gate voltage appears in effect between gate and source and
thus is denoted vGS

2
 Applying a Small Drain to Source Voltage (VDS)
• Once the channel has been created, a voltage vDS causes iD to flow through the induced n channel

• Current is carried by free electrons traveling from source to drain

• By convention, the direction of current flow is opposite to that of the flow of negative charge

• Thus the current in the channel, iD, will be from drain to source, as shown below

3
Applying a Small Drain to Source Voltage (VDS)…

• The magnitude of iD depends on the density of electrons in the channel, which in turn
depends on the magnitude of vGS

• For vGS = Vt, the channel is just induced & the current conducted is still negligibly small

• As vGS exceeds Vt, more electrons are attracted into the channel & increases its depth

• Thus, the channel conductance increases, equivalently, channel resistance decreases

• In fact, the conductance of the channel is proportional to the excess gate voltage (vGS - Vt),
also known as effective or overdrive voltage

• Thus, iD will be proportional to (vGS-Vt) and to the voltage vDS that causes iD to flow

4
Finite Output Resistance in Saturation

• Since iD is inversely proportional to the channel length, i D increases with vDS

1 W
iD  k n (vGS  Vt )2 (1  vDS )
2 L

• λ is a process-technology parameter with the dimensions of V -1 and for given process, λ is

inversely proportional to the length selected for the channel

• When channel-length modulation is considered, the saturation values of i D depend on vDS

• Thus, the output resistance in saturation is no longer infinite

• VA is a positive voltage (a process parameter) is referred to as the Early voltage

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 MOSFET as an Amplifier and as a Switch

• MOSFET acts as a voltage controlled current source in saturation region

• Changes in the gate-to-source voltage vGS cause changes in the drain current iD

• The relationship between vGS and iD is a square (nonlinear) relation in saturation mode

• However, we are interested in linear amplification i.e. an amplifier whose output signal (iD) is
linearly related to the input signal (vGS)

• A technique is used to get a linear relation from this non-linear device (in saturation mode)

• MOSFET is dc biased to operate at a certain VGS and a corresponding ID

• The input signal vGS to be amplified is then superimposed on the dc bias voltage VGS

• By keeping the signal vGS small, the resulting change in drain current i D, can be made
proportional to vGS 6
 Biasing by Fixing VG & Connecting RS

Smaller variability in ID , as compared to the previous case Practical Implementation using a single supply

7
 MOSFET Small Signal Operation
• If vgs is the input signal to be amplified, the total instantaneous gate to source voltage is:

vGS  VGS  vgs

• Then total instantaneous drain current iD is given by:

1 W
iD  (  nCox )( )(VGS  v gs  Vt ) 2
2 L

1 W W 1 W
(  nCox )( )(VGS  Vt ) 2  (  nCox )( )(VGS  Vt )v gs  (  nCox )( )v gs
2
iD 
2 L L 2 L

• The first term represents pure DC component

• The 2nd & 3rd (nonlinear distortion) component represents AC component

• This 3rd component should be kept as small as possible

1 W W
(  nCox )( )v gs  (  nCox )( )(VGS  Vt )v gs
2
2 L L
v gs  2(VGS  Vt ) vgs  2VOV
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 MOSFET Small Signal Operation
• If vgs<<2VOV or small signal condition is satisfied, the 3rd component may be neglected, then:

iD  I D  id
where,
W
id  (  nCox )( )(VGS  Vt )v gs
L
• The parameter that relates id and vgs is the MOSFET transconductance gm

id W W
gm   (  nCox )( )(VGS  Vt )  (  nCox )( )VOV
v gs L L

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Common Source (CS) Amplifier
• The CS or grounded source configuration is the most widely used of all MOS amplifier circuits

• It is used for providing the bulk of the gain in amplifier circuits

Common Source (CS) Amplifier-Terminal Characteristics
• Input Resistance

• Voltage Gain

• Output Resistance
CS Amplifier-Conclusions

A Common Source Amplifier has following characteristics:

• Very High Input Resistance

• Moderately High Voltage Gain

• High Output Resistance

BJT Types & Modes of Operation

13
BJT: iC-vCB curves for an npn transistor

14
BJT: iC-vCE curves for an npn transistor

15
BJT: iC-vCE curves (with Early Effect--VA)

16
BiMOS or BiCMOS

• MOSFET offers high input impedance

• MOSFET operation requires comparatively little power than BJTs

Whereas,

• BJT offers very-high-frequency operation

• BJT offers high-current-driving capability of bipolar transistors

• BJTs can be combined with MOSFETs to create innovative circuits that take their
combined advantages

• These combined circuits are called BiMOS or BiCMOS

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Q-point Analysis of a CE Amplifier

18
Importance of a Stable Q-point

19
Small Signal Operation

20
BJT Small Signal Models - T Model

21
The Common Emitter with an Emitter Resistance

22
CE with an Emitter Resistance - Terminal Characteristics

• Input Resistance

• Voltage Gain

• Output Resistance

23
 Operational Amplifiers

By the end of this topic, the students are expected to:

•Study its terminal characteristics and its applications

•Understand basics of Op Amps

•Understand Characteristics Ideal Op Amps

•The Inverting Configuration & its Applications like Weighted Summer

•The Non-inverting Configuration & its Characteristics

•Difference Amplifiers

•The Instrumentation Amplifier

•OP Amps as Integrators and Differentiators

•DC Imperfections and effects like Slew Rate

25
Ideal Op Amp – Equivalent Circuit

26
 Ideal Op Amp - Characteristics
The following characteristics, thus, describe an ideal Op Amp

• Infinite input impedance

• Zero output impedance

• Zero common-mode gain or, equivalently, infinite common-mode rejection

• Infinite open-loop gain A

• Infinite bandwidth

27
 Op Amp – The Inverting Configuration
• Op amps are not used alone, they are connected to passive components in a feedback
circuit

• Figure shows one such configuration, known as the inverting configuration

• Two resistor R1 and R2 are are used in this configuration, in which R2 provides the –ve
feedback & closes the loop around the op amp

• R1 is connected between the input source vI and the inverting terminal 1

• The other input terminal i.e. terminal 2 is connected to ground in this configuration

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 A Single Op Amp Difference Amplifiers
• The inverting & non-inverting configurations are combined together to get the difference
b/w the two common signal equal to zero

• The two gain magnitudes have to be made equal in order to reject common-mode signals

• The gain of one configuration (1+R2/R1) can be attenuated to R2/R1 & the following
conditions are then met

29
 The Instrumentation Amplifier
• Overcomes the low input resistance problem with difference amplifier

• The first stage A1 & A2 provides the bulk of the gain. A3 provides the differential function

• The second stage ensure proper rejection of the common mode signals

30
 Slew Rate
• Another phenomenon that can cause nonlinear distortion when large output signals are
present is that of slew-rate limiting

• Practically, there is a specific max. rate of change possible at the output of a real op amp

• This maximum is known as the slew rate (SR) of the op amp and is defined as

• It is usually specified on the op-amp data sheet in units of V/μs

• It follows that if the input signal applied to an op-amp circuit is such that it demands an
output response that is faster than the specified value of SR, the op amp will not comply.

• Rather, its output will change at the maximum possible rate, which is equal to its SR

31