Digital Logic Design

Combinational Logic
Decoders
A decoder is a combinational
circuit that converts binary
information from n input lines
to 2n unique output lines

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 Decoders

 Extract “Information” from the code Only one

lamp will
 Binary Decoder turn on
● Example: 2-bit Binary Number

0 1
x1 0
Binary
0 Decoder 0
x0 0

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 Decoders

 2-to-4 Line Decoder

Y3

y3 Y2

Decoder
I1 Binary
y2
Y1
y1
I0
y0 Y0

I1 I 0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 I1 I 0 Y2 I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 I1 I 0 Y0 I1 I 0
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 Decoders

 3-to-8 Line Decoder Y7  I 2 I1 I 0

Y6  I 2 I1 I 0
Y7 Y5  I 2 I1 I 0
Y6
Y4  I 2 I1 I 0
Y5
Decoder
Binary

I2
Y4 Y3  I 2 I1 I 0
I1
Y3 Y2  I 2 I1 I 0
I0
Y2
Y1  I 2 I1 I 0
Y1
Y0 Y0  I 2 I1 I 0

I2
I1
I0
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 Decoders

 “Enable” Control Y3

Y3 Y2

Decoder
I1
Binary Y2
I0
Y1 Y1
E
Y0
Y0
E I1 I 0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
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 Decoders

 Expansion I2 I 1 I 0

I2 I 1 I 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0

Binary
0 1 0 0 0 0 0 0 1 0 0 Y2 Y6
I1
0 1 1 0 0 0 0 1 0 0 0 Y1 Y5
1 0 0 0 0 0 1 0 0 0 0 E
Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3

Decoder
I0

Binary
1 1 1 1 0 0 0 0 0 0 0 Y2 Y3
I1
Y1 Y2
E
Y0 Y1
Y0
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 Decoders

 Active-High / Active-Low
I1 I0 Y3 Y2 Y1 Y0 I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y3 Y3 Y1
Decoder

I1 I1 Decoder
Binary

Binary
Y2 Y2 Y0

Y1 Y1
I0 I0 I1
Y0 Y0 I0

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 Implementation Using Decoders

 Each output is a minterm

Binary
Decoder
 All minterms are produced
Y7
 Sum the required minterms
Y6
Y5
x I2
Y4
y I1
Example: Full Adder Y3
z I0
Y2
S(x, y, z) = ∑(1, 2, 4, 7)
Y1
C(x, y, z) = ∑(3, 5, 6, 7) Y0

S C 10 / 65
 A+B = [(A+B)’]’
= [A’ B’]’

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 Implementation Using Decoders
Binary Binary
Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 x I2
Y4 Y4
y I1 y I1
z Y3 z Y3
I0 I0
Y2 Y2
Y1 Y1
Y0 Y0

S C
S C
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 Encoders

 Performs the inverse function of a Decoder.

 Converts 2n inputs to n outputs
 Put “Information” into code Only one
switch
 Binary Encoder should be
activated
● Example: 4-to-2 Binary Encoder at a time
x1
x3 x2 x1 y1 y0
x2 y1 0 0 0 0 0
Binary
Encoder 0 0 1 0 1
y0
x3 0 1 0 1 0
1 0 0 1 1 13 / 65
 Encoders

 Octal-to-Binary Encoder (8-to-3)

I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
0 0 0 0 0 0 0 1 0 0 0

Encoder
I5 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0
I3 Y0
0 0 0 0 1 0 0 0 0 1 1
I2
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1 I1
0 1 0 0 0 0 0 0 1 1 0 I7
I0
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 I 7  I 6  I 5  I 4 I4
I3 Y1
Y1 I 7  I 6  I 3  I 2 I2
I1
Y0 I 7  I 5  I 3  I1 I0 Y0
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Priority Encoders

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 V=D0+D1+D2+D3

K-Maps for 4-input Priority Encoder

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 Priority Encoders

 4-Input Priority Encoder

I3 V

Encoder
Priority
I3 I 2 I 1 I 0 Y1 Y0 V
I2 Y1
0 0 0 0 0 0 0 I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 I 3  I 2 Y1
1 1 1 1
1 1 1 1
I2 Y0 I 3  I 2 I1
I3 1 1 1 1 I0 V
I0 V  I 3  I 2  I1  I 0

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Encoder / Decoder Pairs

Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2
I4 Y4
Y1 I1
I3 Y3
Y0 I0
I2 Y2
I1 Y1
I0 Y0

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Multiplexers

S1 S0 Y I0
0 0 I0 I1 MUX
Y
0 1 I1 I2
1 0 I2 I3 S1 S0
1 1 I3
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 Multiplexers

 2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
I0
 4-to-1 MUX I1
Y
I0 I2

I1 MUX I3
Y
I2
I3 S1 S0
S1 S0
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 Multiplexers

 Quad 2-to-1 MUX A 3

Y3
A2
x3 I0 Y2
y3 MUX Y A1
I1 S Y1
A0
Y0
x2 I0
MUX Y
B3
y2 I1 S B2
A3
B1 A2
I0 A1 Y3
MUX Y B0
I1 A0
S MUX Y2
x1 B3 Y1
y1 S E B2 Y0
I0
MUX Y B1
I1 S B0 S E

S
x0 22 / 65
 Multiplexers

 Quad 2-to-1 MUX

A3
Y3 A3
A2
Y2 A2
A1
Y1 A1 Y3
A0
A0
MUX Y2
Y0
B3
B3 Y1
B2
B2 Y0
B1
B1
B0
B0 S E
Extra
Buffers
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 Implementation Using Multiplexers

 Example
F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1 MUX
Y F
0 1 1 0 I2
1 0 0 1 I3 S1 S0
1 1 1
x y

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 Implementation Using Multiplexers

 Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3 MUX Y F
0 1 0 1 0
I4
0 1 1 0 0
1 I5
1 0 0 0 I6
1
1 0 1 0 I7 S2 S1 S0
1 1 0 1
1 1 1 1 x y z

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 Implementation Using Multiplexers

 Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z F
0 0 1 1 I1 MUX
0 Y
0 1 0 1 I2
F=z 1
0 1 1 0 I3 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
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 Implementation Using Multiplexers

 Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
D I1
0 0 1 0 0
F=D D
0 0 1 1 1
0 1 0 0 1
I2
F=D 0
0 1 0 1 0
0
I3 MUX Y F
0 1 1 0 0
0 1 1 1 0
F=0 I4
D
1 0 0 0 0
1 0 0 1 0 F=0 1 I5
1 0 1 0 0
F=D 1 I6
1 0 1 1 1
1 1 0 0 1 F=1 I7 S2 S1 S0
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
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 Multiplexer Expansion

 8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1 MUX
Y
I2 I2
I3 I3 S1 S0
I0
MUX Y Y
I1
I0 S
I4 I1 MUX
I5 Y
I2
I6 I3 S1 S0
I7
1 0 0
S2 S1 S0 28 / 65
 DeMultiplexers

Y3
DeMUX Y2
I
Y1
S1 S0 Y0

Y3

Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
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Multiplexer / DeMultiplexer Pairs

MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y Y4
I
I3 Y3
I2 Y2
I1 Y1
Y0
SI20 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
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DeMultiplexers / Decoders

Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX I0
Y1 Y1
E
S1 S0 Y0 Y0

E I1 I 0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0

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 Three-State Gates

 Tri-State Buffer
C A Y
A Y 0 x Hi-Z
1 0 0
1 1 1
C
A Y
 Tri-State Inverter
C

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Three-State Gates

A C D Y
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?

Not Allowed
D
A
C A if C = 1
Y=
B if C = 0
B
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Three-State Gates

I3

I2
Y
I1

I0
Y3
Decoder

S1 I1
Binary

Y2
S0 I0
E Y1
E
Y0
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