(Logic Design)

Lec. # 7

Dr. Ahmed Helmi

Accredited to: Dr. Tamer Samy Gaafr

Boolean Algebra and Logic Gates 1

Decoders and Encoders
▪ Decoder function and implementation
▪ Encoder function
▪ Implementation using decoders

Boolean Algebra and Logic Gates 2

 Decoders
▪ Extract “Information” from the code Only one lamp
will turn on
▪ Binary Decoder
• Example: 2-bit Binary Number

0 1 2 3

1
0
x1
0
Binary
0 Decoder 0
x0
0

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 Decoders
▪ 2-to-4 Line Decoder Y3

y3 Y2
I1 y2
Decoder
Binary
y1
I0 y0 Y1

Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
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 Decoders
▪ 3-to-8 Line Decoder Y7 = I 2 I1 I 0
Y6 = I 2 I1 I 0
Y7
Y6 Y5 = I 2 I1 I 0
Y5
Y4 Y4 = I 2 I1 I 0
Y3
Decoder

I2
Binary

I1 Y2 Y3 = I 2 I1 I 0
I0 Y1
Y0 Y2 = I 2 I1 I 0

Y1 = I 2 I1 I 0

Y0 = I 2 I1 I 0

n I2
Input is n, and output is 2 I1
I0
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 Decoders
▪ “Enable” Control Y3
Y3
I1 Y2 Y2

Decoder
I0 Binary Y1
E Y0
Y1

Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
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 Decoders
▪ Expansion I2 I1 I0

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
Y3 Y7
0 0 1 0 0 0 0 0 0 1 0 I0 Y2

Decoder
0 1 0 0 0 0 0 0 1 0 0 Y6

Binary
I1 Y1
E Y0
0 1 1 0 0 0 0 1 0 0 0 Y5
1 0 0 0 0 0 1 0 0 0 0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3 Y3
I0 Y2
1 1 1 1 0 0 0 0 0 0 0

Decoder
Y2

Binary
I1 Y1
E Y0 Y1
Y0

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 Decoders
▪ Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y1
Y3 Y3
I1 I1
Decoder

Decoder Y0
Binary

Binary
Y2 Y2
I0 Y1 I0 Y1
I1
Y0 Y0 I0
74HC154 4-to-16 Decoder

Boolean Algebra and Logic Gates 9

Implementation Using Decoders
▪ Each output is a minterm Binary Decoder
▪ All minterms are produced
▪ Sum the required minterms Y7
Y6
Y5
x
I2
Y4
Example: Full Adder y I1
I0 Y3

S(x, y, z) = ∑(1, 2, 4, 7) z Y2
Y1
C(x, y, z) = ∑(3, 5, 6, 7) Y0

S C
 Implementation Using Decoders
Binary Decoder Binary Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 x I2
y Y4 y Y4
I1 I1
z I0 Y3 z I0 Y3
Y2 Y2
Y1 Y1
Y0 Y0

S C
S C
BCD to Decimal Decoder
BCD to Decimal Decoder
 Encoders
▪ Put “Information” into code Only one
switch should
▪ Binary Encoder be activated at
a time
• Example: 4-to-2 Binary Encoder
X0
0
x1 x3 x2 x1 x0 y1 y0
1
Binary 0 0 0 0 0 0
y1
x2 Encoder
2 0 0 0 1 0 0
y0 0 0 1 0 0 1
3 x3 0 1 0 0 1 0
n
1 0 0 0 1 1
Input is 2 , and output is n
 Encoders
▪ Octal-to-Binary Encoder (8-to-3)
I7
I7 I6 I5 I4 I3 I2 I 1 I0 Y2 Y1 Y 0 I6
0 0 0 0 0 0 0 1 0 0 0 I5 Y2

Encoder
Binary
0 0 0 0 0 0 1 0 0 0 1 I4
Y1
0 0 0 0 0 1 0 0 0 1 0 I3
0 0 0 0 1 0 0 0 0 1 1 I2 Y0

0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
I7
0 1 0 0 0 0 0 0 1 1 0 I6 Y2
1 0 0 0 0 0 0 0 1 1 1 I5

Y2 = I 7 + I 6 + I 5 + I 4
I4
I3 Y1

Y1 = I 7 + I 6 + I 3 + I 2 I2
I1
Y0
Y0 = I 7 + I 5 + I 3 + I1 I0
 Priority Encoders
▪ 4-Input Priority Encoder
I3
I3 I2 I1 I0 Y1 Y0 V V0

Encoder
Priority
I2
Y1
0 0 0 0 0 0 0 I1
Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 = I 3 + I 2 Y1
1 1 1 1
1 1 1 1
I2 Y0 = I 3 + I 2 I1
I3 I0 V
1 1 1 1
I0
V = I 3 + I 2 + I1 + I 0
I3 I2 I1 I0 Y0
0 0 0 0 0 Simplification of Y0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
I1 I0
00 01 11 10
0 1 0 0 0 I3 I2
0 1 0 1 0 00 0 0 1 1
0 1 1 0 0 01 0 0 0 0
0 1 1 1 0 11 1 1 1 1
1 0 0 0 1 10 1 1 1 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Decimal to BCD Encoder
Decimal to BCD Encoder
Decimal to BCD Priority Encoder

If both 6 and 3 inputs are LOW, then output will be 0110