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JTAG

The document summarizes the JTAG IEEE 1149.1 2001 standard. It describes the Joint Test Action Group's boundary scan standard which aims to test digital chips and interconnections between chips. It outlines the boundary scan architecture, operation modes including normal, shift, capture and update. It also describes the typical boundary scan cell and the TAP controller finite state machine with its 16 states and input/output signals. Finally, it lists some common JTAG instructions like EXTEST, SAMPLE, PRELOAD and optional ones like INTEST.

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Shiva Kumar
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Download as pptx, pdf, or txt
194 views12 pages

JTAG

The document summarizes the JTAG IEEE 1149.1 2001 standard. It describes the Joint Test Action Group's boundary scan standard which aims to test digital chips and interconnections between chips. It outlines the boundary scan architecture, operation modes including normal, shift, capture and update. It also describes the typical boundary scan cell and the TAP controller finite state machine with its 16 states and input/output signals. Finally, it lists some common JTAG instructions like EXTEST, SAMPLE, PRELOAD and optional ones like INTEST.

Uploaded by

Shiva Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
Download as pptx, pdf, or txt
Download as pptx, pdf, or txt
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JTAG IEEE 1149.

1 2001 standard

Joint Test Action Group(JTAG) proposed Boundary Scan Standard


Boundarry Scan Objective: Testing of digital chips and Interconnections between Chips

A Board Containing 4 ICs with Boundary Scan

1149..1 BoundarryScan Architecture

Boundary-Scan Circuitry in A Chip

TRST*

Operation modes: Normal Shift Capture Update

A Typical Boundary--Scan Cell

TAP Controller

A finite state machine with 16 states Input: TCK, TMS Output: 9 or 10 signals including ClockDR, UpdateDR, shiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK, and the optional TRST*

Test-Logic-Reset: normal mode Run-Test/Idle: wait for internal test such as BIST Select-DR-Scan: initiate a data-scan sequence Capture-DR: load test data in parallel Shift-DR: load test data in series Exit1-DR: Finish phase-1 shifting of data

Pause-DR: Temporarily hold the scan operation (allow the bus master to reload data)
Exit2-DR: finish phase-2 shifting of data Update-DR: parallel load from associated shift registers

Instruction Set
EXTEST Test Interconnection between chips and board SAMPLE/PRELOAD Sample and shift out data or shift data only BYPASS Bypass data through a chip

Optional
Intest, RunBist, CLAMP, Idcode, usercode, High-Z, etc.

EXTEST

SAMPLE

PRELOAD

INTEST

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