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ORCIDWayne P. Burleson
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- affiliation: University of Massachusetts Amherst, Department of Electrical and Computer Engineering, MA, USA
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2020 – today
- 2023
[j50]Shayan Moini
, Aleksa Deric, Xiang Li, George Provelengios, Wayne P. Burleson, Russell Tessier, Daniel E. Holcomb:
Voltage Sensor Implementations for Remote Power Attacks on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 16(1): 11:1-11:21 (2023)- [i9]William Lillis, Max Cohen Hoffing, Wayne P. Burleson:
Survey of Security Issues in Memristor-based Machine Learning Accelerators for RF Analysis. CoRR abs/2312.00942 (2023) - 2022
- [j49]Chenglu Jin, Wayne P. Burleson, Marten van Dijk, Ulrich Rührmair:
Programmable access-controlled and generic erasable PUF design and its applications. J. Cryptogr. Eng. 12(4): 413-432 (2022) - [j48]Kohei Yamashita, Benjamin Cyr, Kevin Fu, Wayne P. Burleson, Takeshi Sugawara:
Redshift: Manipulating Signal Propagation Delay via Continuous-Wave Lasers. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4): 463-489 (2022) - 2021
- [j47]Davide Bertozzi, Gabriele Miorandi, Alberto Ghiribaldi, Wayne P. Burleson, Greg Sadowski, Kshitij Bhardwaj, Weiwei Jiang, Steven M. Nowick:
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems. IEEE Micro 41(1): 69-81 (2021) - [c136]Srinivasa Ramanujam, Wayne P. Burleson:
Reconfiguring the Mux-Based Arbiter PUF using FeFETs. ISQED 2021: 257-262 - 2020
- [j46]Salem T. Argaw, Juan Ramón Troncoso-Pastoriza, Darren Lacey, Marie-Valentine Florin, Franck Calcavecchia, Denise Anderson, Wayne P. Burleson, Jan-Michael Vogel, Chana O'Leary, Bruce Eshaya-Chauvin, Antoine Flahault:
Cybersecurity of Hospitals: discussing the challenges and working towards mitigating the risks. BMC Medical Informatics Decis. Mak. 20(1): 146 (2020) - [c135]Chenglu Jin, Wayne P. Burleson, Marten van Dijk, Ulrich Rührmair:
Erasable PUFs: Formal Treatment and Generic Design. ASHES@CCS 2020: 21-33 - [c134]Shayan Moini, Xiang Li, Peter Stanwicks, George Provelengios, Wayne P. Burleson, Russell Tessier, Daniel E. Holcomb:
Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs. MWSCAS 2020: 941-944 - [i8]Wayne P. Burleson, Kevin Fu, Denise L. Anthony, Jorge Guajardo, Carl A. Gunter, Kyle Ingols, Jean-Baptiste Jeannin, Farinaz Koushanfar, Carl E. Landwehr, Susan Squires:
Grand Challenges for Embedded Security Research in a Connected World. CoRR abs/2005.06585 (2020)
2010 – 2019
- 2019
- [j45]Anupam Chattopadhyay, Swaroop Ghosh, Wayne P. Burleson, Debdeep Mukhopadhyay:
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2469-2472 (2019) - [c133]Jacqueline Lagasse, Christopher Bartoli, Wayne P. Burleson:
Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis. ASAP 2019: 214-217 - [c132]Shuo Li, Xiaolin Xu, Wayne P. Burleson:
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations. ISVLSI 2019: 574-579 - 2018
- [j44]Katayoun Neshatpour, Wayne P. Burleson, Amin Khajeh, Houman Homayoun:
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 778-791 (2018) - [i7]Kapil Dev, Indrani Paul, Wei Huang, Yasuko Eckert, Wayne P. Burleson, Sherief Reda:
Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques. CoRR abs/1808.09651 (2018) - [i6]Yansong Gao, Chenglu Jin, Jeeson Kim, Hussein Nili, Xiaolin Xu, Wayne P. Burleson, Omid Kavehei, Marten van Dijk, Damith Chinthana Ranasinghe, Ulrich Rührmair:
Efficient Erasable PUFs from Programmable Logic and Memristors. IACR Cryptol. ePrint Arch. 2018: 358 (2018) - 2017
- [c131]Weiwei Jiang, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski:
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart. DATE 2017: 732-733 - [c130]Shuo Li, Xiaolin Xu, Wayne P. Burleson:
CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter. ISVLSI 2017: 501-506 - 2016
- [j43]Josiah D. Hester, Nicole Tobias, Amir Rahmati, Lanny Sitanayah, Daniel E. Holcomb, Kevin Fu, Wayne P. Burleson, Jacob Sorber:
Persistent Clocks for Batteryless Sensing Devices. ACM Trans. Embed. Comput. Syst. 15(4): 77:1-77:28 (2016) - [c129]Wayne P. Burleson, Onur Mutlu, Mohit Tiwari:
Invited - Who is the major threat to tomorrow's security?: you, the hardware designer. DAC 2016: 145:1-145:5 - [c128]Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne P. Burleson:
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. ISVLSI 2016: 242-247 - [c127]Xiaolin Xu, Wayne P. Burleson, Daniel E. Holcomb:
Using Statistical Models to Improve the Reliability of Delay-Based PUFs. ISVLSI 2016: 547-552 - 2015
- [j42]Xiaolin Xu, Amir Rahmati, Daniel E. Holcomb, Kevin Fu, Wayne P. Burleson:
Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 903-914 (2015) - [j41]Vikram B. Suresh, Wayne P. Burleson:
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1785-1793 (2015) - [c126]Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Reinforcement Learning for Thermal-aware Many-core Task Allocation. ACM Great Lakes Symposium on VLSI 2015: 379-384 - [c125]Katayoun Neshatpour, Houman Homayoun, Amin Khajeh, Wayne P. Burleson:
Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence. ACM Great Lakes Symposium on VLSI 2015: 385-390 - [c124]Shweta Malik, Georg T. Becker, Christof Paar, Wayne P. Burleson:
Development of a Layout-Level Hardware Obfuscation Tool. ISVLSI 2015: 204-209 - [c123]Xiaolin Xu, Ulrich Rührmair, Daniel E. Holcomb, Wayne P. Burleson:
Security Evaluation and Enhancement of Bistable Ring PUFs. RFIDSec 2015: 3-16 - [c122]Raghavan Kumar, Wayne P. Burleson:
Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data. RFIDSec 2015: 53-67 - [c121]Ulrich Rührmair, J. L. Martinez-Hurtado, Xiaolin Xu, Christian Kraeh, Christian Hilgers, Dima Kononchuk, Jonathan J. Finley, Wayne P. Burleson:
Virtual Proofs of Reality and their Physical Implementation. IEEE Symposium on Security and Privacy 2015: 70-85 - [i5]Xiaolin Xu, Ulrich Rührmair, Daniel E. Holcomb, Wayne P. Burleson:
Security Evaluation and Enhancement of Bistable Ring PUFs. IACR Cryptol. ePrint Arch. 2015: 443 (2015) - [i4]Chenglu Jin, Xiaolin Xu, Wayne P. Burleson, Ulrich Rührmair, Marten van Dijk:
PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management. IACR Cryptol. ePrint Arch. 2015: 1052 (2015) - 2014
- [j40]Georg T. Becker, Francesco Regazzoni, Christof Paar, Wayne P. Burleson:
Stealthy dopant-level hardware Trojans: extended version. J. Cryptogr. Eng. 4(1): 19-31 (2014) - [j39]Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 853-866 (2014) - [c120]Sara S. Ghoreishizadeh, Tolga Yalçin, Antonio Pullini, Giovanni De Micheli, Wayne P. Burleson, Sandro Carrara:
A lightweight cryptographic system for implantable biosensors. BioCAS 2014: 472-475 - [c119]Ulrich Rührmair, Xiaolin Xu, Jan Sölter, Ahmed Mahmoud, Mehrdad Majzoobi, Farinaz Koushanfar, Wayne P. Burleson:
Efficient Power and Timing Side Channels for Physical Unclonable Functions. CHES 2014: 476-492 - [c118]Xinfei Guo, Wayne P. Burleson, Mircea R. Stan:
Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques. DAC 2014: 171:1-171:6 - [c117]Ulrich Rührmair, Ulf Schlichtmann, Wayne P. Burleson:
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks. DATE 2014: 1-4 - [c116]Xiaolin Xu, Wayne P. Burleson:
Hybrid side-channel/machine-learning attacks on PUFs: A new threat? DATE 2014: 1-6 - [c115]Raghavan Kumar, Philipp Jovanovic, Wayne P. Burleson, Ilia Polian:
Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. FDTC 2014: 18-28 - [c114]Raghavan Kumar, Wayne P. Burleson:
On design of a highly secure PUF based on non-linear current mirrors. HOST 2014: 38-43 - [c113]Fulya Kaplan, Charlie De Vivero, Samuel Howes, Manish Arora, Houman Homayoun, Wayne P. Burleson, Dean M. Tullsen, Ayse K. Coskun:
Modeling and analysis of Phase Change Materials for efficient thermal management. ICCD 2014: 256-263 - [c112]Raghavan Kumar, Wayne P. Burleson:
Hybrid modeling attacks on current-based PUFs. ICCD 2014: 493-496 - [c111]Mark Buckler, Wayne P. Burleson:
Predictive synchronization for DVFS-enabled multi-processor systems. ISQED 2014: 270-275 - [c110]Vikram B. Suresh, Wayne P. Burleson:
Fine grained wearout sensing using metastability resolution time. ISQED 2014: 480-483 - [c109]Vikram B. Suresh, Wayne P. Burleson:
Variation Aware Design of Post-Silicon Tunable Clock Buffer. ISVLSI 2014: 1-6 - [c108]Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson:
Post-Silicon Validation and Calibration of Hardware Security Primitives. ISVLSI 2014: 29-34 - [c107]Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier:
A Broadcast-Enabled Sensing System for Embedded Multi-core Processors. ISVLSI 2014: 190-195 - [c106]Wayne P. Burleson:
Keynote talk I: Security and privacy in implantable medical devices: An ongoing concern. MEMOCODE 2014: 1 - [c105]Mark Buckler, Arpan Vaidya, Xiaobin Liu, Wayne P. Burleson:
Dynamic synchronizer flip-flop performance in FinFET technologies. NOCS 2014: 104-110 - [c104]Vikram B. Suresh, Wayne P. Burleson:
REFLEX: Reconfigurable logic for entropy extraction. SoCC 2014: 341-346 - [i3]Raghavan Kumar, Philipp Jovanovic, Wayne P. Burleson, Ilia Polian:
Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. IACR Cryptol. ePrint Arch. 2014: 783 (2014) - 2013
- [j38]Ulrich Rührmair, Jan Sölter, Frank Sehnke, Xiaolin Xu, Ahmed Mahmoud, Vera Stoyanova, Gideon Dror, Jürgen Schmidhuber, Wayne P. Burleson, Srinivas Devadas:
PUF Modeling Attacks on Simulated and Silicon Data. IEEE Trans. Inf. Forensics Secur. 8(11): 1876-1891 (2013) - [j37]Hu Xu, Vasilis F. Pavlidis, Xifan Tang, Wayne P. Burleson, Giovanni De Micheli:
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2226-2239 (2013) - [c103]Georg T. Becker, Francesco Regazzoni, Christof Paar, Wayne P. Burleson:
Stealthy Dopant-Level Hardware Trojans. CHES 2013: 197-214 - [c102]Masoud Rostami, Wayne P. Burleson, Farinaz Koushanfar, Ari Juels:
Balancing security and utility in medical devices? DAC 2013: 13:1-13:6 - [c101]Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier:
Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems. DATE 2013: 1395-1398 - [c100]Vikram B. Suresh, Daniele Antonioli, Wayne P. Burleson:
On-chip lightweight implementation of reduced NIST randomness test suite. HOST 2013: 93-98 - [c99]Mark Buckler, Wayne P. Burleson, Greg Sadowski:
Low-power Networks-on-Chip: Progress and remaining challenges. ISLPED 2013: 132-134 - [c98]Raghavan Kumar, Wayne P. Burleson:
Litho-aware and low power design of a secure current-based physically unclonable function. ISLPED 2013: 402-407 - [c97]Gesine Hinterwälder, Christian T. Zenger, Foteini Baldimtsi, Anna Lysyanskaya, Christof Paar, Wayne P. Burleson:
Efficient E-Cash in Practice: NFC-Based Payments for Public Transportation Systems. Privacy Enhancing Technologies 2013: 40-59 - [c96]Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu:
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. VLSI Design 2013: 80-85 - [i2]Ulrich Rührmair, Jan Sölter, Frank Sehnke, Xiaolin Xu, Ahmed Mahmoud, Vera Stoyanova, Gideon Dror, Jürgen Schmidhuber, Wayne P. Burleson, Srinivas Devadas:
PUF Modeling Attacks on Simulated and Silicon Data. IACR Cryptol. ePrint Arch. 2013: 112 (2013) - [i1]Ulrich Rührmair, Xiaolin Xu, Jan Sölter, Ahmed Mahmoud, Farinaz Koushanfar, Wayne P. Burleson:
Power and Timing Side Channels for PUFs and their Efficient Exploitation. IACR Cryptol. ePrint Arch. 2013: 851 (2013) - 2012
- [j36]Markus Kasper, Amir Moradi, Georg T. Becker, Oliver Mischke, Tim Güneysu, Christof Paar, Wayne P. Burleson:
Side channels as building blocks. J. Cryptogr. Eng. 2(3): 143-159 (2012) - [j35]Sandro Carrara, Sara S. Ghoreishizadeh, Jacopo Olivo, Irene Taurino, Camilla Baj-Rossi, Andrea Cavallini, Maaike Op de Beeck, Catherine Dehollain, Wayne P. Burleson, Francis Moussy, Anthony Guiseppi-Elie, Giovanni De Micheli:
Fully Integrated Biochip Platforms for Advanced Healthcare. Sensors 12(8): 11013-11060 (2012) - [j34]Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne P. Burleson:
An architecture-independent instruction shuffler to protect against side-channel attacks. ACM Trans. Archit. Code Optim. 8(4): 20:1-20:19 (2012) - [j33]Georg T. Becker, Daehyun Strobel, Christof Paar, Wayne P. Burleson:
Detecting Software Theft in Embedded Systems: A Side-Channel Approach. IEEE Trans. Inf. Forensics Secur. 7(4): 1144-1154 (2012) - [j32]Lang Lin, Sudheendra Srivathsa, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne P. Burleson:
Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications. IEEE Trans. Inf. Forensics Secur. 7(4): 1394-1403 (2012) - [j31]Jinwook Jang, Olivier Franza, Wayne P. Burleson:
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 66-79 (2012) - [c95]Wayne P. Burleson, Shane S. Clark, Benjamin Ransford, Kevin Fu:
Design challenges for secure implantable medical devices. DAC 2012: 12-17 - [c94]Jia Zhao, Russell Tessier, Wayne P. Burleson:
Distributed sensor data processing for many-cores. ACM Great Lakes Symposium on VLSI 2012: 159-164 - [c93]Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Collaborative calibration of on-chip thermal sensors using performance counters. ICCAD 2012: 15-22 - [c92]Vikram B. Suresh, Wayne P. Burleson:
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration. ISQED 2012: 298-305 - [c91]Hu Xu, Vasilis F. Pavlidis, Wayne P. Burleson, Giovanni De Micheli:
The combined effect of process variations and power supply noise on clock skew and jitter. ISQED 2012: 320-327 - [c90]Raghavan Kumar, Wayne P. Burleson:
PHAP: Password based Hardware Authentication using PUFs. MICRO Workshops 2012: 24-31 - [c89]Gesine Hinterwälder, Christof Paar, Wayne P. Burleson:
Privacy Preserving Payments on Computational RFID Devices with Application in Intelligent Transportation Systems. RFIDSec 2012: 109-122 - [c88]Daniel E. Holcomb, Amir Rahmati, Mastooreh Salajegheh, Wayne P. Burleson, Kevin Fu:
DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification. RFIDSec 2012: 165-179 - [c87]Amir Rahmati, Mastooreh Salajegheh, Daniel E. Holcomb, Jacob Sorber, Wayne P. Burleson, Kevin Fu:
TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks. USENIX Security Symposium 2012: 221-236 - 2011
- [j30]Basab Datta, Wayne P. Burleson:
Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies. J. Low Power Electron. 7(3): 403-419 (2011) - [j29]Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier:
A Dedicated Monitoring Infrastructure for Multicore Processors. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1011-1022 (2011) - [c86]Jinwook Jang, Wayne P. Burleson:
An arbiter based on-chip droop detector system. ACM Great Lakes Symposium on VLSI 2011: 1-6 - [c85]Basab Datta, Wayne P. Burleson:
A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS. ACM Great Lakes Symposium on VLSI 2011: 133-138 - [c84]Basab Datta, Wayne P. Burleson:
A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics. ACM Great Lakes Symposium on VLSI 2011: 289-294 - [c83]Krishna C. Chillara, Jinwook Jang, Wayne P. Burleson:
Robust signaling techniques for through silicon via bundles. ACM Great Lakes Symposium on VLSI 2011: 383-386 - [c82]Wayne P. Burleson, Yusuf Leblebici:
Hardware security in VLSI. ACM Great Lakes Symposium on VLSI 2011: 447-448 - [c81]Georg T. Becker, Ashwin Lakshminarasimhan, Lang Lin, Sudheendra Srivathsa, Vikram B. Suresh, Wayne P. Burleson:
Implementing hardware Trojans: Experiences from a hardware Trojan challenge. ICCD 2011: 301-304 - [c80]Basab Datta, Wayne P. Burleson:
A 12.4μm2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation. ISQED 2011: 67-73 - 2010
- [c79]Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier:
Multicore soft error rate stabilization using adaptive dual modular redundancy. DATE 2010: 27-32 - [c78]Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier:
Thermal-aware voltage droop compensation for multi-core architectures. ACM Great Lakes Symposium on VLSI 2010: 335-340 - [c77]Basab Datta, Wayne P. Burleson:
Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. ACM Great Lakes Symposium on VLSI 2010: 341-346 - [c76]Basab Datta, Wayne P. Burleson:
Circuit-level NBTI macro-models for collaborative reliability monitoring. ACM Great Lakes Symposium on VLSI 2010: 453-458 - [c75]Vikram B. Suresh, Wayne P. Burleson:
Entropy Extraction in Metastability-based TRNG. HOST 2010: 135-140 - [c74]Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne P. Burleson:
Low-power sub-threshold design of secure physical unclonable functions. ISLPED 2010: 43-48 - [c73]Basab Datta, Wayne P. Burleson:
Calibration of on-chip thermal sensors using process monitoring circuits. ISQED 2010: 461-467
2000 – 2009
- 2009
- [j28]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Eduardo Braulio Wanderley Netto, Russell Tessier, Wayne P. Burleson:
A security approach for off-chip memory in embedded microprocessor systems. Microprocess. Microsystems 33(1): 37-45 (2009) - [j27]Daniel E. Holcomb, Wayne P. Burleson, Kevin Fu:
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers. IEEE Trans. Computers 58(9): 1198-1210 (2009) - [c72]Lang Lin, Markus Kasper, Tim Güneysu, Christof Paar, Wayne P. Burleson:
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering. CHES 2009: 382-395 - [c71]Lang Lin, Wayne P. Burleson:
Analysis and mitigation of process variation impacts on Power-Attack Tolerance. DAC 2009: 238-243 - [c70]Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier:
A monitor interconnect and support subsystem for multicore processors. DATE 2009: 761-766 - [c69]Basab Datta, Wayne P. Burleson:
Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors. ACM Great Lakes Symposium on VLSI 2009: 145-148 - [c68]Lang Lin, Wayne P. Burleson, Christof Paar:
MOLES: Malicious off-chip leakage enabled by side-channels. ICCAD 2009: 117-122 - [c67]Basab Datta, Wayne P. Burleson:
On temperature planarization effect of copper dummy fills in deep nanometer technology. ISQED 2009: 494-499 - [c66]Basab Datta, Wayne P. Burleson:
Temperature effects on energy optimization in sub-threshold circuit design. ISQED 2009: 680-685 - 2008
- [j26]Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin:
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 144-155 (2008) - [c65]Basab Datta, Wayne P. Burleson:
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators. ACM Great Lakes Symposium on VLSI 2008: 41-46 - [c64]Venkatesh Arunachalam, Wayne P. Burleson:
Low-power clock distribution in a multilayer core 3d microprocessor. ACM Great Lakes Symposium on VLSI 2008: 429-434 - [c63]Lang Lin, Wayne P. Burleson:
Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems. ISCAS 2008: 252-255 - [c62]Basab Datta, Wayne P. Burleson:
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO. SoCC 2008: 147-150 - 2007
- [j25]Atul Maheshwari, Wayne P. Burleson:
Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1239-1244 (2007) - [c61]Vishak Venkatraman, Wayne P. Burleson:
An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects. CICC 2007: 301-304 - [c60]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne P. Burleson:
High-efficiency protection solution for off-chip memory in embedded systems. ERSA 2007: 117-123 - [c59]Dhruv Kumar, Wayne P. Burleson:
Distributed Collaborative Adaptive Sensing: A Unifying Theme for a Junior Level Embedded Systems Course. MSE 2007: 47-48 - [c58]Sheng Xu, Ibis Benito, Wayne P. Burleson:
Thermal Impacts on NoC Interconnects. NOCS 2007: 220 - [c57]Romain Vaslin, Guy Gogniat, Eduardo Braulio Wanderley Netto, Russell Tessier, Wayne P. Burleson:
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. ReCoSoC 2007: 146-153 - [c56]Basab Datta, Wayne P. Burleson:
Low power on-chip thermal sensors based on wires. VLSI-SoC 2007: 258-263 - 2006
- [j24]Lilian Bossuet, Guy Gogniat, Wayne P. Burleson:
Dynamically configurable security for SRAM FPGA bitstreams. Int. J. Embed. Syst. 2(1/2): 73-85 (2006) - [c55]Guy Gogniat, Tilman Wolf, Wayne P. Burleson:
Reconfigurable Security Support for Embedded Systems. HICSS 2006 - [c54]Vishak Venkatraman, Mark A. Anders, Himanshu Kaul, Wayne P. Burleson, Ram Krishnamurthy:
A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects. SoCC 2006: 289-292 - 2005
- [j23]Matthew W. Heath, Wayne P. Burleson, Ian G. Harris:
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. IEEE Trans. Computers 54(12): 1532-1546 (2005) - [j22]Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson:
A reconfigurable, power-efficient adaptive Viterbi decoder. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 484-488 (2005) - [j21]Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson:
An energy-aware active smart card. IEEE Trans. Very Large Scale Integr. Syst. 13(10): 1190-1199 (2005) - [j20]Jeongseon Euh, Jeevan Chittamuru, Wayne P. Burleson:
Power-Aware 3D Computer Graphics Rendering. J. VLSI Signal Process. 39(1-2): 15-33 (2005) - [c53]Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark A. Anders, Saurabh Dighe, Wayne P. Burleson, Ram Krishnamurthy:
A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. ESSCIRC 2005: 199-202 - [c52]Vishak Venkatraman, Wayne P. Burleson:
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. ISQED 2005: 522-527 - [c51]Guy Gogniat, Tilman Wolf, Wayne P. Burleson:
Reconfigurable Security Primitive for Embedded Systems. SoC 2005: 23-28 - [c50]Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne P. Burleson:
Sensing Design Issues in Deep Submicron CMOS SRAMs. ISVLSI 2005: 42-45 - [c49]Jinwook Jang, Sheng Xu, Wayne P. Burleson:
Jitter in Deep Sub-Micron Interconnect. ISVLSI 2005: 84-89 - [c48]Wayne P. Burleson, Sheng Xu:
Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats. MSE 2005: 3-4 - [c47]Guy Gogniat, Wayne P. Burleson, Lilian Bossuet:
Configurable Computing for High-Security/High-Performance Ambient Systems. SAMOS 2005: 72-81 - [c46]Vishak Venkatraman, Wayne P. Burleson:
Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. VLSI Design 2005: 362-367 - 2004
- [j19]Atul Maheshwari, Wayne P. Burleson, Russell Tessier:
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 299-311 (2004) - [j18]Atul Maheshwari, Wayne P. Burleson:
Differential current-sensing for on-chip interconnects. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1321-1329 (2004) - [j17]Prashant Jain, Andrew Laffely, Wayne P. Burleson, Russell Tessier, Dennis Goeckel:
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. J. VLSI Signal Process. 36(1): 27-40 (2004) - [c45]Matthew W. Heath, Wayne P. Burleson, Ian G. Harris:
Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. DATE 2004: 410-415 - [c44]Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson:
Mitigating static power in current-sensed interconnects. ACM Great Lakes Symposium on VLSI 2004: 224-229 - [c43]Lilian Bossuet, Guy Gogniat, Wayne P. Burleson:
Dynamically Configurable Security for SRAM FPGA Bitstreams. IPDPS 2004 - [c42]Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson:
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. SLIP 2004: 69-75 - 2003
- [c41]Atul Maheshwari, Israel Koren, Wayne P. Burleson:
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits. DFT 2003: 597- - [c40]Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar:
Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC 2003: 413-416 - [c39]Aiyappan Natarajan, David Jasinski, Wayne P. Burleson, Russell Tessier:
A hybrid adiabatic content addressable memory for ultra low-power applications. ACM Great Lakes Symposium on VLSI 2003: 72-75 - [c38]Atul Maheshwari, Wayne P. Burleson:
Repeater and current-sensing hybrid circuits for on-chip interconnects. ACM Great Lakes Symposium on VLSI 2003: 269-272 - [c37]Andrew Laffely, Jian Liang, Russell Tessier, Wayne P. Burleson:
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. ICIP (3) 2003: 105-108 - [c36]Lilian Bossuet, Wayne P. Burleson, Guy Gogniat, Vikas Anand, Andrew Laffely, Jean Luc Philippe:
Targeting Tiled Architectures in Design Exploration. IPDPS 2003: 172 - [c35]Srividya Srinivasaraghavan, Wayne P. Burleson:
Interconnect Effort - A Unification of Repeater Insertion and Logical Effort. ISVLSI 2003: 55-61 - [c34]Andrew Laffely, Wayne P. Burleson:
Using System On-A-Chip As A Vehicle For VLSI Design Education. MSE 2003: 148-149 - 2002
- [j16]Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson:
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 50-62 (2002) - [c33]Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson:
A dynamically reconfigurable adaptive viterbi decoder. FPGA 2002: 227-236 - [c32]Atul Maheshwari, Wayne P. Burleson, Russell Tessier:
Trading off Reliability and Power-Consumption in Ultra-low Power Systems. ISQED 2002: 361-366 - [c31]Jeongseon Euh, Jeevan Chittamuru, Wayne P. Burleson:
A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics. PACS 2002: 99-109 - 2001
- [j15]Wayne P. Burleson, Naresh R. Shanbhag:
Guest Editorial: Reconfigurable Signal Processing Systems. J. VLSI Signal Process. 28(1-2): 5-6 (2001) - [j14]Russell Tessier, Wayne P. Burleson:
Reconfigurable Computing for Digital Signal Processing: A Survey. J. VLSI Signal Process. 28(1-2): 7-27 (2001) - [c30]Wayne P. Burleson, Prashant Jain, Subramanian Venkatraman:
Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT. Workshop on Digital and Computational Video 2001: 4-12 - [c29]Wayne P. Burleson, Russell Tessier, Dennis Goeckel, Sriram Swaminathan, Prashant Jain, Jeongseon Euh, Subramanian Venkatraman, Vidhya Thyagarajan:
Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power. ICASSP 2001: 901-904 - [c28]Ankireddy Nalamalpu, Wayne P. Burleson:
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. ISPD 2001: 204-211 - 2000
- [j13]Elias S. Manolakos, Wayne P. Burleson:
Guest Editor's Introduction. J. VLSI Signal Process. 24(1): 5-6 (2000) - [c27]Andrés D. García, Jean-Luc Danger, Wayne P. Burleson:
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220 - [c26]Jeff Peden, Wayne P. Burleson, Chris Leonardo:
The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning. IEEE International Conference on Multimedia and Expo (II) 2000: 593-596 - [c25]Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. ISCAS 2000: 561-564 - [c24]Ankireddy Nalamalpu, Wayne P. Burleson:
Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis. ISCAS 2000: 766-769 - [c23]Jeongseon Euh, Wayne P. Burleson:
Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. PACS 2000: 51-64
1990 – 1999
- 1999
- [j12]Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems:
The spring scheduling coprocessor: a scheduling accelerator. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 38-47 (1999) - [c22]S. R. Park, Wayne P. Burleson:
Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures. FPGA 1999: 81-89 - [c21]Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Power Modelling in Field Programmable Gate Arrays (FPGA). FPL 1999: 396-404 - 1998
- [j11]Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu:
Wave-pipelining: a tutorial and research survey. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 464-474 (1998) - [j10]Bongjin Jung, Wayne P. Burleson:
Efficient VLSI for Lempel-Ziv compression in wireless data communication networks. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 475-483 (1998) - [j9]Wayne P. Burleson, Konstantinos Konstantinides:
Guest Editors' Introduction. J. VLSI Signal Process. 18(2): 87-88 (1998) - [j8]Bongjin Jung, Wayne P. Burleson:
Vlsi Array Architectures for Pyramid Vector Quantization. J. VLSI Signal Process. 18(2): 141-154 (1998) - [j7]Bongjin Jung, Wayne P. Burleson:
Performance optimization of wireless local area networks through VLSI data compression. Wirel. Networks 4(1): 27-39 (1998) - [c20]S. R. Park, Wayne P. Burleson:
Reconfiguration for power saving in real-time motion estimation. ICASSP 1998: 3037-3040 - 1997
- [j6]Yongjin Jeong, Wayne P. Burleson:
VLSI array algorithms and architectures for RSA modular multiplication. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 211-217 (1997) - [j5]Mircea R. Stan, Wayne P. Burleson:
Low-power encodings for global communication in CMOS VLSI. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 444-455 (1997) - [c19]Michael Petronino, Ray Bambha, James R. Carswell, Wayne P. Burleson:
An FPGA-based data acquisition system for a 95 GHz W-band radar. ICASSP 1997: 4105-4108 - 1996
- [c18]Mircea R. Stan, Wayne P. Burleson:
Two dimensional codes for low power. ISLPED 1996: 335-340 - 1995
- [j4]Mircea R. Stan, Wayne P. Burleson:
Bus-invert coding for low-power I/O. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 49-58 (1995) - [c17]Zheng Zhou, Wayne P. Burleson:
Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions. DAC 1995: 546-551 - [c16]Mircea R. Stan, Wayne P. Burleson:
Coding a terminated bus for low power. Great Lakes Symposium on VLSI 1995: 70-73 - [c15]Yongjin Jeong, Wayne P. Burleson:
High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding. ISCAS 1995: 720-723 - 1994
- [j3]Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen:
Analog VLSI for robot path planning. J. VLSI Signal Process. 8(1): 61-73 (1994) - [c14]Bongjin Jung, Yongjin Jeong, Wayne P. Burleson:
Distributed control synthesis for data-dependent iterative algorithms. ASAP 1994: 57-68 - [c13]Wayne P. Burleson:
Using Regular Array Methods for DSP Module Synthesis. HICSS (1) 1994: 58-67 - [c12]Bongjin Jung, Wayne P. Burleson:
A VLSI Systolic Array Architecture for Lempel-Ziv-Based Data Compression. ISCAS 1994: 65-68 - [c11]Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski:
Forum: Wave-pipelining: Is it Practical? ISCAS 1994: 163-166 - 1993
- [c10]Zheng Zhou, Wayne P. Burleson:
Formal descriptions, semantics and verification of VLSI array processors. ASAP 1993: 321-332 - [c9]Bongjin Jung, Wayne P. Burleson:
Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design. ASAP 1993: 442-453 - [c8]Yongjin Jeong, Wayne P. Burleson:
VLSI array synthesis for polynomial GCD computation. ASAP 1993: 536-547 - [c7]Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems:
The Spring Scheduling Co-Processor: A Scheduling Accelerator. ICCD 1993: 140-144 - [c6]J. David Narkiewicz, Wayne P. Burleson:
Rank-order Filtering Algorithms: A Comparison of VLSI Implementations. ISCAS 1993: 1941-1944 - [c5]Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems, Wayne P. Burleson, Jason Ko:
The Spring Scheduling Co-Processor: Design, Use, and Performance. RTSS 1993: 106-111 - 1992
- [c4]Wayne P. Burleson, Bongjin Jung:
ARREST: an interactive graphic analysis tool for VLSI arrays. ASAP 1992: 149-162 - 1991
- [j2]Wayne P. Burleson, Louis L. Scharf:
A VLSI design methodology for distributed arithmetic. J. VLSI Signal Process. 2(4): 235-252 (1991) - [c3]Wayne P. Burleson:
The partitioning problem on VLSI arrays: I/O and local memory complexity. ICASSP 1991: 1217-1220 - [c2]Walter B. Marvin, Wayne P. Burleson:
A Simulator for General Purpose Optical Arrays. ICCD 1991: 486-489 - [c1]Wayne P. Burleson, Louis L. Scharf:
Input/Output Design for VLSI Array Architectures. VLSI 1991: 357-366
1980 – 1989
- 1989
- [j1]Wayne P. Burleson, Louis L. Scharf, Arthur R. Gabriel, Neil H. Endsley:
A systolic VSLI chip for implementing orthogonal transforms. IEEE J. Solid State Circuits 24(2): 466-469 (1989)
Coauthor Index
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