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2020 – today
- 2024
[c32]Sangsu Jeong, Juyoung Oh, Dongsuk Jeon:
A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference. CICC 2024: 1-2- [c31]Minyoung Kang, Sunghoon Kim, Youngmin Park, Sangsu Jeong, Dongsuk Jeon:
A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain. CICC 2024: 1-2 - [c30]Sunghyeon Woo, Sunwoo Lee, Dongsuk Jeon:
ALAM: Averaged Low-Precision Activation for Memory-Efficient Training of Transformer Models. ICLR 2024 - [c29]Sungjin Park, Kwanghyun Shin, Dongkwon Lee, Minyoung Kang, Sunwoo Lee, Youngmin Park, Mingoo Seok, Dongsuk Jeon:
A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy. VLSI Technology and Circuits 2024: 1-2 - [i3]Sunghyeon Woo, Baeseong Park, Byeongwook Kim, Minjung Jo, Sejung Kwon, Dongsuk Jeon, Dongsoo Lee:
DropBP: Accelerating Fine-Tuning of Large Language Models by Dropping Backward Propagation. CoRR abs/2402.17812 (2024) - 2023
- [j22]Hsueh-Cheng Wang
, Siao-Cing Huang, Po-Jui Huang, Kuo-Lun Wang, Yi-Chen Teng, Yu-Ting Ko, Dongsuk Jeon, I-Chen Wu:
Curriculum Reinforcement Learning From Avoiding Collisions to Navigating Among Movable Obstacles in Diverse Environments. IEEE Robotics Autom. Lett. 8(5): 2740-2747 (2023) - [j21]Yejun Ko, Sunghoon Kim, Kwanghyun Shin, Youngmin Park, Sundo Kim, Dongsuk Jeon:
A 65 nm 12.92-nJ/Inference Mixed-Signal Neuromorphic Processor for Image Classification. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2804-2808 (2023) - [j20]Wonjae Lee, Kukbyung Kim, Woohyun Ahn, Jinho Kim, Dongsuk Jeon:
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 749-761 (2023) - [c28]Sunwoo Lee, Jeongwoo Park, Dongsuk Jeon:
A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array. ESSCIRC 2023: 221-224 - [c27]Sunghyeon Woo, Dongsuk Jeon:
Learning with Auxiliary Activation for Memory-Efficient Training. ICLR 2023 - [c26]Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Dongsuk Jeon:
A0.81 mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS. ISSCC 2023: 340-341 - 2022
- [j19]Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon:
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees. IEEE J. Solid State Circuits 57(3): 965-977 (2022) - [j18]Jiwoo Hong, Sunghoon Kim, Dongsuk Jeon:
An Automatic Circuit Design Framework for Level Shifter Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5169-5181 (2022) - [j17]Sunghoon Kim, Wonjae Lee, Sundo Kim, Sungjin Park, Dongsuk Jeon:
An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1687-1691 (2022) - [j16]Youngmin Park, Dongsuk Jeon:
A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1269-1280 (2022) - [c25]Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon:
A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees. AICAS 2022: 499 - [c24]Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon:
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training. ESSCIRC 2022: 145-148 - [c23]Sunwoo Lee, Jeongwoo Park, Dongsuk Jeon:
Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization. ICLR 2022 - 2021
- [j15]Changyu Seong, Wonjae Lee, Dongsuk Jeon:
A Multi-Channel Spike Sorting Processor With Accurate Clustering Algorithm Using Convolutional Autoencoder. IEEE Trans. Biomed. Circuits Syst. 15(6): 1441-1453 (2021) - [j14]Kwanghyun Shin, Dong-Woo Jee, Dongsuk Jeon:
A 65nm 0.6-1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 67-71 (2021) - [j13]Gwangho Lee, Sunwoo Lee, Dongsuk Jeon:
Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1680-1684 (2021) - [c22]Hyeong-Seok Choi, Sungjin Park, Jie Hwan Lee, Hoon Heo, Dongsuk Jeon, Kyogu Lee:
Real-Time Denoising and Dereverberation wtih Tiny Recurrent U-Net. ICASSP 2021: 5789-5793 - [c21]Jiwoo Hong, Sunghoon Kim, Jaeha Kim, Dongsuk Jeon:
Fast Automatic Circuit Optimization Using Deep Learning. ISOCC 2021: 207-210 - [c20]Hanbyeol Kwon, Kwangrae Kim, Dongsuk Jeon, Ki-Seok Chung:
Reducing Refresh Overhead with In-DRAM Error Correction Codes. ISOCC 2021: 211-214 - [c19]Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon:
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree. ISSCC 2021: 148-150 - [c18]Sunghyeon Woo, Jeongwoo Park, Jiwoo Hong, Dongsuk Jeon:
Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection. NeurIPS 2021: 29697-29709 - [i2]Hyeong-Seok Choi, Sungjin Park, Jie Hwan Lee, Hoon Heo, Dongsuk Jeon, Kyogu Lee:
Real-time Denoising and Dereverberation with Tiny Recurrent U-Net. CoRR abs/2102.03207 (2021) - 2020
- [j12]Jeongwoo Park, Juyun Lee, Dongsuk Jeon:
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback. IEEE J. Solid State Circuits 55(1): 108-119 (2020) - [c17]Sungjin Park, Dongsuk Jeon:
A Modified Serial Commutator Architecture for Real-Valued Fast Fourier Transform. SiPS 2020: 1-6 - [i1]Yeonsoo Jeon, Dongsuk Jeon:
A Fast Finite Field Multiplier for SIKE. CoRR abs/2006.14317 (2020)
2010 – 2019
- 2019
- [j11]Junmo Park, Yongin Kwon, Yongjun Park, Dongsuk Jeon:
Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors. IEEE Access 7: 52371-52378 (2019) - [j10]Jiho Kim, Jehee Cha, Jason Jong Kyu Park, Dongsuk Jeon, Yongjun Park:
Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing. IEEE Comput. Archit. Lett. 18(1): 1-5 (2019) - [j9]Juyun Lee, Dong-Woo Jee, Dongsuk Jeon:
Power-up control techniques for reliable SRAM PUF. IEICE Electron. Express 16(13): 20190296 (2019) - [j8]Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 126-137 (2019) - [j7]Suhong Moon, Kwanghyun Shin, Dongsuk Jeon:
Enhancing Reliability of Analog Neural Network Processors. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1455-1459 (2019) - [c16]Jeongwoo Park, Juyun Lee, Dongsuk Jeon:
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback. ISSCC 2019: 140-142 - 2018
- [j6]Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David T. Blaauw:
A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector. IEEE J. Solid State Circuits 53(1): 50-65 (2018) - 2017
- [j5]Dongsuk Jeon, Qing Dong, Yejoong Kim, Xiaolong Wang, Shuai Chen, Hao Yu, David T. Blaauw, Dennis Sylvester:
A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS. IEEE J. Solid State Circuits 52(6): 1628-1642 (2017) - [c15]Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David T. Blaauw:
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. ISSCC 2017: 148-149 - 2016
- [c14]Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS. APCCAS 2016: 734-735 - [c13]Dongsuk Jeon:
Design techniques for ultra-efficient computing. ISOCC 2016: 87-88 - [c12]Dongsuk Jeon, Nathan Ickes, Priyanka Raina, Hsueh-Cheng Wang, Daniela Rus, Anantha P. Chandrakasan:
24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired. ISSCC 2016: 416-417 - [c11]Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j4]Yen-Po Chen, Dongsuk Jeon, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Inhee Lee, Nicholas B. Langhals, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. IEEE J. Solid State Circuits 50(1): 375-390 (2015) - [c10]Dongsuk Jeon, Qing Dong, Yejoong Kim, Xiaolong Wang, Shuai Chen, Hao Yu, David T. Blaauw, Dennis Sylvester:
A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory. VLSIC 2015: 48- - [c9]Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant H. Kruger, David T. Blaauw, Dennis Sylvester:
A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications. VLSIC 2015: 60- - 2014
- [j3]Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. IEEE J. Solid State Circuits 49(5): 1271-1284 (2014) - [c8]Inhee Lee, Yejoong Kim, Suyoung Bang, Gyouho Kim, Hyunsoo Ha, Yen-Po Chen, Dongsuk Jeon, Seokhyun Jeong, Wanyeong Jung, Mohammad Hassan Ghaed, Zhiyoong Foo, Yoonmyung Lee, Jae-Yoon Sim, Dennis Sylvester, David T. Blaauw:
Circuit techniques for miniaturized biomedical sensors. CICC 2014: 1-7 - [c7]Dongsuk Jeon, Yen-Po Chen, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. ISSCC 2014: 416-417 - 2013
- [c6]Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
A low-power VGA full-frame feature extraction processor. ICASSP 2013: 2726-2730 - [c5]Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. ISSCC 2013: 166-167 - 2012
- [j2]Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS. IEEE J. Solid State Circuits 47(1): 23-34 (2012) - [j1]Dongsuk Jeon, Mingoo Seok, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 952-956 (2012) - [c4]Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs. ICICDT 2012: 1-4 - 2011
- [c3]Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. DAC 2011: 990-995 - [c2]Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
Energy-optimized high performance FFT processor. ICASSP 2011: 1701-1704 - [c1]Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. ISSCC 2011: 342-344
Coauthor Index
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last updated on 2024-10-18 19:31 CEST by the dblp team
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