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ORCIDBorivoje Nikolic
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- affiliation: University of California, Berkeley, USA
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2020 – today
- 2024
[j61]Seah Kim
, Jerry Zhao, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration. IEEE Micro 44(4): 97-105 (2024)- [c122]Kevin Laeufer, Brandon Fajardo, Abhik Ahuja, Vighnesh Iyer, Borivoje Nikolic, Koushik Sen:
RTL-Repair: Fast Symbolic Repair of Hardware Design Code. ASPLOS (3) 2024: 867-881 - [c121]Viansa Schmulbach, Jason Kim, Ethan Gao, Nikhil Jha, Ethan Wu, Oliver Yu, Ben Oliveau, Xiangwei Kong, Brendan Roberts, Connor McMahon, Lixiang Yin, Vamber Yang, Brendan Brenner, George Moujaes, Boyu Hao, Lucy Revina, Kevin Anderson, Bryan Ngo, Yufeng Chi, Hongyi Huang, Reza Sajadiany, Raghav Gupta, Ella Schwarz, Jennifer Zhou, Ken Ho, Jerry Zhao, Anita Flynn, Borivoje Nikolic:
NeCTAr and RASoC: Tale of Two Class SoCs for Language Model Interference and Robotics in Intel 16. HCS 2024: 1 - [c120]Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolic, Yakun Sophia Shao, Krste Asanovic:
FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs. ISCA 2024: 501-515 - [c119]Vikram Jain, Wei Tang, Zuoguo Wu, Viansa Schmulbach, Yakun Sophia Shao, Zhengya Zhang, Borivoje Nikolic:
Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED 2024: 1-6 - [i8]Xiaoyu Huang, Yufeng Chi, Ruofeng Wang, Zhongyu Li, Xue Bin Peng, Yakun Sophia Shao, Borivoje Nikolic, Koushil Sreenath:
DiffuseLoco: Real-Time Legged Locomotion Control with Diffusion from Offline Datasets. CoRR abs/2404.19264 (2024) - 2023
- [j60]Borivoje Nikolic, Mototsugu Hamada:
Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 58(4): 897-900 (2023) - [c118]Kevin Laeufer, Vighnesh Iyer, David Biancolin, Jonathan Bachrach, Borivoje Nikolic, Koushik Sen:
Simulator Independent Coverage for RTL Hardware Languages. ASPLOS (3) 2023: 606-615 - [c117]Harrison Liew, Farhana Sheikh, David Kehlet, Borivoje Nikolic:
Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects. CICC 2023: 1-6 - [c116]Felicia Guo, Nayiri Krzysztofowicz, Alex Moreno, Jeffrey Ni, Daniel Lovell, Yufeng Chi, Kareem Ahmad, Sherwin Afshar, Josh Alexander, Dylan Brater, Cheng Cao, Daniel Fan, Ryan Lund, Jackson Paddock, Griffin Prechter, Troy Sheldon, Shreesha Sreedhara, Anson Tsai, Eric Wu, Kerry Yu, Daniel Fritchman, Aviral Pandey, Ali Niknejad, Kristofer S. J. Pister, Borivoje Nikolic:
A Heterogeneous SoC for Bluetooth LE in 28nm. HCS 2023: 1-11 - [c115]Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks. HPCA 2023: 828-841 - [c114]Sagar Karandikar, Aniruddha N. Udipi, Junsun Choi, Joonho Whangbo, Jerry Zhao, Svilen Kanev, Edwin Lim, Jyrki Alakuijala, Vrishab Madduri, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic, Parthasarathy Ranganathan:
CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. ISCA 2023: 39:1-39:17 - [c113]Dima Nikiforov, Shengjun Chris Dong, Chengyi Lux Zhang, Seah Kim, Borivoje Nikolic, Yakun Sophia Shao:
RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation. ISCA 2023: 64:1-64:15 - [c112]Seah Kim, Jerry Zhao, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads. MICRO 2023: 62-76 - [d1]Dima Nikiforov, Shengjun Chris Dong, Chengyi Lux Zhang, Seah Kim, Borivoje Nikolic, Yakun Sophia Shao:
RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation. Zenodo, 2023
- [i7]Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks. CoRR abs/2305.05843 (2023) - 2022
- [j59]Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woorham Bae, Sean Huang, Vladimir M. Milovanovic, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. IEEE J. Solid State Circuits 57(1): 140-152 (2022) - [j58]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong:
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits 57(2): 573-585 (2022) - [j57]Yusuke Oike, Borivoje Nikolic:
Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 57(4): 983-985 (2022) - [j56]Keertana Settaluri, Zhaokai Liu, Rishubh Khurana, Arash Mirhaj, Rajeev Jain, Borivoje Nikolic:
Automated Design of Analog Circuits Using Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2794-2807 (2022) - [j55]Yue Dai, Maryam Eslami Rasekh, Seyed Hadi Mirfarshbafan, Harrison Liew, Alexandra Gallyas-Sanhueza, James Dunn, Upamanyu Madhow, Christoph Studer, Borivoje Nikolic:
An Adaptable and Scalable Generator of Distributed Massive MIMO Baseband Processing Systems. J. Signal Process. Syst. 94(10): 989-1003 (2022) - [c111]Harrison Liew, Daniel Grubb, John Wright, Colin Schmidt, Nayiri Krzysztofowicz, Adam M. Izraelevitz, Edward Wang, Krste Asanovic, Jonathan Bachrach, Borivoje Nikolic:
Hammer: a modular and reusable physical design flow tool: invited. DAC 2022: 1335-1338 - [c110]Borivoje Nikolic:
ML for Analog Design: Good Progress, but More to Do. MLCAD 2022: 53-54 - 2021
- [j54]Emily Naviasky, Lorenzo Iotti, Greg LaCaille, Borivoje Nikolic, Elad Alon, Ali M. Niknejad:
A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO. IEEE J. Solid State Circuits 56(12): 3811-3826 (2021) - [j53]David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolic, Jonathan Bachrach, Krste Asanovic:
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim. IEEE Micro 41(4): 58-66 (2021) - [j52]Jaeduk Han, Woo-Rham Bae, Eric Chang, Zhongkai Wang, Borivoje Nikolic, Elad Alon:
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1012-1022 (2021) - [c109]Zhongkai Wang, Minsoo Choi, Eric Chang, John Charles Wright, Wooham Bae, Sijun Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt, Ayan Biswas, Borivoje Nikolic, Elad Alon:
An Automated and Process-Portable Generator for Phase-Locked Loop. DAC 2021: 511-516 - [c108]Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert J. Ou, Colin Schmidt, Samuel Steffl, John Charles Wright, Ion Stoica, Jonathan Ragan-Kelley, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. DAC 2021: 769-774 - [c107]Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt, John Charles Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic:
A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. ESSCIRC 2021: 259-262 - [c106]Yue Dai, Greg LaCaille, Harrison Liew, James Dunn, Borivoje Nikolic:
A Scalable Massive MIMO Uplink Baseband Processing Generator. ICC 2021: 1-6 - [c105]Alon Amid, Albert J. Ou, Krste Asanovic, Yakun Sophia Shao, Borivoje Nikolic:
Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs. ISCAS 2021: 1-5 - [c104]Jingyi Xu, Sehoon Kim, Borivoje Nikolic, Yakun Sophia Shao:
Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms. ISPASS 2021: 226-228 - [c103]Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. ISSCC 2021: 58-60 - [c102]Emily Naviasky, Lorenzo Iotti, Greg LaCaille, Borivoje Nikolic, Elad Alon, Ali M. Niknejad:
14.1 A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver in 28nm CMOS. ISSCC 2021: 218-220 - [c101]Sagar Karandikar, Chris Leary, Chris Kennelly, Jerry Zhao, Dinesh Parimi, Borivoje Nikolic, Krste Asanovic, Parthasarathy Ranganathan:
A Hardware Accelerator for Protocol Buffers. MICRO 2021: 462-478 - [c100]Yue Dai, Harrison Liew, Maryam Eslami Rasekh, Seyed Hadi Mirfarshbafan, Alexandra Gallyas-Sanhueza, James Dunn, Upamanyu Madhow, Christoph Studer, Borivoje Nikolic:
A Scalable Generator for Massive MIMO Baseband Processing Systems with Beamspace Channel Estimation. SiPS 2021: 182-187 - [c99]Ryan Lund, Connor McMahon, Daniel D. Garcia, Borivoje Nikolic:
Improved Processor Design Project Testing. WCAE 2021: 1-7 - 2020
- [j51]Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic:
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. IEEE Micro 40(4): 10-21 (2020) - [j50]John Charles Wright, Colin Schmidt, Ben Keller, Daniel Palmer Dabbelt, Jaehwa Kwak, Vighnesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Borivoje Nikolic:
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2721-2725 (2020) - [c98]Sagar Karandikar, Albert J. Ou, Alon Amid, Howard Mao, Randy H. Katz, Borivoje Nikolic, Krste Asanovic:
FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design. ASPLOS 2020: 715-731 - [c97]Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Jonathan Bachrach, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic:
Invited: Chipyard - An Integrated SoC Research and Implementation Environment. DAC 2020: 1-6 - [c96]Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic:
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs. DATE 2020: 490-495 - [c95]Greg LaCaille, James Dunn, Antonio Puglielli, Lorenzo Iotti, Sameet Ramakrishnan, Lucas Calderin, Zhenghan Lin, Emily Naviasky, Borivoje Nikolic, Ali M. Niknejad, Elad Alon:
Design and Demonstration of a Scalable Massive MIMO Uplink at E-Band. ICC Workshops 2020: 1-6 - [c94]Edward Wang, Colin Schmidt, Adam M. Izraelevitz, John Charles Wright, Borivoje Nikolic, Elad Alon, Jonathan Bachrach:
A Methodology for Reusable Physical Design. ISQED 2020: 243-249 - [c93]Paul Rigge, Vasuki Narasimha Swamy, Christian Nelson, Fredrik Tufvesson, Anant Sahai, Borivoje Nikolic:
Wireless Channel Dynamics for Relay Selection under Ultra-Reliable Low-Latency Communication. PIMRC 2020: 1-6
2010 – 2019
- 2019
- [j49]Vasuki Narasimha Swamy, Paul Rigge, Gireeja Ranade, Borivoje Nikolic, Anant Sahai:
Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications. IEEE J. Sel. Areas Commun. 37(4): 705-720 (2019) - [j48]Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic:
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. IEEE J. Solid State Circuits 54(7): 1993-2008 (2019) - [j47]Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019) - [j46]Christopher Celio, Pi-Feng Chiu, Krste Asanovic, Borivoje Nikolic, David A. Patterson:
BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS. IEEE Micro 39(2): 52-60 (2019) - [j45]Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Howard Katz, Jonathan Bachrach, Krste Asanovic:
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. IEEE Micro 39(3): 56-65 (2019) - [c92]Qichen Zhang, Yun Chen, Xiaoyang Zeng, Keshab K. Parhi, Borivoje Nikolic:
A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. A-SSCC 2019: 271-274 - [c91]Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon:
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC 2019: 1-4 - [c90]Elad Alon, Krste Asanovic, Jonathan Bachrach, Borivoje Nikolic:
Open-Source EDA Tools and IP, A View from the Trenches. DAC 2019: 79 - [c89]Vighnesh Iyer, Donggyu Kim, Borivoje Nikolic, Sanjit A. Seshia:
RTL bug localization through LTL specification mining (WIP). MEMOCODE 2019: 5:1-5:5 - [i6]Hasan Genc, Ameer Haj-Ali, Vighnesh Iyer, Alon Amid, Howard Mao, John Charles Wright, Colin Schmidt, Jerry Zhao, Albert J. Ou, Max Banister, Yakun Sophia Shao, Borivoje Nikolic, Ion Stoica, Krste Asanovic:
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures. CoRR abs/1911.09925 (2019) - 2018
- [j44]Bonjern Yang, Eric Chang, Ali M. Niknejad, Borivoje Nikolic, Elad Alon:
A 65-nm CMOS I/Q RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering. IEEE J. Solid State Circuits 53(4): 1127-1138 (2018) - [j43]Woo-Rham Bae, Kyung Jean Yoon, Taeksang Song, Borivoje Nikolic:
A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1839-1843 (2018) - [c88]Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC 2018: 285-288 - [c87]Stevo Bailey, John Wright, Nandish Mehta, Rachel Hochman, Robert Jarnot, Vladimir M. Milovanovic, Dan Werthimer, Borivoje Nikolic:
A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator. CICC 2018: 1-4 - [c86]Eric Chang, Jaeduk Han, Woo-Rham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje Nikolic, Elad Alon:
BAG2: A process-portable framework for generator-based AMS circuit design. CICC 2018: 1-8 - [c85]Angie Wang, Paul Rigge, Adam M. Izraelevitz, Chick Markley, Jonathan Bachrach, Borivoje Nikolic:
ACED: a hardware library for generating DSP systems. DAC 2018: 61:1-61:6 - [c84]Borivoje Nikolic, Elad Alon, Krste Asanovic:
Generating the Next Wave of Custom Silicon. ESSCIRC 2018: 6-11 - [c83]Borivoje Nikolic:
Energy-Efficient Design in FDSOI. ESSCIRC 2018: 258 - [c82]Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic:
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. ESSCIRC 2018: 322-325 - [c81]Borivoje Nikolic:
Energy-Efficient Design in FDSOI. ESSDERC 2018: 182 - [c80]Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy H. Katz, Jonathan Bachrach, Krste Asanovic:
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. ISCA 2018: 29-42 - [c79]Vasuki Narasimha Swamy, Paul Rigge, Gireeja Ranade, Borivoje Nikolic, Anant Sahai:
Predicting Wireless Channels for Ultra-Reliable Low-Latency Communications. ISIT 2018: 2609-2613 - [c78]Amy Whitcombe, Borivoje Nikolic, Farhana Sheikh, Erkan Alpman, Ashoke Ravi:
A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET. VLSI Circuits 2018: 23-24 - [c77]Pi-Feng Chiu, Christopher Celio, Krste Asanovic, David A. Patterson, Borivoje Nikolic:
An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS. VLSI Circuits 2018: 61-62 - [i5]Vasuki Narasimha Swamy, Paul Rigge, Gireeja Ranade, Anant Sahai, Borivoje Nikolic:
Network Coding for Real-time Wireless Communication for Automation. CoRR abs/1803.05143 (2018) - [i4]Vasuki Narasimha Swamy, Paul Rigge, Gireeja Ranade, Borivoje Nikolic, Anant Sahai:
Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications. CoRR abs/1806.08777 (2018) - 2017
- [j42]Xiao Xiao, Amanda Pratt, Bonjern Yang, Angie Wang, Ali M. Niknejad, Elad Alon, Borivoje Nikolic:
A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use. IEEE J. Solid State Circuits 52(7): 1768-1782 (2017) - [j41]Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee, Milovan Blagojevic, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. IEEE J. Solid State Circuits 52(7): 1863-1875 (2017) - [j40]Lucas Calderin, Sameet Ramakrishnan, Antonio Puglielli, Elad Alon, Borivoje Nikolic, Ali M. Niknejad:
Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems. IEEE J. Solid State Circuits 52(8): 2038-2054 (2017) - [j39]Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic:
Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor. IEEE J. Solid State Circuits 52(10): 2589-2600 (2017) - [j38]Woo-Rham Bae, Borivoje Nikolic, Deog-Kyoon Jeong:
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3543-3547 (2017) - [j37]Vasuki Narasimha Swamy, Sahaana Suri, Paul Rigge, Matthew Weiner, Gireeja Ranade, Anant Sahai, Borivoje Nikolic:
Real-Time Cooperative Communication for Automation Over Wireless. IEEE Trans. Wirel. Commun. 16(11): 7168-7183 (2017) - [c76]Yi-An Li, Monte Mar, Borivoje Nikolic, Ali M. Niknejad:
On-chip spur and phase noise cancellation techniques. A-SSCC 2017: 109-112 - [c75]Aikaterini Papadopoulou, Vladimir M. Milovanovic, Borivoje Nikolic:
A low-voltage low-offset dual strong-arm latch comparator. A-SSCC 2017: 281-284 - [c74]Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic:
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. A-SSCC 2017: 305-308 - [c73]Aikaterini Papadopoulou, Borivoje Nikolic:
A yield optimization methodology for mixed-signal circuits. CICC 2017: 1-4 - 2016
- [j36]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [j35]Jaehwa Kwak, Borivoje Nikolic:
A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI. IEEE J. Solid State Circuits 51(10): 2368-2379 (2016) - [j34]Antonio Puglielli, Andrew Townley, Greg LaCaille, Vladimir M. Milovanovic, Pengpeng Lu, Konstantin Trotskovsky, Amy Whitcombe, Nathan Narevsky, Gregory Wright, Thomas A. Courtade, Elad Alon, Borivoje Nikolic, Ali M. Niknejad:
Design of Energy- and Cost-Efficient Massive MIMO Arrays. Proc. IEEE 104(3): 586-606 (2016) - [c72]Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic:
Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. A-SSCC 2016: 121-124 - [c71]Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic:
On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. A-SSCC 2016: 125-128 - [c70]Pi-Feng Chiu, Brian Zimmer, Borivoje Nikolic:
A double-tail sense amplifier for low-voltage SRAM in 28nm technology. A-SSCC 2016: 181-184 - [c69]Xiao Xiao, Amanda Pratt, Ali M. Niknejad, Elad Alon, Borivoje Nikolic:
A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use. ESSCIRC 2016: 181-184 - [c68]Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic:
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. ESSCIRC 2016: 269-272 - [c67]Amy Whitcombe, Scott Taylor, Martin Denham, Vladimir M. Milovanovic, Borivoje Nikolic:
On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS. ESSDERC 2016: 248-251 - [c66]Angie Wang, Jonathan Bachrach, Borivoje Nikolic:
A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines. ICASSP 2016: 1016-1020 - [c65]Antonio Puglielli, Greg LaCaille, Ali M. Niknejad, Gregory Wright, Borivoje Nikolic, Elad Alon:
Phase noise scaling and tracking in OFDM multi-user beamforming arrays. ICC 2016: 1-6 - [c64]Milovan Blagojevic, Martin Cochet, Ben Keller, Philippe Flatresse, Andrei Vladimirescu, Borivoje Nikolic:
A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. VLSI Circuits 2016: 1-2 - [c63]Sameet Ramakrishnan, Lucas Calderin, Antonio Puglielli, Elad Alon, Ali M. Niknejad, Borivoje Nikolic:
A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage. VLSI Circuits 2016: 1-2 - [c62]Vasuki Narasimha Swamy, Paul Rigge, Gireeja Ranade, Anant Sahai, Borivoje Nikolic:
Network coding for high-reliability low-latency wireless control. WCNC 2016: 1-7 - [c61]Vasuki Narasimha Swamy, Paul Rigge, Gireeja Ranade, Anant Sahai, Borivoje Nikolic:
Network coding for high-reliability low-latency wireless control. WCNC Workshops 2016: 138-144 - [i3]Vasuki Narasimha Swamy, Sahaana Suri, Paul Rigge, Matthew Weiner, Gireeja Ranade, Anant Sahai, Borivoje Nikolic:
Cooperative Communication for Control over Wireless. CoRR abs/1609.02968 (2016) - 2015
- [j33]Pi-Feng Chiu, Borivoje Nikolic:
A Differential 2R Crosspoint RRAM Array With Zero Standby Current. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 461-465 (2015) - [j32]Ruzica Jevtic, Hanh-Phuc Le, Milovan Blagojevic, Stevo Bailey, Krste Asanovic, Elad Alon, Borivoje Nikolic:
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 723-730 (2015) - [c60]Jaehwa Kwak, Borivoje Nikolic:
A 550-2260MHz self-adjustable clock generator in 28nm FDSOI. A-SSCC 2015: 1-4 - [c59]Borivoje Nikolic:
Simpler, more efficient design. ESSCIRC 2015: 20-25 - [c58]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic:
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - [c57]Antonio Puglielli, Nathan Narevsky, Pengpeng Lu, Thomas A. Courtade, Gregory Wright, Borivoje Nikolic, Elad Alon:
A scalable massive MIMO array architecture based on common modules. ICC Workshops 2015: 1310-1315 - [c56]Vasuki Narasimha Swamy, Sahaana Suri, Paul Rigge, Matthew Weiner, Gireeja Ranade, Anant Sahai, Borivoje Nikolic:
Cooperative communication for high-reliability low-latency wireless control. ICC 2015: 4380-4386 - [c55]Stephane Le Tuai, Borivoje Nikolic, Tetsuya Iizuka, Ichiro Fujimori:
F1: High-speed interleaved ADCs. ISSCC 2015: 1-2 - [c54]D. Danilovic, Andreia Cathelin, Andrei Vladimirescu, Borivoje Nikolic:
Design considerations for low-noise transconductance amplifiers in 28nm UTBB-FDSOI. NEWCAS 2015: 1-4 - [c53]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2014
- [j31]Charles Wu, Elad Alon, Borivoje Nikolic:
A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver. IEEE J. Solid State Circuits 49(7): 1639-1652 (2014) - [c52]Nai-Chung Kuo, Bonjern Yang, Chaoying Wu, Lingkai Kong, Angie Wang, Michael Reiha, Elad Alon, Ali M. Niknejad, Borivoje Nikolic:
A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers. A-SSCC 2014: 345-348 - [c51]Brian Zimmer, Olivier Thomas, Seng Oon Toh, Taylor Vincent, Krste Asanovic, Borivoje Nikolic:
Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM. ESSDERC 2014: 98-101 - [c50]Matthew Weiner, Milos Jorgovanovic, Anant Sahai, Borivoje Nikolic:
Design of a low-latency, high-reliability wireless communication system for control applications. ICC 2014: 3829-3835 - [c49]Matthew Weiner, Milovan Blagojevic, Sergey Skotnikov, Andreas Burg, Philippe Flatresse, Borivoje Nikolic:
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI. ISSCC 2014: 464-465 - 2013
- [j30]Vinayak Nagpal, I-Hsiang Wang, Milos Jorgovanovic, David Tse, Borivoje Nikolic:
Coding and System Design for Quantize-Map-and-Forward Relaying. IEEE J. Sel. Areas Commun. 31(8): 1423-1435 (2013) - [j29]Dusan Stepanovic, Borivoje Nikolic:
A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 48(4): 971-982 (2013) - [c48]Charles Wu, Borivoje Nikolic:
A 0.4 GHz - 4 GHz direct RF-to-digital ΣΔ multi-mode receiver. ESSCIRC 2013: 275-278 - [c47]Milos Jorgovanovic, Matthew Weiner, David Tse, Borivoje Nikolic, I-Hsiang Wang, Vinayak Nagpal:
Relay scheduling and interference cancellation for quantize-map-and-forward cooperative relaying. ISIT 2013: 1959-1963 - 2012
- [j28]Brian Zimmer, Seng Oon Toh, Huy Vo, Yunsup Lee, Olivier Thomas, Krste Asanovic, Borivoje Nikolic:
SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 853-857 (2012) - [j27]Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 564-568 (2012) - [c46]Dusan Stepanovic, Borivoje Nikolic:
A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS. VLSIC 2012: 84-85 - [i2]Vinayak Nagpal, I-Hsiang Wang, Milos Jorgovanovic, David Tse, Borivoje Nikolic:
Coding and System Design for Quantize-Map-and-Forward Relaying. CoRR abs/1209.4679 (2012) - 2011
- [j26]Ji-Hoon Park, Brian C. Richards, Borivoje Nikolic:
A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band. IEEE J. Solid State Circuits 46(11): 2524-2534 (2011) - [j25]Seng Oon Toh, Zheng Guo, Tsu-Jae King Liu, Borivoje Nikolic:
Characterization of Dynamic SRAM Stability in 45 nm CMOS. IEEE J. Solid State Circuits 46(11): 2702-2712 (2011) - [j24]Socrates D. Vamvakos, Vladimir Stojanovic, Borivoje Nikolic:
Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1211-1224 (2011) - [j23]Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos:
Technology Variability From a Design Perspective. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 1996-2009 (2011) - [c45]Borivoje Nikolic:
Managing variability for ultimate energy efficiency. ECCTD 2011: 1-4 - [c44]Matthew Weiner, Borivoje Nikolic, Zhengya Zhang:
LDPC decoder architecture for high-data rate personal-area networks. ISCAS 2011: 1784-1787 - 2010
- [j22]Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic:
An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors. IEEE J. Solid State Circuits 45(4): 843-855 (2010) - [j21]Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic:
Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes. IEEE Trans. Inf. Theory 56(1): 181-201 (2010) - [j20]Andrew Carlson, Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King Liu, Borivoje Nikolic:
SRAM Read/Write Margin Enhancements Using FinFETs. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 887-900 (2010) - [c43]Vinayak Nagpal, I-Hsiang Wang, Milos Jorgovanovic, David Tse, Borivoje Nikolic:
Quantize-map-and-forward relaying: Coding and system design. Allerton 2010: 443-450 - [c42]Borivoje Nikolic, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Ji-Hoon Park, Seng Oon Toh:
Technology variability from a design perspective. CICC 2010: 1-8 - [c41]Lynn T.-N. Wang, Nuo Xu, Seng Oon Toh, Andrew R. Neureuther, Tsu-Jae King Liu, Borivoje Nikolic:
Parameter-specific ring oscillator for process monitoring at the 45 nm node. CICC 2010: 1-4 - [c40]Borivoje Nikolic, Changhwan Shin, Min Hee Cho, Xin Sun, Tsu-Jae King Liu, Bich-Yen Nguyen:
SRAM design in fully-depleted SOI technology. ISCAS 2010: 1707-1710 - [c39]Jason Tsai, Seng Oon Toh, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic:
SRAM stability characterization using tunable ring oscillators in 45nm CMOS. ISSCC 2010: 354-355
2000 – 2009
- 2009
- [j19]Lara Dolecek, Pamela Lee, Zhengya Zhang, Venkat Anantharam, Borivoje Nikolic, Martin J. Wainwright:
Predicting error floors of structured LDPC codes: deterministic bounds and estimates. IEEE J. Sel. Areas Commun. 27(6): 908-917 (2009) - [j18]Radu Zlatanovici, Sean Kao, Borivoje Nikolic:
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example. IEEE J. Solid State Circuits 44(2): 569-583 (2009) - [j17]Liang-Teck Pang, Borivoje Nikolic:
Measurements and Analysis of Process Variability in 90nmCMOS. IEEE J. Solid State Circuits 44(5): 1655-1663 (2009) - [j16]Liang-Teck Pang, Kun Qian, Costas J. Spanos, Borivoje Nikolic:
Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology. IEEE J. Solid State Circuits 44(8): 2233-2243 (2009) - [j15]Zheng Guo, Andrew Carlson, Liang-Teck Pang, Kenneth Duong, Tsu-Jae King Liu, Borivoje Nikolic:
Large-Scale SRAM Variability Characterization in 45 nm CMOS. IEEE J. Solid State Circuits 44(11): 3174-3192 (2009) - [j14]Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright:
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices. IEEE Trans. Commun. 57(11): 3258-3268 (2009) - [c38]Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic:
A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. CICC 2009: 499-502 - [c37]Ji-Hoon Park, Liang-Teck Pang, Kenneth Duong, Borivoje Nikolic:
Fixed- and variable-length ring oscillators for variability characterization in 45nm CMOS. CICC 2009: 519-522 - [c36]Sokratis D. Vamvakos, Vladimir Stojanovic, Borivoje Nikolic:
Discrete-time, cyclostationary phase-locked loop model for jitter analysis. CICC 2009: 637-640 - [c35]Vinayak Nagpal, Sameer Pawar, David Tse, Borivoje Nikolic:
Cooperative multiplexing in the multiple antenna half duplex relay channel. ISIT 2009: 1438-1442 - [i1]Vinayak Nagpal, Sameer Pawar, David Tse, Borivoje Nikolic:
Cooperative Multiplexing in the Multiple Antenna Half Duplex Relay Channel. CoRR abs/0901.2164 (2009) - 2008
- [c34]Liang-Teck Pang, Borivoje Nikolic:
Measurement and analysis of variability in 45nm strained-Si CMOS technology. CICC 2008: 129-132 - [c33]Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic:
Background ADC calibration in digital domain. CICC 2008: 301-304 - [c32]Andrew Carlson, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic:
Compensation of systematic variations through optimal biasing of SRAM wordlines. CICC 2008: 411-414 - [c31]Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. ESSCIRC 2008: 90-93 - [c30]Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright:
Lowering LDPC Error Floors by Postprocessing. GLOBECOM 2008: 3074-3079 - [c29]Pamela Lee, Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Borivoje Nikolic, Martin J. Wainwright:
Error floors in LDPC codes: Fast simulation, bounds and hardware emulation. ISIT 2008: 444-448 - 2007
- [j13]Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen:
Power and Area Minimization for Multidimensional Signal Processing. IEEE J. Solid State Circuits 42(4): 922-934 (2007) - [c28]Dejan Markovic, Chen Chang, Brian C. Richards, Hayden Kwok-Hay So, Borivoje Nikolic, Robert W. Brodersen:
ASIC Design and Verification in an FPGA Environment. CICC 2007: 737-740 - [c27]Radu Marculescu, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli:
Fresh air: the emerging landscape of design for networked embedded systems. CODES+ISSS 2007: 124 - [c26]Zhengya Zhang, Lara Dolecek, Martin J. Wainwright, Venkat Anantharam, Borivoje Nikolic:
Quantization Effects in Low-Density Parity-Check Decoders. ICC 2007: 6231-6237 - [c25]Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic:
Analysis of Absorbing Sets for Array-Based LDPC Codes. ICC 2007: 6261-6268 - [c24]Borivoje Nikolic:
Power-Limited Design. ICECS 2007: 927-930 - [c23]Zhengya Zhang, Renaldi Winoto, Ahmad Bahai, Borivoje Nikolic:
Peak-to-Average Power Ratio Reduction in an FDM Broadcast System. SiPS 2007: 25-30 - 2006
- [j12]Radu Zlatanovici, Borivoje Nikolic:
Power - Performance Optimization for Custom Digital Circuits. J. Low Power Electron. 2(1): 113-120 (2006) - [j11]Jan M. Rabaey, Fernando De Bernardinis, Ali M. Niknejad, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli:
L. Embedding Mixed-Signal Design in Systems-on-Chip. Proc. IEEE 94(6): 1070-1088 (2006) - [c22]Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Venkat Anantharam, Martin J. Wainwright:
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation. GLOBECOM 2006 - [c21]Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen:
Power and Area Efficient VLSI Architectures for Communication Signal Processing. ICC 2006: 3223-3228 - [c20]Sean Kao, Radu Zlatanovici, Borivoje Nikolic:
A 240ps 64b carry-lookahead adder in 90nm CMOS. ISSCC 2006: 1735-1744 - 2005
- [c19]Yun Chiu, Borivoje Nikolic, Paul R. Gray:
Scaling of analog-to-digital converters into ultra-deep-submicron CMOS. CICC 2005: 375-382 - [c18]Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic:
FinFET-based SRAM design. ISLPED 2005: 2-7 - [c17]Radu Zlatanovici, Borivoje Nikolic:
Power - Performance Optimization for Custom Digital Circuits. PATMOS 2005: 404-414 - 2004
- [j10]Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolic:
A shared-well dual-supply-voltage 64-bit ALU. IEEE J. Solid State Circuits 39(3): 494-500 (2004) - [j9]Dejan Markovic, Vladimir Stojanovic, Borivoje Nikolic, Mark A. Horowitz, Robert W. Brodersen:
Methods for true energy-performance optimization. IEEE J. Solid State Circuits 39(8): 1282-1293 (2004) - [j8]Yun Chiu, Paul R. Gray, Borivoje Nikolic:
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J. Solid State Circuits 39(12): 2139-2151 (2004) - [j7]Yun Chiu, Cheongyuen W. Tsang, Borivoje Nikolic, Paul R. Gray:
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 38-46 (2004) - [j6]Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic:
Level conversion for dual-supply systems. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 185-195 (2004) - [c16]Edward Liao, Engling Yeo, Borivoje Nikolic:
Low-density parity-check code constructions for hardware implementation. ICC 2004: 2573-2577 - [c15]Sokratis D. Vamvakos, Carl Werner, Borivoje Nikolic:
Phase-locked loop architecture for adaptive jitter optimization. ISCAS (4) 2004: 161-164 - 2003
- [j5]Engling Yeo, Stephanie Augsburger, W. Rhett Davis, Borivoje Nikolic:
A 500-Mb/s soft-output Viterbi decoder. IEEE J. Solid State Circuits 38(7): 1234-1241 (2003) - [c14]Radu Zlatanovici, Borivoje Nikolic:
Power-performance optimal 64-bit carry-lookahead adders. ESSCIRC 2003: 321-324 - [c13]Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic:
Level conversion for dual-supply systems. ISLPED 2003: 164-167 - [c12]Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic:
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. IEEE International Workshop on Rapid System Prototyping 2003: 148- - 2002
- [j4]W. Rhett Davis, Ning Zhang, Kevin Camera, Dejan Markovic, Tina Smilkstein, M. Josie Ammer, Engling Yeo, Stephanie Augsburger, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high-throughput low-power dedicated signal processing systems. IEEE J. Solid State Circuits 37(3): 420-431 (2002) - [c11]Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic:
Methods for true power minimization. ICCAD 2002: 35-42 - [c10]Stephanie Augsburger, Borivoje Nikolic:
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction. ICCD 2002: 316-321 - 2001
- [j3]Michael Leung, Borivoje Nikolic, Leo Ki-Chun Fu, Taehyun Jeon:
Reduced complexity sequence detection for high-order partial response channels. IEEE J. Sel. Areas Commun. 19(4): 649-661 (2001) - [c9]W. Rhett Davis, Ning Zhang, Kevin Camera, Fred Chen, Dejan Markovic, Nathan Chan, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high throughput, low power dedicated signal processing systems. CICC 2001: 545-548 - [c8]David G. Chinnery, Borivoje Nikolic, Kurt Keutzer:
Achieving 550Mhz in an ASIC Methodology. DAC 2001: 420-425 - [c7]Julio Leao da Silva Jr., J. Shamberger, M. Josie Ammer, Chunlong Guo, Suet-Fei Li, Rahul C. Shah, Tim Tuan, Michael Sheets, Jan M. Rabaey, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli, Paul K. Wright:
Design methodology for PicoRadio networks. DATE 2001: 314-325 - [c6]Dragan Petrovic, Borivoje Nikolic, Kannan Ramchandran:
List Viterbi decoding with continuous error detection for magnetic recording. GLOBECOM 2001: 3007-3011 - [c5]Engling Yeo, Payam Pakzad, Borivoje Nikolic, Venkat Anantharam:
High throughput low-density parity-check decoder architectures. GLOBECOM 2001: 3019-3024 - [c4]Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen:
Analysis and design of low-energy flip-flops. ISLPED 2001: 52-55 - 2000
- [j2]Borivoje Nikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, Michael Ming-Tak Leung:
Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Solid State Circuits 35(6): 876-884 (2000) - [j1]Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 460-463 (2000)
1990 – 1999
- 1999
- [c3]Borivoje Nikolic, Michael Leung, Leo Ki-Chun Fu:
A rate 8/9 sliding block trellis code with stationary detector for magnetic recording. ICC 1999: 1653-1657 - 1998
- [c2]Jelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic:
CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor. ICECS 1998: 349-352 - 1997
- [c1]Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED 1997: 323-327
Coauthor Index
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