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2020 – today
- 2024
[j50]Sota Kano, Tetsuya Iizuka:
150GHz Fundamental Oscillator Utilizing Transmission-Line-Based Inter-Stage Matching in 130nm SiGe BiCMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 741-745 (2024)- [j49]Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka:
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 746-750 (2024) - [j48]Masaru Osada
, Zule Xu, Zunsong Yang, Tetsuya Iizuka:
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits 59(7): 2171-2184 (2024) - [j47]Ken Takeuchi, Tetsuya Iizuka, Kazuko Nishimura, Jerald Yoo:
Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 59(10): 3119-3122 (2024) - [j46]Haoming Zhang, Shuowei Li, Tetsuya Iizuka:
A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 938-951 (2024) - [c69]Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham:
A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS 2024: 1-5 - [c68]Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li:
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. VLSI Technology and Circuits 2024: 1-2 - [i2]Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, Tetsuya Iizuka:
Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons. CoRR abs/2409.11612 (2024) - 2023
- [j45]Akira Matsuoka, Yo Kumano, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka:
A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2759-2763 (2023) - [j44]Ryoya Shibata, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka:
Analysis of SAR ADC Performance Enhancement Utilizing Stochastic Resonance. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4324-4328 (2023) - [c67]Haoming Zhang, Shuowei Li, Tetsuya Iizuka:
Dynamic Circuit Characterization and a Single Ring-Oscillator-Based Test Structure for Its Timing Parameter Extraction. ICICDT 2023: 76-79 - [c66]Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka:
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit. ICICDT 2023: 88-91 - [c65]Zhenyu Cheng, Zunsong Yang, Yuyang Zhu, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka:
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit. ICICDT 2023: 92-95 - [c64]Haoyuan Gao, Hao Xu, Xinyi Lin, Yan Liu, Zhidong Tang, Xufeng Kou, Xingyu Zhang, Tetsuya Iizuka, Na Yan:
INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications. ICTA 2023: 1-4 - [c63]Hisashi Inoue, Hiroto Tamura, Ai Kitoh, Xiangyu Chen, Zolboo Byambadorj, Takeaki Yajima, Yasushi Hotta, Tetsuya Iizuka, Gouhei Tanaka, Isao H. Inoue:
Long-time-constant leaky-integrating oxygen-vacancy drift-diffusion FET for human-interactive spiking reservoir computing. VLSI Technology and Circuits 2023: 1-2 - [c62]Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka:
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j43]Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada:
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. 105-C(10): 544-551 (2022) - [j42]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 378-388 (2022) - [j41]Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka:
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5072-5084 (2022) - [j40]Akira Matsuoka, Tomohiro Nezuka, Tetsuya Iizuka:
Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 944-948 (2022) - [c61]Masaru Osada, Zule Xu, Tetsuya Iizuka:
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC 2022: 245-248 - [c60]Nguyen Ngoc Mai Khanh, Daisuke Yamazaki, Tetsuya Iizuka:
140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS. ICICDT 2022: 73-76 - [c59]Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka:
A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. ISCAS 2022: 3224-3228 - [c58]Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka:
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits 2022: 10-11 - [i1]Xiangyu Chen, Takeaki Yajima, Hisashi Inoue, Isao H. Inoue, Zolboo Byambadorj, Tetsuya Iizuka:
CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks. CoRR abs/2208.11881 (2022) - 2021
- [j39]Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka:
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2153-2162 (2021) - [c57]Tetsuya Iizuka, Hao Xu, Asad A. Abidi:
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. ESSCIRC 2021: 381-386 - [c56]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada:
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT 2021: 1-4 - [c55]Zule Xu, Masaru Osada, Tetsuya Iizuka:
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits 2021: 1-2 - 2020
- [j38]Daisuke Yamazaki, Yoshitaka Otsuki, Takafumi Hara, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka:
11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS. IET Circuits Devices Syst. 14(3): 322-326 (2020) - [j37]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 298-308 (2020) - [j36]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. 67-I(12): 5561-5573 (2020) - [c54]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS 2020: 1-6 - [c53]Masaru Osada, Zule Xu, Tetsuya Iizuka:
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j35]Yoshitaka Otsuki, Daisuke Yamazaki, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka:
A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS. IEICE Electron. Express 16(6): 20190051 (2019) - [j34]Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada:
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16(19): 20190390 (2019) - [j33]Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura:
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express 16(19): 20190546 (2019) - [j32]Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68(7): 2519-2530 (2019) - [j31]Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 11-19 (2019) - [c52]Naoki Ojima, Zule Xu, Tetsuya Iizuka:
A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. NEWCAS 2019: 1-4 - 2018
- [j30]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34(2): 147-161 (2018) - [j29]Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda:
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15(5) (2018) - [j28]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 410-424 (2018) - [j27]Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada:
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. 101-C(4): 218-223 (2018) - [j26]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. 101-C(4): 292-298 (2018) - [j25]Tetsuya Iizuka, Asad A. Abidi:
A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit. IEICE Trans. Electron. 101-C(7): 432-443 (2018) - [j24]Tetsuya Iizuka, Takaaki Ito, Asad A. Abidi:
Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1157-1173 (2018) - [j23]Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada:
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. 67(4): 745-753 (2018) - [c51]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS 2018: 408-411 - [c50]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) 2018: 1-13 - [c49]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC 2018: 55-58 - 2017
- [j22]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 200-209 (2017) - [j21]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. 100-C(9): 736-745 (2017) - [j20]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2741-2749 (2017) - [c48]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC 2017: 23-24 - [c47]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
CMOS-on-quartz pulse generator for low power applications. ASP-DAC 2017: 29-30 - [c46]Colin McAndrew, Tetsuya Iizuka:
Session 4 - Modeling and measurement of mixed-signal circuits. CICC 2017: 1 - [c45]Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging 2017: 18-23 - [c44]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS 2017: 1-2 - [c43]Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS 2017: 1-4 - [c42]Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS 2017: 231-234 - [c41]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS 2017: 318-321 - [c40]Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada:
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS 2017: 1-3 - [c39]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS 2017: 257-260 - 2016
- [j19]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25(3): 1640017:1-1640017:16 (2016) - [j18]Tetsuya Iizuka, Asad A. Abidi:
FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1325-1336 (2016) - [j17]Tetsuya Iizuka, Asad A. Abidi:
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1337-1348 (2016) - [c38]Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC 2016: 313-316 - [c37]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE 2016: 517-522 - [c36]Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada:
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC 2016: 301-304 - [c35]Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS 2016: 29-32 - [c34]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Resonant power supply noise reduction using a triangular active charge injection. ICECS 2016: 113-116 - [c33]Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC 2016: 1-8 - 2015
- [j16]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. 64(4): 840-848 (2015) - [c32]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC 2015: 1-4 - [c31]Robert C. Aitken, Tetsuya Iizuka:
Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects. CICC 2015: 1 - [c30]Tetsuya Iizuka, Takahiro J. Yamaguchi:
Session 3 - Optical interconnect and reliability enhancement techniques. CICC 2015: 1 - [c29]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS 2015: 131-136 - [c28]Stephane Le Tuai, Borivoje Nikolic, Tetsuya Iizuka, Ichiro Fujimori:
F1: High-speed interleaved ADCs. ISSCC 2015: 1-2 - [c27]Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS 2015: 1-4 - 2014
- [j15]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1688-1698 (2014) - [c26]Manoj Sachdev, Tetsuya Iizuka:
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. CICC 2014: 1 - [c25]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS 2014: 111-114 - 2013
- [j14]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2458-2466 (2013) - [c24]Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC 2013: 255-260 - [c23]Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada:
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC 2013: 1-4 - [c22]Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC 2013: 1-4 - [c21]Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Pulse Width controlled PLL and its automated design flow. ICECS 2013: 5-8 - [c20]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD 2013: 69-76 - [c19]Boris Murmann, Tetsuya Iizuka:
Session 26 overview: High-speed data converters. ISSCC 2013: 460-461 - 2012
- [j13]Tetsuya Iizuka, Kunihiro Asada:
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. 95-C(4): 627-634 (2012) - [j12]Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada:
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. 95-C(4): 661-667 (2012) - [j11]Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. 95-C(12): 1857-1863 (2012) - [c18]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium 2012: 252-257 - [c17]Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada:
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC 2012: 1-4 - 2011
- [j10]Tetsuya Iizuka, Kunihiro Asada:
All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express 8(1): 20-25 (2011) - [j9]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. 94-C(4): 487-494 (2011) - [j8]Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. 94-C(4): 654-662 (2011) - [j7]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. 94-C(6): 1098-1104 (2011) - [j6]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. J. Next Gener. Inf. Technol. 2(4): 1-9 (2011) - [c16]Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80 - [c15]Tetsuya Iizuka, Kunihiro Asada:
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS 2011: 115-120 - [c14]Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada:
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC 2011: 399-402 - 2010
- [c13]Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172 - [c12]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC 2010: 182-185 - [c11]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC 2010: 266-269
2000 – 2009
- 2007
- [j5]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 716-720 (2007) - [c10]Kenichiro Kurihara, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. ICECS 2007: 1296-1299 - [c9]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED 2007: 776-781 - 2006
- [c8]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE 2006: 884-889 - [c7]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. ICECS 2006: 704-707 - [c6]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS 2006 - 2005
- [j4]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1957-1963 (2005) - [j3]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3485-3491 (2005) - [c5]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI 2005: 74-77 - 2004
- [c4]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154 - [c3]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380 - 2000
- [c2]Mariko Yoshida, Tetsuya Iizuka, Hisako Shiohara, Masanori Ishiguro:
Mining sequential patterns including time intervals. Data Mining and Knowledge Discovery: Theory, Tools, and Technology 2000: 213-220
1990 – 1999
- 1998
- [c1]Yuichi Iizuka, Hisako Shiohara, Tetsuya Iizuka, Seiji Isobe:
Automatic Visualization Method for Visual Data Mining. PAKDD 1998: 173-185
1980 – 1989
- 1989
- [j2]Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato:
A 32 kbyte integrated cache memory. IEEE J. Solid State Circuits 24(4): 881-888 (1989) - 1988
- [j1]Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka:
A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. IEEE J. Solid State Circuits 23(1): 12-19 (1988)
Coauthor Index
[j43] [c56] [j34] [j32] [j31] [j30] [j29] [j28] [j27] [j26] [j23] [c51] [c50] [c49] [j22] [j21] [j20] [c48] [c47] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [j19] [c38] [c37] [c36] [c35] [c34] [c33] [j16] [c32] [c29] [c27] [j15] [c25] [j14] [c24] [c23] [c22] [c21] [c20] [j13] [j12] [j11] [c18] [c17] [j10] [j9] [j8] [j7] [j6] [c16] [c15] [c14] [c13] [c12] [c11] [j5] [c10] [c9] [c8] [c7] [c6] [j4] [j3] [c5] [c4] [c3]
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