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ORCIDLars Hedrich
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- affiliation: Goethe University Frankfurt am Main, Germany
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2020 – today
- 2024
[c50]Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler:
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. DAC 2024: 51:1-51:6- 2023
- [c49]Sascha Schmalhofer, Marwin Möller, Nikoletta Katsaouni
, Marcel H. Schulz, Lars Hedrich:
Debugging Low Power Analog Neural Networks for Edge Computing. DATE 2023: 1-2 - 2022
- [j8]Nikoletta Katsaouni, Florian Aul, Lukas Krischker, Sascha Schmalhofer, Lars Hedrich, Marcel H. Schulz:
Energy efficient convolutional neural networks for arrhythmia detection. Array 13: 100127 (2022) - 2021
- [c48]Ahmad Tarraf, Lars Hedrich:
Towards Compositional Abstraction of Analog Neuronal Networks. CCWC 2021: 34-37 - 2020
- [j7]Ahmad Tarraf, Lars Hedrich:
From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction. it Inf. Technol. 62(5-6): 257-270 (2020) - [c47]Niklas Kochdumper, Ahmad Tarraf, Malgorzata Rechmal, Markus Olbrich, Lars Hedrich, Matthias Althoff:
Establishing Reachset Conformance for the Formal Analysis of Analog Circuits. ASP-DAC 2020: 199-204 - [c46]Ahmad Tarraf, Lars Hedrich, Niklas Kochdumper, Malgorzata Rechmal-Lesse, Markus Olbrich:
Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. ISVLSI 2020: 7-12
2010 – 2019
- 2019
- [c45]Ahmad Tarraf, Lars Hedrich:
Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata. DATE 2019: 1451-1456 - [c44]Ömer Ibrahim Erduran, Mirjam Minor, Lars Hedrich, Ahmad Tarraf, Frederik Ruehl, Hans Schroth:
Multi-agent Learning for Energy-Aware Placement of Autonomous Vehicles. ICMLA 2019: 1671-1678 - [c43]Yashwant Kolluru, Rolando Dölling, Lars Hedrich:
Numerical Simulations of Vibro-acoustic Behaviors related to Drive Train Assemblies. ISSE 2019: 1-8 - [c42]Ahmad Tarraf, Lars Hedrich:
Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices. SMACD 2019: 133-136 - 2018
- [j6]Philipp Tertel, Lars Hedrich:
Real-time emulation of block-based analog circuits on an FPGA. Integr. 63: 373-382 (2018) - 2017
- [c41]Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher:
Novel metrics for Analog Mixed-Signal coverage. DDECS 2017: 97-102 - [c40]Andreas Furtig, Moritz Paschke, Lars Hedrich:
Comparing code coverage metrics for analog behavioral models. SMACD 2017: 1-4 - [c39]Philipp Tertel, Lars Hedrich:
Real-time emulation of block-based analog circuits on an FPGA. SMACD 2017: 1-4 - 2016
- [c38]Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher:
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. DATE 2016: 1102-1111 - [c37]Andreas Furtig, Sebastian Steinhorst, Lars Hedrich:
Feature based state space coverage of analog circuits. FDL 2016: 1-7 - 2015
- [j5]Julius von Rosen, Felix Salfelder, Lars Hedrich, Benjamin Betting, Uwe Brinkschulte:
A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture. Integr. 48: 55-71 (2015) - [j4]Markus Meissner, Lars Hedrich:
FEATS: Framework for Explorative Analog Topology Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 213-226 (2015) - [c36]Julius von Rosen, Markus Meissner, Lars Hedrich:
Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. DATE 2015: 912-915 - [c35]Felix Salfelder, Lars Hedrich:
Ageing simulation of analogue circuits and systems using adaptive transient evaluation. DATE 2015: 1261-1264 - [c34]Tim Dackermann, Rolando Dölling, Lars Hedrich:
Method for system level vibro-acoustic gear modeling and simulation of electro-mechanical drive trains. ISSE 2015: 60-65 - 2014
- [j3]Mingyu Ma, Lars Hedrich, Christian Sporrer:
ASDeX: a formal specification for analog circuit enabling a full automated design validation. Des. Autom. Embed. Syst. 18(1-2): 99-118 (2014) - 2013
- [c33]Benjamin Betting, Julius von Rosen, Lars Hedrich, Uwe Brinkschulte:
A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip. ARCS 2013: 122-133 - [c32]Matthias Kauer, Swaminathan Naranayaswami, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Lars Hedrich:
Modular system-level architecture for concurrent cell balancing. DAC 2013: 155:1-155:10 - 2012
- [c31]Markus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich:
Fast isomorphism testing for a graph-based analog circuit synthesis framework. DATE 2012: 757-762 - [c30]Sebastian Steinhorst, Lars Hedrich:
Analog assertion-based verification on partial state space representations using ASL. FDL 2012: 98-104 - [c29]Sebastian Steinhorst, Lars Hedrich:
Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits. ICCAD 2012: 202-209 - [c28]Christoph Leineweber, Mathias Pacher, Benjamin Betting, Julius von Rosen, Uwe Brinkschulte, Lars Hedrich:
Detection and Defense Strategies against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip. ISORC 2012: 135-143 - [c27]Sebastian Steinhorst, Lars Hedrich:
Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification. VLSI-SoC 2012: 135-140 - 2011
- [c26]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich:
Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78 - [c25]Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores:
Automated constraint-driven topology synthesis for analog circuits. DATE 2011: 1662-1665 - [c24]Mingyu Ma, Lars Hedrich, Christian Sporrer:
A machine-readable specification of analog circuits for integration into a validation flow. FDL 2011: 1-8 - [c23]Oliver Mitea, Markus Meissner, Lars Hedrich:
Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. VLSI-SoC 2011: 78-81 - 2010
- [j2]Sebastian Steinhorst, Lars Hedrich:
Advanced methods for equivalence checking of analog circuits with strong nonlinearities. Formal Methods Syst. Des. 36(2): 131-147 (2010) - [c22]Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich:
Towards assertion-based verification of heterogeneous system designs. DATE 2010: 1171-1176 - [c21]Sebastian Steinhorst, Lars Hedrich:
Improving verification coverage of analog circuit blocks by state space-guided transient simulation. ISCAS 2010: 645-648
2000 – 2009
- 2009
- [c20]Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang:
Formal approaches to analog circuit verification. DATE 2009: 724-729 - 2008
- [j1]Alexander Jesser, Stefan Lämmermann, Alexander Pacholik, Roland Weiss, Jürgen Ruf, Lars Hedrich, Wolfgang Fengler, Thomas Kropf, Wolfgang Rosenstiel:
Advanced Assertion-Based Design for Mixed-Signal Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3548-3555 (2008) - [c19]Alexander Jesser, Lars Hedrich:
A symbolic approach for mixed-signal model checking. ASP-DAC 2008: 404-409 - [c18]Sebastian Steinhorst, Lars Hedrich:
Model Checking of Analog Systems using an Analog Specification Language. DATE 2008: 324-329 - [c17]Xiaoying Wang, Lars Hedrich:
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. DATE 2008: 800-803 - 2006
- [c16]Xiaoying Wang, Lars Hedrich:
An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. ASP-DAC 2006: 700-705 - [c15]Xiaoying Wang, Lars Hedrich:
Hierarchical exploration and selection of transistor-topologies for analog circuit design. ISCAS 2006 - [c14]Alexander Jesser, Markus Wedler, Lars Hedrich, Wolfgang Kunz:
A case study on applying bounded model checking to analog circuit verification. MBMV 2006: 106-113 - [c13]Ralf Klausen, Lars Hedrich, Erich Barke:
Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV 2006: 122-131 - 2005
- [c12]Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke:
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. FAC 2005: 37-52 - 2004
- [c11]Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke:
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE 2004: 442-447 - 2002
- [c10]Walter Hartong, Lars Hedrich, Erich Barke:
On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV 2002: 401-413 - [c9]Walter Hartong, Lars Hedrich, Erich Barke:
Model checking algorithms for analog verification. DAC 2002: 542-547 - [c8]Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke:
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE 2002: 274-278 - [c7]Walter Hartong, Lars Hedrich, Erich Barke:
An Approach to Model Checking for Nonlinear Analog Systems. DATE 2002: 1080 - [c6]Andreas C. Lemke, Lars Hedrich, Erich Barke:
Analog circuit sizing based on formal methods using affine arithmetic. ICCAD 2002: 486-489 - 2000
- [c5]Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke:
A current driven routing and verification methodology for analog applications. DAC 2000: 385-389
1990 – 1999
- 1999
- [c4]Tim Wichmann, Ralf Popp, Walter Hartong, Lars Hedrich:
On the Simplification of Nonlinear DAE Systems in Analog Circuit Design. CASC 1999: 485-498 - 1998
- [c3]Lars Hedrich, Erich Barke:
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE 1998: 649-654 - 1997
- [b1]Lars Hedrich:
Ansätze zur formalen Verifikation analoger Schaltungen. University of Hanover, VDI-Verlag 1997, ISBN 3-18-325720-3, pp. 1-128 - 1996
- [c2]Carsten Borchers, Lars Hedrich, Erich Barke:
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC 1996: 236-239 - 1995
- [c1]Lars Hedrich, Erich Barke:
A formal approach to nonlinear analog circuit verification. ICCAD 1995: 123-127
Coauthor Index
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last updated on 2024-11-13 23:51 CET by the dblp team
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