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2020 – today
- 2024
[j45]Kaoru Yamashita
, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro:
A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. IEEE J. Solid State Circuits 59(3): 740-752 (2024)- [j44]Yi Tan, Cheng Huang, Hiroki Ishikuro:
Design of Dual Lower Bound Hysteresis Control in Switched-Capacitor DC-DC Converter for Optimum Efficiency and Transient Speed in Wide Loading Range for IoT Application. IEEE J. Solid State Circuits 59(6): 1823-1834 (2024) - [j43]Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro:
Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS. Microelectron. J. 144: 106066 (2024) - [j42]Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro:
A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator. Microelectron. J. 153: 106435 (2024) - [c84]Paul Shine Eugine, Peter Toth, Kaoru Yamashita, Sebastian Halama, Christian Ospelkaus, Hiroki Ishikuro, Vadim Issakov:
A Direct Digital Synthesizer-Based Arbitrary Waveform Generator for Envelope Modulation in Trapped-Ion Quantum Computer Operating at 4K. BCICTS 2024: 50-53 - [c83]Alexander Meyer, Kaoru Yamashita, Adilet Dossanov, Martin Maier, Finn Stapelfeldt, Yerzhan Kudabay, Peter Toth, Fa Foster Dai, Hiroki Ishikuro, Vadim Issakov:
A 10-bit 100kS/s SAR ADC With a Monotonic Capacitor Switching Procedure for Single-Ended Inputs in 22nm CMOS FDSOI. ISCAS 2024: 1-5 - [c82]Yi Tan, Jianqiang Jiang, Cheng Huang, Hiroki Ishikuro:
Orthogonal Decomposition Based Digital Controller Design for Hybrid Converter. MWSCAS 2024: 1378-1382 - 2023
- [j41]Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka:
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. IEEE J. Solid State Circuits 58(2): 428-438 (2023) - [j40]Peter Toth, Alexander Meyer, Sebastian Halama, Hiroki Ishikuro, Vadim Issakov:
A Cryogenic 12 GHz Frequency Doubler With Temperature Compensation for Trapped-Ion Quantum Computer. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3877-3881 (2023) - [c81]Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro:
A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. CICC 2023: 1-2 - [c80]Chia-Wei Pai, Hiroki Ishikuro:
A High-Speed Low-Power Two-Stage Comparator with Regeneration Enhancement and Through Current Suppression Techniques. MWSCAS 2023: 79-83 - [c79]Billy Mårtensson, Hinata Mitomo, Baktash Behmanesh, Naoji Matsuhisa, Hiroki Ishikuro:
An Oscillator with Inductively Coupled Resonators for Readout of Stretchable Resistive Strain Sensor. MWSCAS 2023: 177-181 - 2022
- [j39]Shinya Kajiyama, Yutaka Igarashi, Toru Yazaki, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yohei Nakamura, Yoshihiro Hayashi, Takuya Kaneko, Hiroki Ishikuro, Taizo Yamawaki:
T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 153-165 (2022) - [j38]Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro:
Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 463-473 (2022) - [c78]Tomohisa Miyao, Takahisa Tanaka, Itsuki Imanishi, Masayuki Ichikawa, Shuya Nakagawa, Hiroki Ishikuro, Toshitsugu Sakamoto, Munehiro Tada, Ken Uchida:
Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors. DRC 2022: 1-2 - [c77]Yi Tan, Hiroki Ishikuro:
A Dual-Mode 2: 1 Switched Capacitor Converter with >65% Efficiency over 1000x Load Current Range and One Clock Cycle Transient Response. ICECS 2022 2022: 1-4 - 2021
- [c76]Peter Toth, Hiroki Ishikuro:
An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. ASP-DAC 2021: 9-10 - [c75]Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro:
Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting. ASP-DAC 2021: 11-12 - [c74]Peter Toth, Hiroki Ishikuro:
An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. ASP-DAC 2021: 105-106 - [c73]Yi Tan, Hiroki Ishikuro:
A Switched-Capacitor DC-DC Converter with >77.3% Efficiency and 80 ns Active Transient Response in 40 µA - 4 mA Load Current Range. ESSCIRC 2021: 355-358 - [c72]Yuya Maekawa, Hiroki Ishikuro:
An Amp-Less Time-Domain AC Bridge for Impedance Spectroscopy with 1-bit $\Delta \Sigma$ DAC. ICECS 2021: 1-5 - [c71]Kaoru Yamashita, Tokihiko Shimura, Shun Sato, Naoji Matsuhisa, Hiroki Ishikuro:
Robust Readout Circuit with Leakage Current Cancellation Technique for Stretchable Touch Sensors. ICECS 2021: 1-5 - [c70]Yuya Fuketa, Kohei Tatehora, Yohsuke Shiiki, Shuya Nakagawa, Hiroki Ishikuro:
A Fast Wake-Up and High Accuracy Sensor Interface by Synchronous Sampling with Power-Efficient Switching Regulator. MWSCAS 2021: 154-157 - 2020
- [c69]Yuya Maekawa, Syuya Nakagawa, Hiroki Ishikuro:
A Highly Linear Amp-Less Interface Circuit for Capacitive Sensors with ΔΣ C-DAC. APCCAS 2020: 118-120 - [c68]Tatsuya Ishikawa, Chia-Wei Pai, Hiroki Ishikuro:
A Linearity Testing of Cascaded Analog Mixed-Signal Blocks Using SEIR Method. I2MTC 2020: 1-6 - [c67]Shuya Nakagawa, Takumi Miyazaki, Hiroki Ishikuro:
A Digital-to-Resistance Converter with an Automatic Offset Calibration Method for Evaluating Dynamic Performance of Resistive Sensor Readout Circuits. I2MTC 2020: 1-5 - [c66]Shuya Nakagawa, Takumi Miyazaki, Hiroki Ishikuro:
A High-Resolution Oscillator Based Resistance-to-Digital Converter with Non-Linearity Canceling Feedback by ΔΣ Modulated Variable Resistor. ISCAS 2020: 1-5 - [c65]Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro:
A 0.12V Fully Integrated Charge Pump with Gate Voltage Optimization for Energy Harvesting Applications. ISCAS 2020: 1-5 - [c64]Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Takahisa Tanaka, Ken Uchida, Hiroki Ishikuro:
A Wide Range and High Accuracy Sensor Interface with Switching Regulator for Coin-Cell Powered Tiny Wireless Sensor Node. ISCAS 2020: 1-4 - [c63]Yi Tan, Hiroki Ishikuro:
A Discrete-Time Model for Frequency Modulated Charge Pumps with Synchronized Controller. MWSCAS 2020: 929-932 - [c62]Peter Toth, Hiroki Ishikuro:
A Wide Input-Range, Low-Power and Highly Flexible 18 Bit Time-to-Digital Converter with Compact Differential Circuit Topology. MWSCAS 2020: 937-940
2010 – 2019
- 2019
- [j37]Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura:
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2575-2586 (2019) - [c61]Yohsuke Shiiki, Hiroki Ishikuro:
A High Accuracy Opamp-less Interface Circuit for 2-D Cross-Point Resistive Sensor Array with Switch Resistance Calibration. APCCAS 2019: 105-108 - [c60]Peter Toth, Hiroki Ishikuro:
A Differential-Ring-Oscillator with up to 35 dBc/Hz Phase Noise Improving Amplitude Feedback Loop for Ultra Low Power Systems. ICECS 2019: 350-353 - [c59]Takumi Miyazaki, Shuya Nakagawa, Hiroki Ishikuro:
High-Resolution Auto-Balancing Wheatstone-Bridge with Successive Approximation of ΔΣ-Modulated Digitally Controlled Variable Resistor. ICECS 2019: 474-477 - [c58]Yohsuke Shiiki, Hiroki Ishikuro:
Interface with Opamp Output-Impedance Calibration Technique for a Large Integrated 2-D Resistive Sensor Array. ISCAS 2019: 1-5 - [c57]Takahisa Tanaka, K. Tabuchi, Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Tsunaki Takahashi, R. Shimizu, Hiroki Ishikuro, Tadahiro Kuroda, T. Yanagida, Ken Uchida:
Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. VLSI Circuits 2019: 158- - 2018
- [j36]Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants. IEEE J. Solid State Circuits 53(2): 538-551 (2018) - [c56]Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro:
Design of resource sharing reconfigurable ΔΣ SAR-ADC. ASP-DAC 2018: 317-318 - [c55]Shuya Nakagawa, Kaito Horikoshi, Hiroki Ishikuro:
A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter. MWSCAS 2018: 242-245 - 2017
- [c54]Hiroki Ishikuro:
Distortion and its suppression in low-power delta-sigma modulator. MWSCAS 2017: 452-455 - 2016
- [j35]Kaoru Kohira, Hiroki Ishikuro:
A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link. IEICE Trans. Electron. 99-C(4): 458-465 (2016) - [j34]Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro:
A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe. IEICE Trans. Electron. 99-C(10): 1164-1173 (2016) - [j33]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits 51(4): 1041-1050 (2016) - [j32]Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A Near-Optimum 13.56 MHz CMOS Active Rectifier With Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants. IEEE J. Solid State Circuits 51(8): 1797-1809 (2016) - [j31]Atsutake Kosuge, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 265-275 (2016) - [c53]Takuma Suguro, Hiroki Ishikuro:
Low power DT delta-sigma modulator with ring amplifier SC-integrator. ISCAS 2016: 2006-2009 - [c52]Kohei Yamada, Yosuke Toyama, Hiroki Ishikuro:
A programmable ΔΣ SAR-ADC with charge shuttling technique. ISOCC 2016: 51-52 - [c51]Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro:
A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe. RWS 2016: 10-12 - [c50]Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants. VLSI Circuits 2016: 1-2 - 2015
- [j30]Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. IEEE J. Solid State Circuits 50(4): 932-945 (2015) - [j29]Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2122-2131 (2015) - [j28]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 356-368 (2015) - [c49]Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro:
Dual-output wireless power delivery system for small size large volume wireless memory card. ASP-DAC 2015: 32-33 - [c48]Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants. CICC 2015: 1-4 - [c47]Masaki Yonekura, Hiroki Ishikuro:
I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique. ESSCIRC 2015: 229-232 - [c46]Toru Kawajiri, Takahiro Moroto, Hiroki Ishikuro:
A low EMI SIDO wireless power transfer system with 10μsec response time. ESSCIRC 2015: 253-256 - [c45]Koki Tanaka, Ryo Saito, Hiroki Ishikuro:
A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration. ESSCIRC 2015: 327-330 - [c44]Isao Saito, Kaoru Kohira, Hiroki Ishikuro:
Fence loaded antenna coupler for high-band UWB with steep cutoff characteristics. RWS 2015: 56-58 - [c43]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC 2015: 128- - 2014
- [j27]Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits 49(1): 223-231 (2014) - [c42]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ASP-DAC 2014: 31-32 - [c41]Takahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, Hiroki Ishikuro:
A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing. ESSCIRC 2014: 387-390 - [c40]Kentaro Yoshioka, Hiroki Ishikuro:
A 13b SAR ADC with eye-opening VCO based comparator. ESSCIRC 2014: 411-414 - [c39]Atsutake Kosuge, Shu Ishizuka, Lechang Liu, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. ISSCC 2014: 496-497 - [c38]Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. VLSIC 2014: 1-2 - 2013
- [j26]Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 443-452 (2013) - [j25]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. 96-C(6): 820-827 (2013) - [j24]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits 48(3): 790-800 (2013) - [j23]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE J. Solid State Circuits 48(11): 2628-2636 (2013) - [c37]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC 2013: 91-92 - [c36]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC 2013: 111-112 - [c35]Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, Hiroki Ishikuro:
A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier. ISCAS 2013: 809-812 - [c34]Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro:
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. ISCAS 2013: 1576-1579 - [c33]Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC 2013: 200-201 - [c32]Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
3D clock distribution using vertically/horizontally-coupled resonators. ISSCC 2013: 258-259 - [c31]Teruo Jyo, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA. RWS 2013: 217-219 - 2012
- [j22]Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing. IEICE Trans. Electron. 95-C(4): 668-676 (2012) - [j21]Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro:
High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Trans. Electron. 95-C(4): 752-760 (2012) - [j20]Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE J. Solid State Circuits 47(4): 1022-1030 (2012) - [j19]Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda:
A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. IEEE J. Solid State Circuits 47(5): 1232-1241 (2012) - [j18]Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda:
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits 47(10): 2484-2495 (2012) - [j17]Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits 47(10): 2496-2504 (2012) - [j16]Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro:
1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. IEEE J. Solid State Circuits 47(11): 2576-2585 (2012) - [j15]Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits 47(11): 2643-2653 (2012) - [j14]Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1285-1294 (2012) - [c30]Abul Hasan Johari, Hiroki Ishikuro:
0.6 - 3.6 GHz wideband operation with high phase resolution On-Chip Network Analyzer. APCCAS 2012: 539-542 - [c29]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC 2012: 1-4 - [c28]Lechang Liu, Hiroki Ishikuro, Tadahiro Kuroda:
A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. CICC 2012: 1-4 - [c27]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. ESSCIRC 2012: 381-384 - [c26]Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC 2012: 52-54 - [c25]Ryota Shinoda, Kazutoshi Tomita, Yuya Hasegawa, Hiroki Ishikuro:
Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching. ISSCC 2012: 288-290 - [c24]Takayuki Abe, Yuxiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda:
A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. ISSCC 2012: 442-444 - [c23]Takeshi Matsubara, Isamu Hayashi, Abul Hasan Johari, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. RWS 2012: 71-74 - 2011
- [j13]Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1902-1907 (2011) - [j12]Kiichi Niitsu, Vishwesh V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda:
A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2058-2066 (2011) - [c22]Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. A-SSCC 2011: 145-148 - [c21]Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro:
1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. A-SSCC 2011: 177-180 - [c20]Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC 2011: 205-208 - [c19]Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro:
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. ESSCIRC 2011: 471-474 - [c18]Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6W/25mm2 inductive power transfer for non-contact wafer-level testing. ISSCC 2011: 230-232 - [c17]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12Gb/s non-contact interface with coupled transmission lines. ISSCC 2011: 492-494 - 2010
- [j11]Hiroki Ishikuro, Tadahiro Kuroda:
Wireless proximity interfaces with a pulse-based inductive coupling technique. IEEE Commun. Mag. 48(10): 192-199 (2010) - [j10]Vishal V. Kulkarni, Hiroki Ishikuro, Tadahiro Kuroda:
A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme. IEICE Trans. Electron. 93-C(1): 120-127 (2010) - [j9]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits 45(1): 134-141 (2010) - [j8]Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2269-2278 (2010) - [j7]Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1238-1243 (2010) - [c16]Abul Hasan Johari, Satoshi Kumaki, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro:
0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit. APCCAS 2010: 232-235 - [c15]Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro:
A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. APCCAS 2010: 1015-1018 - [c14]Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro:
A 0.5V 6-bit scalable phase interpolator. APCCAS 2010: 1019-1022 - [c13]Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda:
A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. ISSCC 2010: 264-265
2000 – 2009
- 2009
- [j6]Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda:
A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. IEEE J. Solid State Circuits 44(2): 394-403 (2009) - [j5]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits 44(3): 947-955 (2009) - [c12]Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda:
A wireless real-time on-chip bus trace system. ASP-DAC 2009: 91-92 - [c11]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC 2009: 449-452 - [c10]Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC 2009: 244-245 - 2008
- [j4]Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. 91-C(2): 200-205 (2008) - [j3]Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits 43(1): 285-291 (2008) - [c9]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC 2008: 298-299 - 2007
- [j2]Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai:
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. IEICE Trans. Electron. 90-C(4): 786-792 (2007) - [c8]Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda:
Wideband Inductive-coupling Interface for High-performance Portable System. CICC 2007: 13-20 - [c7]Vishal V. Kulkarni, Muhammad Muqsith, Hiroki Ishikuro, Tadahiro Kuroda:
A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. CICC 2007: 647-650 - [c6]Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC 2007: 358-608 - [c5]Hiroki Ishikuro, Toshihiko Sugahara, Tadahiro Kuroda:
An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. ISSCC 2007: 360-608 - 2006
- [c4]Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Takayasu Sakurai:
Compact outside-rail circuit structure by single-cascode two-transistor topology. CICC 2006: 619-622 - 2005
- [j1]Toru Tanzawa, Kenichi Agawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Masayuki Koizumi, Fumitoshi Hatori:
A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters. IEICE Trans. Electron. 88-C(4): 490-495 (2005) - [c3]Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada:
A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. CICC 2005: 583-586 - [c2]Hideaki Majima, Hiroki Ishikuro, Kenichi Agawa, Mototsugu Hamada:
A 1.2-V CMOS complex bandpass filter with a tunable center frequency. ESSCIRC 2005: 327-330 - 2004
- [c1]Toru Tanzawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Kenichi Agawa, Masayuki Koizumi, Fumitoshi Hatori:
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter. CICC 2004: 273-276
Coauthor Index
[c57] [j33] [j31] [j29] [j28] [c43] [j27] [c42] [c39] [j26] [j25] [j24] [j23] [c37] [c36] [c34] [c33] [c32] [c31] [j22] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [c29] [c28] [c27] [c26] [c24] [c23] [j13] [j12] [c22] [c21] [c20] [c19] [c18] [c17] [j11] [j10] [j9] [j8] [j7] [c13] [j6] [j5] [c12] [c11] [c10] [j4] [j3] [c9] [c8] [c7] [c6] [c5]
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