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ORCIDNORCAS 2015: Oslo, Norway
- Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, October 26-28, 2015. IEEE 2015, ISBN 978-1-4673-6576-5
- Alexander N. Deleuran, Nicklas Lindbjerg, Martin K. Pedersen, Pere Llimos Muntal
, Ivan H. H. Jørgensen:
A capacitor-free, fast transient response linear voltage regulator in a 180nm CMOS. 1-4 - David Bierbuesse, Pierre Bousseaud, Renato Negra:
Inductorless and cross-coupled wideband LNA with high linearity. 1-4 - Viola Rieger, Henning Schütz, Stefan Gambach, Albrecht Rothermel:
On-chip spatial filter for subretinal implants. 1-4 - Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz:
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. 1-4 - Nagaveni Vamsi, Akash Gupta, Ashudeb Dutta, Shiv Govind Singh:
Ultra low power on-chip hybrid start-up for wireless sensor networks. 1-4 - Waqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi:
Design of a hybrid multicore platform for high performance reconfigurable computing. 1-8 - Pere Llimos Muntal, Kjartan Færch, Ivan H. H. Jørgensen, Erik Bruun:
System level design of a continuous-time ΔΣ modulator for portable ultrasound scanners. 1-4 - Prakash Harikumar, J. Jacob Wikner, Atila Alvandpour:
An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias. 1-4 - Pavlos Athanasiadis, Lampros Mountrichas, Stylianos Siskos:
An ultra wide-band adaptive frequency divider for mm-wave PLL applications. 1-4 - Messaoud Ahmed Ouameur, Daniel Massicotte, Wei-Ping Zhu:
Carrier frequency and sampling rate offsets effect on sub 6 GHz Massive MIMO. 1-4 - Ahmed Mahmoud, Pietro Andreani, Ping Lu:
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise. 1-4 - Vishnu Unnikrishnan, Srinivasa Rao Pathapati, Mark Vesterbacka:
A fully synthesized all-digital VCO-based analog-to-digital converter. 1-4 - Mikhael Daouri, Fernando A. Escobar, Xin Chang, Carlos Valderrama:
A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm. 1-4 - Jong-Seok Kim, Jae-Yoon Lee, Byong-Deok Choi:
High-efficiency peak-current-control non-inverting buck-boost converter using mode selection for single Ni-MH cell battery operation. 1-4 - Stefano Brenna, Luca Bettini, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita:
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters. 1-4 - Jochen Rust, Nils Heidmann, Steffen Paul:
Two-variable numeric function approximation using least-squares-based regression. 1-4 - S. Fahmy, Markus Dietl, Puneet Sareen, Maurits Ortmanns, Jens Anders:
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter. 1-4 - Mauro Mangia, Daniele Bortolotti, Andrea Bartolini, Fabio Pareschi, Luca Benini, Riccardo Rovatti, Gianluca Setti:
Long-Term ECG monitoring with zeroing Compressed Sensing approach. 1-4 - Clement Devigne, Jean-Baptiste Bréjon, Quentin L. Meunier, Franck Wajsbürt:
Executing secured virtual machines within a manycore architecture. 1-4 - Martin Krcma, Zdenek Kotásek, Jan Kastil:
Fault tolerant Field Programmable Neural Networks. 1-4 - Antonio Passamani, Davide Ponton, Gerhard Knoblinger, Andrea Bevilacqua:
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs. 1-4 - Hasene Gulperi Ozsema, Duygu Kostak, Tugba Demirci, Yusuf Leblebici:
Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology. 1-4 - Hasene Gulperi Ozsema, Tugba Demirci, Yusuf Leblebici:
3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation. 1-4 - Allan Munck, Jan Madsen:
Test-driven modeling of embedded systems. 1-4 - Sara Pashmineh, Dirk Killat:
Self-biasing high-voltage driver based on standard CMOS with an adapted level shifter for a wide range of supply voltages. 1-4 - Even Låte, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet:
Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI. 1-4 - Arun Ashok, Gabor Varga, Iyappan Subbiah, Moritz Schrey, Stefan Heinen:
Process tolerant highly linear mixer output stage with feedforward linearity improvement method for a high-IF converter. 1-4 - Sajjad Nouri, Waqar Hussain, Jari Nurmi:
Design and evaluation of correlation accelerator in IEEE-802.11a/g receiver using a template-based Coarse-Grained Reconfigurable Array. 1-6 - Mohsin Mumtaz Tarar, Muh-Dey Wei, Renato Negra:
A compact 0.3-10 GHz broadband stacked amplifier in 65nm standard CMOS. 1-4 - Takashi Yoshida, Naoyuki Aikawa:
The low delay low-pass FIR digital differentiators having flat passband and equiripple stopband. 1-4 - Vishnu Unnikrishnan, Mark Vesterbacka:
A NAND gate based standard cell VCO for use in synthesizable ADCs. 1-4 - Gabor Varga, Arun Ashok, Iyappan Subbiah, Moritz Schrey, Stefan Heinen:
Design of a highly linear, low noise, broad band up-converter for cognitive radio applications. 1-4 - Arcangelo Sisto, Luca Pilato, Riccardo Serventi, Luca Fanucci:
A design platform for flexible programmable DSP for automotive sensor conditioning. 1-4 - Raimund Ubar, Lembit Jurimagi, Jaan Raik:
Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. 1-4 - Oner Hanay, Erkan Bayram, Mohamed Saeed Elsayed, Renato Negra:
Systematic frequency planning for a high SFDR digital-IF RF-DAC-based transmitter. 1-4 - Luca Pezzarossa, Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø:
Interfacing hardware accelerators to a time-division multiplexing network-on-chip. 1-4 - Shadi M. Harb, William R. Eisenstadt:
A CMOS High Resolution Multi-Edge Delay Generator. 1-4 - Dominic A. Funke, Jürgen Oehm, Pierre Mayr, Thomas Maeke, John S. McCaskill, Abhishek Sharma, Lukas Straczek:
Ultra low-power, -area and -frequency CMOS thyristor based oscillator for autonomous microsystems. 1-4 - Mohamad El Ahmad, Mohamad Najem, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Adaptive Power monitoring for self-aware embedded systems. 1-4 - Ben Minnaert, Nobby Stevens:
Evaluation of the vertical magnetic field generated by a spiral planar coil. 1-3 - Farid Shamani, Vida Fakour Sevom, Jari Nurmi, Tapani Ahonen:
Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA. 1-8 - Peter Nilsson, Yuhang Sun, Rakesh Gangarajaiah, Erik Hertz:
Low power unrolled CORDIC architectures. 1-4 - Stanislaw J. Piestrak, Piotr Patronik:
Fault-tolerant implementation of direct FIR filters protected using residue codes. 1-4 - Gökçe Aydos, Görschwin Fey:
Empirical results on parity-based soft error detection with software-based retry. 1-4 - Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. 1-4 - Juan A. Torreño, Susana Patón, Laura Conesa-Peraleja, Luis Hernández, Dietmar Straeussnigg:
A noise coupled ΣΔ architecture using a Non Uniform Quantizer. 1-4 - Mounir Khelifi, Daniel Massicotte, Yvon Savaria:
Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems. 1-4 - Nisha Gupta, Ashudeb Dutta, Shiv Govind Singh:
A low/high band highly linearized reconfigurable down conversion mixer in 65nm CMOS process. 1-4 - Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad:
Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection. 1-4 - Tharald Solheim, Marius Grannaes:
A comparison of serial interfaces on energy critical systems. 1-4 - Siyu Tan, Yun Miao, Mattias Palm, Joachim Rodrigues, Pietro Andreani:
Digital background calibration in continuous-time delta-sigma analog to digital converters. 1-4 - Abdelrahman Elkafrawy, Jens Anders, Maurits Ortmanns:
A 10-bit reference free current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS. 1-4 - Joakim Nilsson, Johan Borg, Jonny Johansson:
Single chip wireless condition monitoring of power semiconductor modules. 1-4 - Muhammad Abdullah Khan, Ahmed Farouk Aref, Muh-Dey Wei, Renato Negra:
Highly linear and reliable low band class-O RF power amplifier in 130 nm CMOS technology for 4G LTE applications. 1-4 - Hannu Heusala, Jorma Skyttä:
How small and still effective a CMOS-SoC could ever be? 1-4 - Hourieh Attarzadeh, Snorre Aunet, Trond Ytterdal:
An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm. 1-4 - Fabio Pareschi, Tommaso Vincenzi, Mauro Mangia, Nicola Bertoni, Riccardo Rovatti, Gianluca Setti:
Application of spread-spectrum techniques to class-E DC/DC converters: some preliminary results. 1-4 - Ziyad Almohaimeed, Mihai Sima:
Secured-by-design FPGA: look-up tables and switch-boxes. 1-4 - Waqas Mughal, Bhaskar Choubey:
Fixed pattern noise correction for wide dynamic range CMOS image sensor with Reinhard tone mapping operator. 1-4 - Dmitry Osipov, Steffen Paul, Serge Strokov, Andreas K. Kreiter:
A new current stimulator architecture for visual cortex stimulation. 1-4 - Mohammad El-Sayed, Peter Koch, Yannick Le Moullec:
Architectural design space exploration of an FPGA-based compressed sampling engine: Application to wireless heart-rate monitoring. 1-5 - Hamid Yadegar Amin, Binboga Siddik Yarman:
Wide band edge-coupled impedance matching network with quarter wavelength measurement circuit. 1-4 - Navneeta Deo, Johan Wernehag, Joakim Thelberg:
Low power, highly stable and wideband LNA for GNSS applications in SiGe technology. 1-4 - Priit Ruberg, Keijo Lass, Peeter Ellervee:
Microcontroller energy consumption estimation based on software analysis for embedded systems. 1-4
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