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ORCIDCICC 2000: Orlando, FL, USA
- Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000. IEEE 2000, ISBN 0-7803-5809-0
- Ravindranath Naiknaware, Terri S. Fiez:
142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. 5-8 - Chris Binan Wang:
A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme. 9-12 - Mohamed Dessouky, Andreas Kaiser:
A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping. 13-16 - Eric Fogleman, Jared Welz, Ian Galton:
An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC. 17-20 - Yves Geerts, Michiel Steyaert
, Willy Sansen:
A 12-bit 12.5 MS/s multi-bit ΔΣ CMOS ADC. 21-24 - Kyung-Ho Cho, Henry Samueli:
A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversity. 27-30 - Dorin Emil Calbaza, Yvon Savaria:
Direct digital frequency synthesis of low-jitter clocks. 31-34 - Yoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz:
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. 35-38 - Hiroshi Suzuki, Zhongfeng Wang, Keshab K. Parhi:
A K=3, 2 Mbps low power turbo decoder for 3rd generation W-CDMA systems. 39-42 - Robert Pasko, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. 43-46 - Tak H. Ning:
CMOS in the new millennium. 49-56 - Akihiko Ebina, Tadao Kadowaki, Yoko Sato, Masayuki Yamaguchi:
Ultra low-power CMOS IC using partially-depleted SOI technology. 57-60 - T. Yoshida, H. Takato, T. Sakurai, K. Kokubun, K. Hiyama, A. Nomachi, Y. Takasu, M. Kishida, H. Ohtsuka, H. Naruse, Y. Morimasa, N. Yanagiya, T. Hashimoto, T. Noguchi, T. Miyamae, N. Iwabuchi, M. Tanaka, J. Kumagai, H. Ishiuchi:
A fabrication method for high performance embedded DRAM of 0.18 μm generation and beyond. 61-64 - Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. 65-68 - Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor. 71-74 - Yiorgos Makris, Alex Orailoglu, Praveen Vishakantaiah:
Modular test generation and concurrent transparency-based test translation using gate-level ATPG. 75-78 - Jayabrata Ghosh-Dastidar, Nur A. Touba:
Diagnosing resistive bridges using adaptive techniques. 79-82 - Mohamed M. Hafed, Gordon W. Roberts:
A stand-alone integrated excitation/extraction system for analog BIST applications. 83-86 - Albert Z. Wang:
A new design for complete on-chip ESD protection. 87-90 - Kenneth L. Shepard, K. Chou:
Cell characterization for noise stability. 91-94 - Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata:
Quantitative characterization of substrate noise for physical design guides in digital circuits. 95-98 - Grant Martin, Christopher K. Lennard:
Improving embedded software design and integration in SOCs. 101-108 - Reinaldo A. Bergamaschi, William R. Lee, Duane Richardson, Subhrajit Bhattacharya, Michael Muhlada, Ronaldo Wagner, Arthur Weiner, Foster White:
Coral-automating the design of systems-on-chip using cores. 109-112 - Charles Ouyang, Kyungsuk Ryu, Hans T. Heineken, Jitu Khare, Saghir A. Shaikh, Manuel d'Abreu:
Wire planning for performance and yield enhancement. 113-116 - Cristinel Ababei, Radu Marculescu, Venkat Sundarajan:
Probabilistic aspects of crosstalk problems in CMOS ICs. 117-120 - David E. Lackey:
Applying placement-based synthesis for on-time system-on-a-chip design. 121-124 - Patrick H. Buffet, Joseph Natonio, Robert A. Proctor, Yu H. Sun, Gulsun Yasar:
Methodology for I/O cell placement and checking in ASIC designs using area-array power grid. 125-128 - Jason P. Clifford, Steven J. E. Wilton:
Architecture of cluster-based FPGAs with memory. 131-134 - Andrew Kennings, Haneef Mohammed, Joseph P. Skudlarek, Bing Tian:
Cypress Delta39KTM. A memory-rich, high performance, scalable CPLD architecture. 135-138 - Ian Brynjolfson, Zeljko Zilic:
Dynamic clock management for low power applications in FPGAs. 139-142 - Sammy Cheung, Kar Keng Chua, Boon Jin Ang, Thow Pang Chong, Wei Lian Goay, Wei Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, Chiakang Sung, Kim Pin Tan, Yu Fong Tan, Choong Kit Wong:
A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM. 143-146 - Tarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham:
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. 147-150 - Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina:
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. 151-154 - Steve Knapp, Danesh Tavana:
Field configurable system-on-chip device architecture. 155-158 - Qiuting Huang:
CMOS RF design-the low power dimension. 161-166 - Alexandre Vouilloz, Catherine Dehollain, Michel J. Declercq:
A low-power CMOS super-regenerative receiver at 1 GHz. 167-170 - Alain-Serge Porret, Thierry Melly, Dominique Python, Christian C. Enz, Eric A. Vittoz:
A 1 V, 1 mW, 434 MHz FSK receiver fully integrated in a standard digital CMOS process. 171-174 - Jussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, Aarno Pärssinen, Kari Halonen:
A dual-band RF front-end for WCDMA and GSM applications. 175-178 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process. 179-182 - Osama Shana'a, Ivan Linscott, Len Tyler:
Frequency-scalable SiGe bipolar RFIC front-end design. 183-186 - Christian C. Enz:
MOS transistor modeling for RF integrated circuit design. 189-196 - Pin Su, Samuel K. H. Fung, Stephen Tang, Fariborz Assaderaghi, Chenming Hu:
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. 197-200 - Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu:
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. 201-204 - Timothy C. Kuo:
RFCMOS extension model accurate up to 40 GHz with distributed junction diode. 205-208 - Oscar da Costa Gouveia-Filho, Ana Isabele Araujo Cunha, Márcio Cherem Schneider, Carlos Galup-Montoro:
Advanced compact model for short-channel MOS transistors. 209-212 - Gi-Young Yang, Yeong-Gil Kim, Taek-Soo Kim, Jeong-Taek Kong:
S-TFT: an analytical model of polysilicon thin-film transistors for circuit simulation. 213-216 - Michele Borgatti, Alessandro Rocchi, Marco Bisio, Monica Besana, Loris Navoni, Pier Luigi Rolandi:
A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory. 219-222 - Luca Bolcioni, Roberto Guerrieri:
A low-power system-on-chip for the documentation of road accidents. 223-226 - Paul Freud:
Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies. 227-230 - Shinichi Kozu, Toshiya Aramaki, Chinatsu Ikeda, Yasuaki Kuroda, Satoru Kawanago, Mitsuji Okada, Hiroshi Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii:
A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home. 231-234 - Ilwan Lee, Dongkyu Kim, Seokjun Lee, Kipaek Kwon, Jongdae Kim, Incheol Kim, Yongho Kim, Sungjun Park, Cheongon Kim, Haemook Jung, Gyuhwan Chang:
A 300 K-gate 0.5 μm CMOS implementation of an 8-VSB receiver IC [for HDTV]. 235-238 - Patrick Rakers, Larry Connell, Tim Collins, Dan Russell:
Secure contactless smartcard ASIC with DPA protection. 239-242 - Jonathan C. Jensen, Lawrence E. Larson:
A broadband 10 GHz track-and-hold in Si/SiGe HBT technology. 245-248 - Koen Uyttenhove, Augusto Marques, Margot Steyaert:
A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction. 249-252 - Robert C. Taft, Maria Rosaria Tursi:
A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V. 253-256 - David G. Nairn:
A 10-bit, 3 V, 100 MS/s pipelined ADC. 257-260 - Paul F. Ferguson Jr., Xavier Haurie, Gabor C. Temes:
A highly linear low-power 10 bit DAC for GSM. 261-264 - Anne Van den Bosch, Melissa Borremans, Michiel Steyaert, Willy Sansen:
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. 265-268 - Mitsuya Kinoshita, Tadaaki Yamauchi, Teruhiko Amano, Katsumi Dosaka, Kenshin Arimoto:
Design methodology of the embedded DRAM with the virtual socket architecture. 271-274 - Naoyuki Kawabe, Kimiyoshi Usami:
Low-power technique for on-chip memory using biased partitioning and access concentration. 275-278 - Yuji Yokoyama, Nybutaka Itoh, Masap Katayama, Kazumasa Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Tom Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%. 279-282 - Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi:
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. 283-286 - Richard J. McPartland, D. J. Loeper, Frank P. Higgins, Raj Singh, G. MacDonald, Goh Komoriya, S. Aymeloglu, M. V. DePaolis, C. W. Leung:
SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy. 287-289 - Philip W. Diodato, J. H. O'Neill, Y.-H. Wong, G. B. Alers, H. M. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C.-T. Liu, W. Y.-C. Lai:
Embedded DRAM: an element and circuit evaluation. 291-294 - Doug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer:
Design validation of .18 μm 1 GHz cache and register arrays. 295-298 - Patrick P. Siniscalchi, Jeanne K. Pitz, Richard K. Hester, Stewart DeSoto, Minsheng Wang, Sucheedran Sridharan, Robert L. Halbach, Donald Richardson, William Bright, Maher M. Sarraj, James R. Hellums, Christopher L. Betty, Glenn H. Westphal:
A CMOS ADSL codec for central office applications. 303-306 - John Kenney, Faramarz Sabouri, Vincent W. Leung, John Guido, Ed Zimany, Anthony Agrillo, Joseph Trackim, John Khoury, Reza Shariatdous:
A 4 channel analog front end for central office ADSL modems. 307-310 - Fang Lu, Jonathan S. Min, Sam Liu, Kelly B. Cameron, Christopher Jones, Owen Lee, Johnson Li, Aaron Buchwald, Stephen Jantzi, Christopher Ward, Kenneth Choi, Jim Searle, Henry Samueli:
A single-chip universal burst receiver for cable modem/digital cable-TV applications. 311-314 - Jesus Guinea, Luciano Tomasini, Santo Maggio, Massimiliano Rutar:
A single chip 155 Mbps/140 Mbps SDH/PDH transceiver. 315-318 - Giacomino Bollati, Angelo Dati, Giorgio Betti, Ivan Bietti, Francesco Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Daniele Ottini, Valerio Pisati, Francesco Rezzi, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello:
A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi. 319-322 - Roberto Cappelletti, Andrea Baschirotto:
A versatile low-power power line FSK transceiver. 323-326 - Nobuyasu Kanekawa, Yasuyuki Kojima, Seigo Yukutake, Minehiro Nemoto, Takayuki Iwasaki, Kazuhisa Takami, Yusuke Takeuchi, Atsuko Yano, Yasuo Shima:
An analog front-end LSI with on-chip isolator for V.90 56 kbps modems. 327-330 - Jan Sevenhans:
Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOS. 333-340 - Feng-Jung Huang, Kenneth K. O:
A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-μm CMOS process. 341-344 - Alireza Zolfaghari, Andrew Chan, Behzad Razavi:
Stacked inductors and 1-to-2 transformers in CMOS technology. 345-348 - Lai-Pong (Lawrence) Wong, Chris Snyder, Tajinder Manku, Stephen Kovacic:
An integrated capacitively coupled transformer and its application for RF IC's. 349-352 - Min Xu, David K. Su, Derek K. Shaeffer, Thomas H. Lee, Bruce A. Wooley:
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver. 353-356 - Wolfgang Winkler, Frank Herzel:
Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings. 357-360 - Eyad Abou-Allam, Tajinder Manku, Michele Ting, Michael S. Obrecht:
Impact of technology scaling on CMOS RF devices and circuits. 361-364 - David J. Foley, Michael P. Flynn:
CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator. 371-374 - Tsung-Hsien Lin, William J. Kaiser:
A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop. 375-378 - Seema Butala Anand, Behzad Razavi:
A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology. 379-382 - Johan van der Tang, Dieter Kasperkovitz, Arend Bretveld:
A 65 mW, 0.4-2.3 GHz bandpass filter for satellite receivers. 383-386 - Jiunn-Yih Lee, Chien-Cheng Tu, Wei-Hong Chen:
A 3 V linear input range tunable CMOS transconductor and its application to a 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter for ADSL. 387-390 - Pietro Andreani, Sven Mattisson:
A CMOS gm-C IF filter for Bluetooth. 391-394 - Tristan Reimann, François Krummenacher, B. Willing, P. Muralt, Michel J. Declercq:
A CMOS readout circuit for pico-ampere thin film pyroelectric array detectors. 395-398 - Mohamed W. Allam, Mohab H. Anis, Mohamed I. Elmasry:
Effect of technology scaling on digital CMOS logic styles. 401-408 - Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai:
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. 409-412 - Liqiong Wei, Kaushik Roy, Cheng-Kok Koh:
Power minimization by simultaneous dual-Vth assignment and gate-sizing. 413-416 - Anne-Johan Annema, Govert Geelen, Peter C. de Jong:
5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. 417-420 - Mohamed W. Allam, Mohamed I. Elmasry:
Dynamic current mode logic (DyCML), a new low-power high-performance logic family. 421-424 - Ganesh Balamurugan, Naresh R. Shanbhag:
A noise-tolerant dynamic circuit design technique. 425-428 - Joel R. Phillips, Kenneth S. Kundert:
Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise. 431-438 - Donhee Ham, Ali Hajimiri:
Complete noise analysis for CMOS switching mixers via stochastic differential equations. 439-442 - Payam Heydari, Massoud Pedram:
Analysis of jitter due to power-supply noise in phase-locked loops. 443-446 - Lin Wu, Huawen Jin, William C. Black Jr.:
Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems. 447-450 - Joel R. Phillips:
Automated extraction of nonlinear circuit macromodels. 451-454 - Mark Chapman, Alper Demir, Peter Feldmann:
Finite-length signal quantization using discrete optimization. 455-458 - Tai-Cheng Lee, Behzad Razavi:
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. 461-464 - Erich F. Haratsch, Kamran Azadet:
A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet. 465-468 - Christopher Deng, Charles Chien:
A PN-acquisition ASIC for wireless CDMA systems. 469-472 - T. Kamemaru, Hideo Ohira, H. Suzuki, Ken'ichi Asano, Masahiko Yoshimoto, Tokumichi Murakami:
Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video. 473-476 - Stefan R. Meier, Matthias Schoebinger:
Efficient and reusable time-sharing architectures for equalizer structures. 477-480 - Gregg N. Hoyer, Carl Sechen:
A locally-clocked dynamic logic serial/parallel multiplier. 481-484 - Xiaoning Qi, Gaofeng Wang, Zhiping Yu, Robert W. Dutton, Tak Young, Norman Chang:
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation. 487-490 - Eileen You, Swee Yav Choe, Chin Kim, Lakshminarasimh Varadadesikan, Kathirgamar Aingaran, John MacDonald:
Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience. 491-494 - Yasuhiko Sasaki, Kazuo Yano:
Multi-aggressor relative window method for timing analysis including crosstalk delay degradation. 495-498 - Pavan K. Gunupudi, Michel S. Nakhla:
Multi-dimensional model reduction of VLSI interconnects. 499-502 - Yonghee Im, Kaushik Roy:
A novel high-performance predictable circuit architecture for the deep sub-micron era. 503-506 - Paul P. Sotiriadis, Anantha P. Chandrakasan:
Low power bus coding techniques considering inter-wire capacitances. 507-510 - Kurt Antreich, Josef Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, Robert Schwencker, Stephan Zizala:
WiCkeD: analog circuit synthesis incorporating mismatch. 511-514 - Edoardo Charbon, Ilhami Torunoglu:
On intellectual property protection. 517-523 - James Nash, Philip Smith:
An analysis of the design processes required for the technology conversion of SoC intellectual property. 525-527 - Adhikary Ranjit, Prakasam Ramkumar, Vargese Noel:
Firm IP development: methodology and deliverables. 529-532 - Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A new paradigm for very flexible SONET/SDH IP-modules. 533-536 - G. Bollano, S. Claretto, Enrica Filippi, Alessandro Torielli, Maura Turolla:
Merging hardware and software: intellectual property cores for Internet applications. 537-540 - Roberto Yusi Omaki, Yu Dong, M. Horgan Miki, Makoto Furuie, Shohei Yamada, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa:
VLSI implementation of a realtime wavelet video coder. 543-546 - Joerg Ritter, Paul Molitor:
A partitioned wavelet-based approach for image compression using FPGA's. 547-550 - Sang-Joon Nam, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, Chong-Min Kyung:
FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit. 551-554 - Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda:
Novel VLIW code compaction method for a 3D geometry processor. 555-558 - Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park:
Multi-thread VLIW processor architecture for HDTV decoding. 559-562 - Sekyoung Hong, Byungcheol Park, Yoonseok Song, Hangyo See, Jonghyun Kim, Hyungjong Lee, Dalsoo Kim, Minkyu Song:
A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal data converters. 563-566 - Jacob J. Rael, Asad A. Abidi:
Physical processes of phase noise in differential LC oscillators. 569-572 - Frank Herzel, Heide Erzgraeber, Nikolay Ilkov:
A new approach to fully integrated CMOS LC-oscillators with a very large tuning range. 573-576 - Francesco Svelto, Stefano Deantoni, Rinaldo Castello:
A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO. 577-580 - Hui Wu, Ali Hajimiri:
A 10 GHz CMOS distributed voltage controlled oscillator. 581-584 - Bram De Muer, Nobuyulu Itoh, Marc Borremans, Michiel Steyaert:
A 1.8 GHz highly-tunable low-phase-noise CMOS VCO. 585-588 - Amr N. Hafez, Mohamed I. Elmasry:
A fully-integrated low phase-noise nested-loop PLL for frequency synthesis. 589-592 - Mihai A. Margarit, M. Jamal Deen:
A low power high spectral purity frequency translational loop for wireless applications. 593-596
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