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ORCIDFPGA 2024: Monterey, CA, USA
- Zhiru Zhang, Andrew Putnam:
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024. ACM 2024
Keynote I
- Timothy Sherwood
:
Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA. 1
Session: FPGA Circuit Design
- Alireza Khataei, Kia Bazargan:
CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond. 2-11 - Greg Stitt, Wesley Piard, Christopher Crary:
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet. 12-21 - Shaoxian Xu, Sitong Lu, Zhiyuan Shao, Xiaofei Liao, Hai Jin:
MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs. 22-32 - Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao:
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine. 33-39
Poster Session I
- Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne:
DynaRapid: From C to FPGA in a Few Seconds. 40 - Hui Wei, Jingyong Ye, Yutong Chen, Heng Wu:
Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory. 40 - Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao:
Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design. 41 - Zelin Wang, Guiyuan Zhu, Yunhai Liu, Yisong Chang, Ke Zhang, Mingyu Chen:
XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAs. 41 - Muhammed Kawser Ahmed, Christophe Bobda:
ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA. 42 - Xiaoyu Niu, Yanjun Zhang, Yifan Zhang, Hongzheng Tian, Bo Yu, Shaoshan Liu, Sitao Huang:
Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware HW/SW Co-Optimizations. 42 - Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel:
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels. 43 - Thore Gerlach, Stefan Knipp, David Biesner, Stelios Emmanouilidis, Klaus Hauber, Nico Piatkowski:
FPGA-Placement via Quantum Annealing. 43
Session: Applications I
- Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. 44-54 - Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou:
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. 55-66 - Zifan He, Linghao Song, Robert F. Lucas, Jason Cong:
LevelST: Stream-based Accelerator for Sparse Triangular Solver. 67-77 - Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus:
A 475 MHz Manycore FPGA Accelerator for RTL Simulation. 78-84
Session: CAD for FPGAs
- Mahdi Abbaszadeh, Dana L. How:
From Topology to Realization in FPGA/VPR Routing. 85-96 - Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez, Zhiru Zhang:
Formal Verification of Source-to-Source Transformations for HLS. 97-107 - Dongjoon Park, André DeHon:
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. 108-118
Session: Datacenter and Cloud
- Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Saddam Gafsi, Judson Douglas Ryckman, Qing Yang, Tao Wei:
An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits. 119-129 - Will Lin, Yizhou Shan, Ryan Kosta, Arvind Krishnamurthy, Yiying Zhang:
SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC. 130-141
Keynote II
- Prabhat K. Gupta:
My Fifteen Year Journey of Deploying FPGA Accelerated Solutions. 142
Session: Applications II
- Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang:
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. 143-153 - Manoj B. Rajashekar, Xingyu Tian, Zhenman Fang:
HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs. 154-164 - Martin Langhammer, George A. Constantinides:
A Statically and Dynamically Scalable Soft GPGPU. 165-175 - Mark Klaisoongnoen, Nick Brown, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus:
Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis. 176-182
Poster Session II
- Yan Chen, Kiyofumi Tanaka:
A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs. 183 - Geng Yang, Jie Lei, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie, Yunsong Li:
E4SA: An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional Neural Networks. 183 - Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. 184 - Yiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser:
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. 184 - Kai Qian, Zheng Liu, Yinqiu Liu, Haodong Lu, Zexu Zhang, Ruiqiu Chen, Kun Wang:
AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator. 185 - Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang:
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. 185 - Shengjun Xu, Wenlu Peng, Wenjin Huang, Qi Liu, Yihua Huang:
HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model. 186 - Ruifan Xu, Jin Luo, Yun Liang:
Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs. 186 - Qizhe Wu, Letian Zhao, Yuchen Gui, Huawen Liang, Xiaotian Wang, Xi Jin:
Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. 187 - Zhigang Wei, Aman Arora, Emily Shriver, Lizy Kurian John:
Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning. 187
Session: High-Level Abstractions and Tools for FPGAs
- Jiahui Xu, Lana Josipovic:
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. 188-198 - Xiaochen Hao, Hongbo Rong, Mingzhe Zhang, Ce Sun, Hong H. Jiang, Yun Liang:
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations. 199-210 - Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang:
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. 211-222
Session: Machine Learning
- Shulin Zeng, Jun Liu, Guohao Dai, Xinhao Yang, Tianyu Fu, Hongyi Wang, Wenheng Ma, Hanbo Sun, Shiyao Li, Zixiao Huang, Yadong Dai, Jintao Li, Zehao Wang, Ruoyu Zhang, Kairui Wen, Xuefei Ning, Yu Wang:
FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs. 223-234 - Daniel Gerlinghoff, Benjamin Chen Ming Choong, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo:
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic. 235-245 - Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So:
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. 246-257
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