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ORCIDMicroprocessing and Microprogramming, Volume 30
Volume 30, Numbers 1-5, August 1990
- Mario Stevens:
Chairman's introduction. vii - D. Q. M. Fay:
Opening address: Hardware and software in system engineering. 1-2 - G. A. Schwippert:
Keynote address K1: Small and medium sized industries (SMI). 3 - J. A. Dinklo:
Keynote address K2: The strategic importance of microcomputing for the business environment. 5 - M. Malek:
Keynote address K3: Responsive systems (the challenge for the nineties). 9-16 - Robert V. Adams:
Keynote address K4: The state of global printing in the '90s. 17 - Arthus I. Karshmer, James N. Thomas, P. K. Annaiyappa, D. Eshner, S. Kankanahalli, G. Kurup:
Architectural support for operating systems: A popular RISC vs. a popular CISC. 21-32 - Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble:
A risc central processing unit for a massivelly parallel architecture. 33-39 - Djamshid Tavangarian, M. Beck:
ASTRA: An associative RISC-Architecture. 41-48 - Dimitris E. Metafas, Costas E. Goutis:
A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms. 51-57 - Thomas Kropf, Jürgen Frößl, W. Beller, T. Giesler:
A hardware implementation of a modified DES-algorithm. 59-65 - Walter Bragagnini, Paolo Guazzoni, Maurizio Pitalieri, Luisa Zetta:
Computational logic unit for a microprogrammed data acquisition system: an evaluation prototype. 67-74 - J. Tiberghien:
Parallel Applications. 75 - Wouter Joosen, Yolande Berbers, Pierre Verbaeten:
Dynamic load balancing in transputer applications with geometric parallelism. 77-84 - Valmir C. Barbosa
, Maria Cristina Silva Boeres:
An Occam-based evaluation of a parallel version of simulated annealing. 85-92 - Hong Shen:
Occam implementation of path-disjoint routing on the Hathi-2 transputer system. 93-100 - Christian Ewering, Gunter Gerhardt:
PASS: High level synthesis. 103-108 - Björn Lisper:
The interactive space-time scheduler. 109-116 - A. J. W. M. ten Berg:
Stepwise decomposition in controlpath synthesis. 117-124 - William A. Geideman, Roger A. Niederland, David L. Harrington:
A 32-bit RISC CPU implemented in GaAs. 127-133 - J. E. H. M. Bormans, Willem J. Withagen, F. P. M. Budzelaar, M. P. J. Stevens:
Designing high performance instruction caches in VLSI. 135-142 - Olatz Arregi, Clemente Rodríguez, Amaia Ibarra:
Evaluation of the optimal strategy for managing the register file. 143-150 - D. Wilson:
Session B: Signal - II. 151 - M. Maresca, G. Carravieri, G. Cornara, Arrigo L. Frisiani:
Partitioned algorithms for gaussian elimination on reconfigurable processor arrays. 153-158 - H. Bekker, M. Renardus:
Design of a transputer network for searching neighbours in M.D. simulations. 159-165 - Eric Lindemann, Miller S. Puckette, Eric Viara, Michel Starkier:
The IRCAM signal processing workstation - An environment for research in real-time musical signal processing and performance. 167-174 - R. J. Huis in 't Veld:
The role of languages in the design-trajectory. 177-183 - Gerd Kock:
Towards the verification of optimizing transformations for imperative programs. 185-192 - Andrea Domenici:
Petri nets in logic. 193-198 - J. Vlahavas, Andreas S. Pombortsis, D. Stamatis:
Towards a parallel inference machine: the APIM project. 201-206 - Cosimo Antonio Prete:
A new solution of coherence protocol for tightly coupled multiprocessor systems. 207-214 - Erik F. Dirkx, Frank Verboven, Jacques Tiberghien:
Distributed simulation of computer networks. 215-220 - Jean-Luc Dubois, Przemyslaw Bakowski, Adam Pawlak:
Synthesis of programmable control structures for a simulation speed-up. 223-229 - S. Balakrishnan, S. K. Nandy:
Quasi dynamic approach to layout compaction. 231-236 - N. A. Kyrloglou, Odysseas G. Koufopavlou, Costas E. Goutis:
A generator for a number format conversion IC. 237-240 - Ad. C. Verschueren:
An object oriented design and simulation system for VLSI. 241-246 - Bernard Faure, Guy Mazaré:
A cellular architecture dedicated to neural net emulation. 249-255 - J. Hoekstra:
System architecture of a modular neural network using 400 simple processors. 257-262 - Lambert Spaanenburg, A. J. Beltman, J. A. G. Nijhuis, A. Reitsma:
A case study in the migration of software to hardware using basics. 263-270 - Antti Auer, Mikko Levanto, Ari Okkonen, Jyrki Okkonen:
Solution in software crisis. 273-280 - Ian R. McChesney, Derrick Glass, John G. Hughes:
Case tool support for requirements capture and analysis. 281-288 - Timo Jokela, Kai Lindberg:
Statecharts based requirements analysis: Deriving user oriented models. 289-296 - Jari Arkko, Vesa Hirvisalo, Juha Kuusela, Esko Nuutila:
Supporting testing of specifications and implementations. 297-302 - Lech Józwiak:
Simultaneous decompositions of sequential machines. 305-312 - Mikael R. K. Patel:
Random logic circuit implementation of extended Timed Petri Nets. 313-319 - M. P. J. Stevens, F. P. M. Budzelaar:
System level VLSI design. 321-329 - K. Parthenis, C. Metaxaki-Kossionidis, B. Dimitriadis:
EIKON: A software library for image processing applications. 333-339 - C. E. Prakash, S. K. Nandy:
VOXEL based modeling and rendering irregular solids. 341-346 - P. Pitot, B. Moisan, Yves Duthen, René Caubet:
A transputer based implementation of the VOXAR project. 347-353 - Gerardo Canfora, Aniello Cimitile, Ugo de Carlini:
Reverse engineering and data flow diagrams in ADA environment. 357-364 - Nelson Q. Vasconcelos, Edil S. T. Fernandes, Fernando M. B. Barbosa:
An environment for parallel programming in PASCAL. 365-370 - Andrea Clematis, Gabriella Dodero, Vittoria Gianuzzi:
Recovery meta program in Unix based environment. 371-378 - T. S. Hughes, Jim E. Cooling:
Animation prototyping of formal specifications of real-time systems. 381-388 - J. S. Sagoo, D. J. Holding:
The specification and design of hard real-time systems using timed and temporal petri nets. 389-396 - Charles Andre, Luc Fancelli:
A mixed implementation of a real-time system. 397-402 - Giacomo Buonanno, A. Burri, Franco Fummi, Donatella Sciuto:
An approach to a design for testability personal consultant. 405-412 - Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Assessing the diagnostic power of test pattern sets. 413-419 - Paolo Camurati, Tiziana Margaria, Paolo Prinetto:
The OTTER environment for resolution-based proof of hardware correctness. 421-428 - P. B. Franken, Ad J. van de Goor:
Special architecture for high-performance scan conversion. 431-438 - Luís Vieira de de Sá, Vítor Silva, Fernando Perdigão, Sérgio Faria, Pedro Assunção:
A parallel architecture for real-time video coding. 439-445 - Ferenc Vajda:
Application and implementation of window-based image processing algorithms. 447-454 - A. T. Balou, Apostolos Nikolaos Refenes:
Designing a parallel object-oriented compiler target language (TOOL). 457-465 - Michel Auguin, Fernand Boéri, C. Carrière, G. Menez:
From program to hardware: A parallel architecture compiler. 467-474 - E. Accomazzo, M. Ancona, R. Bobbio, C. Cagnassi, L. Paolin:
Integrating intermediate code optimization with retargetable code generation. 475-481 - Wolfgang A. Halang:
Session E4: Real Time Systems II. 483 - Monika Kapus-Kolar:
Constructing real-time multi-channel protocols. 485-490 - Stephen C. Winter, Derek R. Wilson, D. F. Neale:
Real-time functional programming systems. 491-497 - David Scholefield, Hussein Zedan:
TAM: Temporal agent model for real-time distributed systems. 499-506 - Olaf Stern, Heinrich Theodor Vierhaus:
CMOS layout generation for improved testability. 509-512 - Henrique Madeira, Gonçalo Quadros, João Gabriel Silva:
Experimental evaluation of a set of simple error detection mechanisms. 513-520 - Tassos Markas, Nick Kanopoulos:
A bus-monitor unit for fault-tolerant system configurations. 521-527 - Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda:
A transputer-based gate-level fault simulator. 529-534 - Peter J. de Graaff:
On the formal specification and verification of digital circuits. 537-544 - Stefano Antoniazzi, Mirella Mastretti:
An interactive environment for hardware/software system design at the specification level. 545-553 - Edwige E. Pissaloux:
A rational methodology for design of new computer structures. 555-560 - Uwe Wienkop:
Behavioral circuit description on system level. 561-566 - Edwige E. Pissaloux, Samir Bouaziz, Alain Mérigot, Francis Devos:
Co-programming: A tool for the development of software for massively parallel computers. 569-576 - Peter Buhler:
The COIN model for concurrent computation and its implementation. 577-584 - Andrew M. Tyrrell, Geoffrey F. Carpenter:
Data flow methods in the design of parallel computing systems. 585-591 - T. J. G. Benson, Peter Milligan, N. S. Scott:
Program development within the mathematician's devil. 593-597 - Ranjani Narayan, V. Rajaraman:
Performance analysis of a multiprocessor machine based on data flow principles. 601-608 - Emilio L. Zapata, José Carlos Cabaleiro, Ramon Doallo, Francisco Argüello:
Systolic architecture for the calculation of the correlation coefficients. 609-616 - Jie Xu, Shize Huang:
A new comparison-based scheme for multiprocessor fault tolerance. 617-623 - Arthur I. Karshmer, James N. Thomas, James M. Phelan:
TVNet II: A cable TV based metropolitan area network using the KEDS protocol. 627-635 - Jong K. Ahn, Song C. Moon:
Join optimization in distributed databases on broadcast network. 637-644 - Apostolos Nikolaos Refenes:
Message passing via singly-buffered channels: an efficient & flexible communications control mechanism. 645-653 - Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux:
Vector addressing processor for direct and indirect accesses. 657-664 - J. P. C. F. H. Smeets, Willem J. Withagen, M. P. J. Stevens:
Pipelining a memory based CISC processor. 665-672 - Geoffrey M. Macharia, James Austin:
A performance analysis of toroidal mesh networks. 675-682 - Ryszard F. Gajda, Miroslaw Thor, Marek S. Tudruj:
Enhancing a control graph based HDL for performance evaluation of simulated architectures. 683-691 - Geoffrey F. Carpenter:
The synthesis of deadlock-free interprocess communications. 695-701 - P. Pramanik, Pradip K. Das, A. K. Bandyopadhyay, D. Q. M. Fay:
A deadlock-free communication kernel for loop connected message passing computer architecture. 703-712
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