default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDUlf Schlichtmann
Person information
- affiliation: Technical University of Munich, Institute for Electronic Design Automation, Germany
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j84]Vasilii Kulagin, Sergio Vinagrero Gutierrez, Tobias Kilian, Daniel Tille, Ulf Schlichtmann, Giorgio Di Natale, Elena-Ioana Vatajelu:
On the Relation Between Reliability and Entropy in Physical Unclonable Functions. IEEE Des. Test 41(6): 46-53 (2024)- [j83]Weiqing Ji
, Xingzhuo Guo, Shouan Pan, Fei Long, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao:
GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers. IEEE Trans. Biomed. Circuits Syst. 18(3): 622-635 (2024) - [j82]Xing Huang, Huayang Cai, Wenzhong Guo, Genggeng Liu, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann:
Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 277-290 (2024) - [j81]Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann:
CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 573-585 (2024) - [j80]Yu-Guang Chen, Chieh-Shih Wang, Ing-Chao Lin, Zheng-Wei Chen, Ulf Schlichtmann:
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1580-1593 (2024) - [j79]Bowen Zhang, Huaxi Gu, Grace Li Zhang, Yintang Yang, Ziteng Ma, Ulf Schlichtmann:
A 3D Hybrid Optical-Electrical NoC Using Novel Mapping Strategy Based DCNN Dataflow Acceleration. IEEE Trans. Parallel Distributed Syst. 35(7): 1139-1154 (2024) - [c240]Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li:
Logic Design of Neural Networks for High-Throughput and Low-Power Applications. ASPDAC 2024: 902-907 - [c239]Philipp van Kempen, Jefferson Parker Jones, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension. CF (Companion) 2024 - [c238]Alexander Hoffman, Ala Fnayou, Fedor Smirnov, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. COINS 2024: 1-8 - [c237]Zhidan Zheng, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, Ulf Schlichtmann:
Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. DAC 2024: 74:1-74:6 - [c236]Siyuan Liang, Yushen Zhang, Rana Altay, Hudson Gasvoda, Mengchu Li, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design. DAC 2024: 197:1-197:6 - [c235]Mengchu Li, Hanchen Gu, Yushen Zhang, Siyuan Liang, Hudson Gasvoda, Rana Altay, Ismail Emre Araci, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann:
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI). DAC 2024: 340:1-340:2 - [c234]Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks. DATE 2024: 1-6 - [c233]Qingrong Huang, Hamza Errahmouni Barkam, Zeyu Yang, Jianyi Yang, Thomas Kämpfe, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Mohsen Imani, Cheng Zhuo, Xunzhao Yin:
A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation. DATE 2024: 1-6 - [c232]Xing Huang, Jiaxuan Wang, Zhiwen Yu, Bin Guo, Tsung-Yi Ho, Ulf Schlichtmann, Krishnendu Chakrabarty:
PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems. DATE 2024: 1-6 - [c231]Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann:
ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. DATE 2024: 1-2 - [c230]Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation. DATE 2024: 1-6 - [c229]Philipp van Kempen, Mathis Salmen, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. DSD 2024: 335-342 - [c228]Philipp Fengler, Sani R. Nassif, Ulf Schlichtmann:
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes. ISQED 2024: 1-8 - [c227]Alexander Hoffman, Ulf Schlichtmann, Daniel Mueller-Gritschneder:
MuNAS: TinyML Network Architecture Search Using Goal Attainment and Reinforcement Learning. MECO 2024: 1-8 - [c226]Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models. MLCAD 2024: 15:1-15:9 - [c225]Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. MLCAD 2024: 18:1-18:10 - [i44]Bo Liu, Grace Li Zhang, Xunzhao Yin, Ulf Schlichtmann, Bing Li:
EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration. CoRR abs/2402.18595 (2024) - [i43]Christopher Wolters, Xiaoxuan Yang, Ulf Schlichtmann, Toyotaro Suzumura:
Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference. CoRR abs/2406.08413 (2024) - [i42]Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
LiveMind: Low-latency Large Language Models with Simultaneous Inference. CoRR abs/2406.14319 (2024) - [i41]Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li:
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. CoRR abs/2407.03738 (2024) - [i40]Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models. CoRR abs/2407.03889 (2024) - [i39]Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. CoRR abs/2407.03891 (2024) - [i38]Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann:
Classification-Based Automatic HDL Code Generation Using LLMs. CoRR abs/2407.18326 (2024) - [i37]Sijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
An Efficient General-Purpose Optical Accelerator for Neural Networks. CoRR abs/2409.12966 (2024) - 2023
- [j78]Ulf Schlichtmann, Bing Li, Bei Yu, Raviv Gal:
Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA. IEEE Des. Test 40(1): 5-7 (2023) - [j77]Tinghuan Chen, Grace Li Zhang, Bei Yu, Bing Li, Ulf Schlichtmann:
Machine Learning in Advanced IC Design: A Methodological Survey. IEEE Des. Test 40(1): 17-33 (2023) - [j76]Xing Huang, Youlin Pan, Zhen Chen, Wenzhong Guo, Lu Wang, Qingshan Li, Robert Wille, Tsung-Yi Ho, Ulf Schlichtmann:
Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass Paradigm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 327-331 (2023) - [j75]Xunzhao Yin, Yu Qian, Mohsen Imani, Kai Ni, Chao Li, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo:
Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1099-1112 (2023) - [j74]Mengchu Li, Yushen Zhang, Ju Young Lee, Hudson Gasvoda, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann:
Integrated Test Module Design for Microfluidic Large-Scale Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1939-1950 (2023) - [j73]Di Gao, Zeyu Yang, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo:
BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2136-2148 (2023) - [j72]Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero:
A Multilabel Active Learning Framework for Microcontroller Performance Screening. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3436-3449 (2023) - [j71]Felix Last, Ulf Schlichtmann:
Training PPA Models for Embedded Memories on a Low-data Diet. ACM Trans. Design Autom. Electr. Syst. 28(2): 26:1-26:24 (2023) - [j70]Tobias Kilian, Daniel Tille, Martin Huch, Markus Hanel, Ulf Schlichtmann:
Performance Screening Using Functional Path Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 711-724 (2023) - [c224]Johannes Geier, Lukas Auer, Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann:
CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V. ASP-DAC 2023: 676-682 - [c223]Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Enabling Inter-Product Transfer Learning on MCU Performance Screening. ATS 2023: 1-6 - [c222]Samira Ahmadifarsani, Rafael Stahl, Philipp van Kempen, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA. CODAI 2023: 6-10 - [c221]Philipp van Kempen, Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
MLonMCU: TinyML Benchmarking with Fast Retargeting. CODAI 2023: 32-36 - [c220]Richard Petri, Grace Li Zhang, Yiran Chen, Ulf Schlichtmann, Bing Li:
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration. DAC 2023: 1-6 - [c219]Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann:
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation. DATE 2023: 1-6 - [c218]Bernhard Lippmann, Joel Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, Michaela Brunner, Tim Music, Michael Pehl, Tauseef Siddiqui, Ralf Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, Maurits Ortmanns, Robert Hesselbarth, Matthias Hiller:
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations. DATE 2023: 1-6 - [c217]Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann:
Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems. DATE 2023: 1-2 - [c216]Uzair Sharif, Daniel Mueller-Gritschneder, Rafael Stahl, Ulf Schlichtmann:
Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications. DATE 2023: 1-6 - [c215]Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li, Ulf Schlichtmann:
Class-based Quantization for Neural Networks. DATE 2023: 1-6 - [c214]Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann:
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. DATE 2023: 1-6 - [c213]Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers. DATE 2023: 1-6 - [c212]Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann:
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators. DFT 2023: 1-6 - [c211]Ahsan Saeed, Denis Hoornaert, Dakshina Dasari, Dirk Ziegenbein, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Andreas Gerstlauer, Renato Mancuso:
Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs. ECRTS 2023: 4:1-4:23 - [c210]Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Semi-Supervised Deep Learning for Microcontroller Performance Screening. ETS 2023: 1-6 - [c209]Weiqing Ji, Xingcheng Yao, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin:
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. ACM Great Lakes Symposium on VLSI 2023: 255-260 - [c208]Weiqing Ji, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin:
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. ACM Great Lakes Symposium on VLSI 2023: 483-488 - [c207]Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann:
MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems. PARMA-DITAM 2023: 5:1-5:12 - [c206]Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing. ICCAD 2023: 1-9 - [c205]Zhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin:
NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. ICCAD 2023: 1-9 - [c204]Siyuan Liang, Meng Lian, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based Implementation. ICCAD 2023: 1-9 - [c203]Meng Lian, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines. ISPD 2023: 53-61 - [c202]Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Feature Selection for Cost Reduction In MCU Performance Screening. LATS 2023: 1-6 - [c201]Christopher Wolters, Brady Taylor, Edward Hanson, Xiaoxuan Yang, Ulf Schlichtmann, Yiran Chen:
Biologically Plausible Learning on Neuromorphic Hardware Architectures. MWSCAS 2023: 733-737 - [c200]Amro Eldebiky, Georg Böcherer, Maximilian Schädler, Stefano Calabrò, Bing Li, Ulf Schlichtmann:
Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing. OFC 2023: 1-3 - [c199]Bo Liu, Christian Blümm, Stefano Calabrò, Bing Li, Ulf Schlichtmann:
Area-Efficient Neural Network CD Equalizer for 4×200Gb/s PAM4 CWDM4 Systems. OFC 2023: 1-3 - [i36]Richard Petri, Grace Li Zhang, Yiran Chen, Ulf Schlichtmann, Bing Li:
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration. CoRR abs/2303.13997 (2023) - [i35]Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference. CoRR abs/2303.17878 (2023) - [i34]Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks. CoRR abs/2306.07294 (2023) - [i33]Philipp van Kempen, Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
MLonMCU: TinyML Benchmarking with Fast Retargeting. CoRR abs/2306.08951 (2023) - [i32]Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li:
Logic Design of Neural Networks for High-Throughput and Low-Power Applications. CoRR abs/2309.10510 (2023) - [i31]Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation. CoRR abs/2312.01403 (2023) - 2022
- [j69]Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Krishnendu Chakrabarty, Ulf Schlichtmann:
Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems. ACM Comput. Surv. 54(5): 97:1-97:29 (2022) - [j68]Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann:
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors. ACM Trans. Archit. Code Optim. 19(3): 31:1-31:24 (2022) - [j67]Xing Huang, Wenzhong Guo, Zhisheng Chen, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization. IEEE Trans. Computers 71(2): 464-478 (2022) - [j66]Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann:
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2185-2198 (2022) - [j65]Hui-Chieh Yu, Yu-Huei Lin, Zhiyang Chen, Bing Li, Xing Huang, Ulf Schlichtmann, Tsung-Yi Ho, Hailong Yao:
Contamination-Aware Synthesis for Programmable Microfluidic Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5016-5029 (2022) - [j64]Xiao Moyuan, Tsun-Ming Tseng, Ulf Schlichtmann:
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5261-5274 (2022) - [j63]Xing Huang, Tsung-Yi Ho, Zepeng Li, Genggeng Liu, Lu Wang, Qingshan Li, Wenzhong Guo, Bing Li, Ulf Schlichtmann:
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5449-5463 (2022) - [j62]Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann:
VirtualSync+: Timing Optimization With Virtual Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5526-5540 (2022) - [c198]Felix Last, Ceren Yeni, Ulf Schlichtmann:
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level. ASP-DAC 2022: 506-512 - [c197]Jiahao Cai, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin:
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory. DAC 2022: 751-756 - [c196]Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao:
GNN-based concentration prediction for random microfluidic mixers. DAC 2022: 763-768 - [c195]Duan Shen, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
Contamination-Free Switch Design and Synthesis for Microfluidic Large-Scale Integration. DATE 2022: 646-651 - [c194]Grace Li Zhang, Shuhang Zhang, Hai Helen Li, Ulf Schlichtmann:
RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming. DSD 2022: 423-428 - [c193]Francesco Angione, Davide Appello, J. Aribido, Jyotika Athavale, Nicolò Bellarmino, Paolo Bernardi, Riccardo Cantoro, Corrado De Sio, Tommaso Foscale, Gabriele Gavarini, J. Guerrero, Martin Huch, Giusy Iaria, Tobias Kilian, Riccardo Mariani, Raffaele Martone, Annachiara Ruospo, Ernesto Sánchez, Ulf Schlichtmann, Giovanni Squillero, Matteo Sonza Reorda, Luca Sterpone, Vincenzo Tancorre, Roberto Ugioli:
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip. ETS 2022: 1-10 - [c192]Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann:
Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators. ETS 2022: 1-6 - [c191]Conrad Foik, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation. FDL 2022: 1-8 - [c190]Siyuan Liang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer Design. ICCAD 2022: 116:1-116:9 - [c189]Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data. IOLTS 2022: 1-7 - [c188]Wenwen Ye, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin:
Aging Aware Retraining for Memristor-based Neuromorphic Computing. ISCAS 2022: 3294-3298 - [c187]Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann:
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data. ITC 2022: 258-267 - [c186]Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V. MECO 2022: 1-4 - [c185]Ahsan Saeed, Dakshina Dasari, Dirk Ziegenbein, Varun Rajasekaran, Falk Rehm, Michael Pressler, Arne Hamann, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores. RTAS 2022: 133-145 - [i30]Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann:
VirtualSync+: Timing Optimization with Virtual Synchronization. CoRR abs/2203.05516 (2022) - [i29]Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann:
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation. CoRR abs/2211.14917 (2022) - [i28]Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann:
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. CoRR abs/2211.14926 (2022) - [i27]Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li, Ulf Schlichtmann:
Class-based Quantization for Neural Networks. CoRR abs/2211.14928 (2022) - [i26]Christopher Wolters, Brady Taylor, Edward Hanson, Xiaoxuan Yang, Ulf Schlichtmann, Yiran Chen:
Biologically Plausible Learning on Neuromorphic Hardware Architectures. CoRR abs/2212.14337 (2022) - 2021
- [j61]Marilyn Wolf, Jörg Henkel, Raviv Gal, Ulf Schlichtmann:
Report on First and Second ACM/IEEE Workshop on Machine Learning for CAD (MLCAD). IEEE Des. Test 38(2): 97-99 (2021) - [j60]Rafael Stahl, Alexander Hoffman, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices. Int. J. Parallel Program. 49(4): 600-624 (2021) - [j59]Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs. ACM Trans. Archit. Code Optim. 18(1): 8:1-8:25 (2021) - [j58]Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 115-128 (2021) - [j57]Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance. ACM Trans. Embed. Comput. Syst. 20(5s): 70:1-70:22 (2021) - [c184]Shuhang Zhang, Hai Helen Li, Ulf Schlichtmann:
Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars. ASP-DAC 2021: 107-113 - [c183]Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology. ASP-DAC 2021: 568-573 - [c182]Grace Li Zhang, Bing Li, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann:
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks. ASP-DAC 2021: 853-858 - [c181]Di Gao, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo:
Bayesian Inference Based Robust Computing on Memristor Crossbar. DAC 2021: 121-126 - [c180]Jingyao Zhang, Huaxi Gu, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs. DATE 2021: 667-672 - [c179]Grace Li Zhang, Bing Li, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann:
An Efficient Programming Framework for Memristor-based Neuromorphic Computing. DATE 2021: 1068-1073 - [c178]Yu Qian, Zhenhao Fan, Haoran Wang, Chao Li, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin:
Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory. DATE 2021: 1090-1095 - [c177]Xiao Moyuan, Tsun-Ming Tseng, Ulf Schlichtmann:
FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs. DATE 2021: 1651-1656 - [c176]Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero:
Exploiting Active Learning for Microcontroller Performance Prediction. ETS 2021: 1-4 - [c175]Di Gao, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo:
Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training. ICCAD 2021: 1-9 - [c174]Xing Huang, Youlin Pan, Zhen Chen, Wenzhong Guo, Robert Wille, Tsung-Yi Ho, Ulf Schlichtmann:
BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems. ICCAD 2021: 1-8 - [c173]Tsun-Ming Tseng, Meng Lian, Mengchu Li, Philipp Rinklin, Leroy Grob, Bernhard Wolfrum, Ulf Schlichtmann:
Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics. ICCAD 2021: 1-8 - [c172]Shuhang Zhang, Hai Li, Ulf Schlichtmann:
Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing. ICCAD 2021: 1-9 - [c171]Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip. ICCAD 2021: 1-9 - [c170]Fangda Zuo, Mengchu Li, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann:
Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips. ICCAD 2021: 1-9 - [c169]Yu-Kai Chuang, Yong Zhong, Yi-Hao Cheng, Bo-Yi Yu, Shao-Yun Fang, Bing Li, Ulf Schlichtmann:
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection. ISQED 2021: 67-72 - [c168]Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann:
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators. ITC 2021: 299-303 - [c167]Felix Last, Ulf Schlichtmann:
Feeding Hungry Models Less: Deep Transfer Learning for Embedded Memory PPA Models : Special Session. MLCAD 2021: 1-6 - [c166]Ahsan Saeed, Daniel Mueller-Gritschneder, Falk Rehm, Arne Hamann, Dirk Ziegenbein, Ulf Schlichtmann, Andreas Gerstlauer:
Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores. MLCAD 2021: 1-6 - [i25]Felix Last, Ceren Yeni, Ulf Schlichtmann:
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level. CoRR abs/2109.09502 (2021) - 2020
- [j56]Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface. IEEE Embed. Syst. Lett. 12(2): 66-69 (2020) - [j55]Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. Integr. 72: 1-12 (2020) - [j54]Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 359-372 (2020) - [j53]Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li:
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 613-625 (2020) - [j52]Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2489-2502 (2020) - [j51]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Test Generation for Flow-Based Microfluidic Biochips With General Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2530-2543 (2020) - [j50]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4482-4495 (2020) - [j49]Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann:
PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5197-5210 (2020) - [j48]Felix Last, Max Haeberlein, Ulf Schlichtmann:
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks. ACM Trans. Design Autom. Electr. Syst. 25(5): 39:1-39:19 (2020) - [j47]Yong Hu, Marcel Mettler, Daniel Mueller-Gritschneder, Thomas Wild, Andreas Herkersdorf, Ulf Schlichtmann:
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. ACM Trans. Design Autom. Electr. Syst. 25(5): 44:1-44:27 (2020) - [c165]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects. AICAS 2020: 11-15 - [c164]Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation. ASP-DAC 2020: 80-84 - [c163]Mengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann:
Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips. ASP-DAC 2020: 109-114 - [c162]Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann:
Timing Resilience for Efficient and Secure Circuits. ASP-DAC 2020: 623-628 - [c161]Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy:
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. DATE 2020: 1335-1338 - [c160]Shuhang Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines. DATE 2020: 1426-1431 - [c159]Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann:
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise. DATE 2020: 1590-1593 - [c158]Grace Li Zhang, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho, Hai (Helen) Li, Ulf Schlichtmann:
Reliable and Robust RRAM-based Neuromorphic Computing. ACM Great Lakes Symposium on VLSI 2020: 33-38 - [c157]Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann:
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips. ICCAD 2020: 29:1-29:8 - [c156]Alexandre Truppel, Tsun-Ming Tseng, Ulf Schlichtmann:
PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction. ICCAD 2020: 43:1-43:9 - [c155]Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin:
Overview of 2020 CAD Contest at ICCAD. ICCAD 2020: 67:1-67:3 - [c154]Ying Zhu, Grace Li Zhang, Bing Li, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann:
Countering Variations and Thermal Effects for Accurate Optical Neural Networks. ICCAD 2020: 152:1-152:7 - [c153]Riccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero:
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors. ITC 2020: 1-5 - [c152]Felix Last, Ulf Schlichtmann:
Partial Sharing Neural Networks for Multi-Target Regression on Power and Performance of Embedded Memories. MLCAD 2020: 123-128 - [c151]Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. VLSID 2020: 49-54 - [e2]Ulf Schlichtmann, Raviv Gal, Hussam Amrouch, Hai (Helen) Li:
MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, Virtual Event, Iceland, November 16-20, 2020. ACM 2020, ISBN 978-1-4503-7519-1 [contents] - [i24]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020) - [i23]Felix Last, Max Haeberlein, Ulf Schlichtmann:
Predicting Memory Compiler Performance Outputs using Feed-Forward Neural Networks. CoRR abs/2003.03269 (2020)
2010 – 2019
- 2019
- [j46]Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann:
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 705-718 (2019) - [j45]Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1237-1250 (2019) - [j44]Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann:
Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2255-2270 (2019) - [c150]Petra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. ASP-DAC 2019: 33-38 - [c149]Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. ASP-DAC 2019: 96-103 - [c148]Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Ulf Schlichtmann:
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports. DAC 2019: 145 - [c147]Michael Schwarz, Raphael Stahl, Daniel Müller-Gritschneder, Ulf Schlichtmann, Dominik Stoffel, Wolfgang Kunz:
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization. DAC 2019: 187 - [c146]Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, Subhasish Mitra:
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. DAC 2019: 198 - [c145]Tim Fritzmann, Uzair Sharif, Daniel Müller-Gritschneder, Cezar Reinbrecht, Ulf Schlichtmann, Johanna Sepúlveda:
Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V. DATE 2019: 1148-1153 - [c144]Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Sani R. Nassif:
SRAM Design Exploration with Integrated Application-Aware Aging Analysis. DATE 2019: 1249-1252 - [c143]Zhisheng Chen, Xing Huang, Wenzhong Guo, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage. DATE 2019: 1525-1530 - [c142]Yu-Huei Lin, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann:
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices. DATE 2019: 1531-1536 - [c141]Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann:
Fault Localization in Programmable Microfluidic Devices. DATE 2019: 1607-1610 - [c140]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing. DATE 2019: 1751-1756 - [c139]Mengchu Li, Tsun-Ming Tseng, Yanlu Ma, Tsung-Yi Ho, Ulf Schlichtmann:
VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips. ICCAD 2019: 1-8 - [c138]Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin:
Overview of 2019 CAD Contest at ICCAD. ICCAD 2019: 1-2 - [c137]Tsun-Ming Tseng, Mengchu Li, Yushen Zhang, Tsung-Yi Ho, Ulf Schlichtmann:
Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper. ICCAD 2019: 1-6 - [c136]Tsun-Ming Tseng, Alexandre Truppel, Mengchu Li, Mahdi Nikdast, Ulf Schlichtmann:
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper. ICCAD 2019: 1-6 - [c135]Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann:
PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs. ISPD 2019: 49-56 - [c134]Xu Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou:
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation. ISQED 2019: 76-80 - [c133]Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs. NEWCAS 2019: 1-4 - [c132]Rafael Stahl, Zhuoran Zhao, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices. SAMOS 2019: 77-90 - [i22]Krishnendu Chakrabarty, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann:
Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152). Dagstuhl Reports 9(4): 43-58 (2019) - 2018
- [j43]Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [j42]Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann:
Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices. Microelectron. J. 79: 38-45 (2018) - [j41]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 392-405 (2018) - [j40]Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, Ulf Schlichtmann:
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1588-1601 (2018) - [j39]Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fault Injection for Test-Driven Development of Robust SoC Firmware. ACM Trans. Embed. Comput. Syst. 17(1): 19:1-19:26 (2018) - [j38]Munish Jassi, Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs. ACM Trans. Design Autom. Electr. Syst. 23(3): 40:1-40:26 (2018) - [j37]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2395-2405 (2018) - [c131]Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann:
On enabling diagnosis for 1-Pin Test fails in an industrial flow. ASP-DAC 2018: 233-238 - [c130]Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC 2018: 26:1-26:6 - [c129]Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann:
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. DAC 2018: 151:1-151:6 - [c128]Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Amy Mongersun, Ismail Emre Araci, Tsung-Yi Ho, Ulf Schlichtmann:
Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration. DAC 2018: 163:1-163:6 - [c127]Chunfeng Liu, Bing Li, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann:
Design-for-testability for continuous-flow microfluidic biochips. DAC 2018: 164:1-164:6 - [c126]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c125]Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann:
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. DATE 2018: 609-612 - [c124]Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis. DATE 2018: 1484-1487 - [c123]Yasamin Moradi, Krishnendu Chakrabarty, Ulf Schlichtmann:
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis. ETS 2018: 1-2 - [c122]Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation. FDL 2018: 5-16 - [c121]Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann:
Automatic Design of Microfluidic Devices. FDL 2018: 5-16 - [c120]Mengchu Li, Tsun-Ming Tseng, Davide Bertozzi, Mahdi Tala, Ulf Schlichtmann:
CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs. ICCAD 2018: 100 - [c119]Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search. ICCAD 2018: 102 - [c118]Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD 2018: 123 - [c117]Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann:
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML. ICCAD 2018: 127 - [c116]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration. ICICDT 2018: 97-100 - [c115]Petra R. Maier, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary. IOLTS 2018: 119-122 - [c114]Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Kluge, Ulf Schlichtmann:
Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping. IOLTS 2018: 220-225 - [c113]Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann:
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS 2018: 1-4 - [c112]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. ISVLSI 2018: 715-718 - 2017
- [j36]Elisabeth Glocker, Qingqing Chen, Ulf Schlichtmann, Doris Schmitt-Landsiedel:
Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping. Microprocess. Microsystems 50: 90-101 (2017) - [j35]Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(6): 1488-1499 (2017) - [j34]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1313-1326 (2017) - [c111]Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC 2017: 524-529 - [c110]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC 2017: 49:1-49:6 - [c109]Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling. DAC 2017: 51:1-51:6 - [c108]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing microfluidic Fully Programmable Valve Arrays (FPVAs). DATE 2017: 91-96 - [c107]Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform. DATE 2017: 1673-1678 - [c106]Bing Li, Ulf Schlichtmann:
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs). DFT 2017: 1 - [c105]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
A Method for Phase Noise Analysis of RF Circuits. ACM Great Lakes Symposium on VLSI 2017: 227-231 - [c104]Yong Hu, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Model-based framework for networks-on-chip design space exploration. AISTECS@HiPEAC 2017: 32-35 - [c103]Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann:
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening. ICCAD 2017: 623-630 - [c102]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Methodology for automated phase noise minimization in RF circuit interconnect trees. ISCAS 2017: 1-4 - [c101]Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann:
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP 2017: 79-84 - [c100]Ulf Schlichtmann:
Frontiers of timing. SLIP 2017: 1-4 - [c99]Shushanik Karapetyan, Ulf Schlichtmann:
20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics. SMACD 2017: 1-4 - [c98]Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi:
Generative adversarial network based scalable on-chip noise sensor placement. SoCC 2017: 239-242 - [c97]Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann:
Application of machine learning methods in post-silicon yield improvement. SoCC 2017: 243-248 - [e1]Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar:
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017. IEEE 2017, ISBN 978-1-5386-4034-0 [contents] - [i21]Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
Static Timing Model Extraction for Combinational Circuits. CoRR abs/1705.02610 (2017) - [i20]Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann:
On Hierarchical Statistical Static Timing Analysis. CoRR abs/1705.04975 (2017) - [i19]Bing Li, Ning Chen, Ulf Schlichtmann:
Timing Model Extraction for Sequential Circuits Considering Process Variations. CoRR abs/1705.04976 (2017) - [i18]Bing Li, Ning Chen, Ulf Schlichtmann:
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers. CoRR abs/1705.04979 (2017) - [i17]Bing Li, Ning Chen, Ulf Schlichtmann:
Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. CoRR abs/1705.04980 (2017) - [i16]Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann:
On Timing Model Extraction and Hierarchical Statistical Timing Analysis. CoRR abs/1705.04981 (2017) - [i15]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation. CoRR abs/1705.04982 (2017) - [i14]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards. CoRR abs/1705.04983 (2017) - [i13]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing. CoRR abs/1705.04984 (2017) - [i12]Bing Li, Ulf Schlichtmann:
Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements. CoRR abs/1705.04986 (2017) - [i11]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Storage and Caching: Synthesis of Flow-based Microfluidic Biochips. CoRR abs/1705.04988 (2017) - [i10]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability. CoRR abs/1705.04990 (2017) - [i9]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing. CoRR abs/1705.04991 (2017) - [i8]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. CoRR abs/1705.04992 (2017) - [i7]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model. CoRR abs/1705.04993 (2017) - [i6]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. CoRR abs/1705.04995 (2017) - [i5]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing Microfluidic Fully Programmable Valve Arrays (FPVAs). CoRR abs/1705.04996 (2017) - [i4]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR abs/1705.04998 (2017) - 2016
- [j33]Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel:
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58(6): 297-307 (2016) - [j32]Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann:
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer. ACM J. Emerg. Technol. Comput. Syst. 12(4): 44:1-44:28 (2016) - [j31]Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou:
Editorial. Microelectron. Reliab. 61: 1-2 (2016) - [j30]Shushanik Karapetyan, Veit Kleeberger, Ulf Schlichtmann:
FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies. Microelectron. Reliab. 61: 30-34 (2016) - [j29]André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Binjie Cheng, Asen Asenov, Ulf Schlichtmann:
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 197-210 (2016) - [j28]Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann:
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 1981-1994 (2016) - [c96]Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li:
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC 2016: 705-711 - [c95]Petra R. Maier, Veit Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing. CODES+ISSS 2016: 18:1-18:10 - [c94]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. DAC 2016: 60:1-60:6 - [c93]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. DAC 2016: 101:1-101:6 - [c92]Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Columba: co-layout synthesis for continuous-flow microfluidic biochips. DAC 2016: 147:1-147:6 - [c91]Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. DATE 2016: 624-629 - [c90]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based buffer insertion for post-silicon yield improvement under process variability. DATE 2016: 1457-1460 - [c89]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Fully synthesized time-to-digital converter for cellular transceivers. EBCCSP 2016: 1-5 - [c88]Munish Jassi, Uzair Sharif, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs. ACM Great Lakes Symposium on VLSI 2016: 287-292 - [c87]Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann:
Where formal verification can help in functional safety analysis. ICCAD 2016: 85 - [c86]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model. ICCAD 2016: 100 - [c85]Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai:
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD 2016: 103 - [c84]Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler:
From biochips to quantum circuits: computer-aided design for emerging technologies. ICCAD 2016: 132 - [c83]Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann:
Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models. ISIC 2016: 1-2 - [c82]Anja von Beuningen, Ulf Schlichtmann:
PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip. ISPD 2016: 27-34 - [c81]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Synthesis-based methodology for high-speed multi-modulus divider. SMACD 2016: 1-4 - [c80]Jie Wu, Ulf Schlichtmann, Yiyu Shi:
On the measurement of power grid robustness under load uncertainties. SmartGridComm 2016: 218-223 - [c79]Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann:
Efficient handling of the fault space in functional safety analysis utilizing formal methods. VLSI-SoC 2016: 1-7 - 2015
- [j27]Tsun-Ming Tseng, Bing Li, Ulf Schlichtmann, Tsung-Yi Ho:
Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips. IEEE Des. Test 32(6): 69-75 (2015) - [j26]Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Müller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis:
Application-aware cross-layer reliability analysis and optimization. it Inf. Technol. 57(3): 159-169 (2015) - [j25]Martin Barke, Ulf Schlichtmann:
A Cross-Layer Approach to Measure the Robustness of Integrated Circuits. ACM J. Emerg. Technol. Comput. Syst. 12(3): 24:1-24:22 (2015) - [j24]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 1000-1013 (2015) - [j23]Bing Li, Ulf Schlichtmann:
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1784-1797 (2015) - [c78]Munish Jassi, Daniel Müller-Gritschneder, Ulf Schlichtmann:
GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs. DAC 2015: 46:1-46:6 - [c77]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping. DAC 2015: 141:1-141:6 - [c76]Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu:
Timing verification for adaptive integrated circuits. DATE 2015: 1587-1590 - [c75]Yong Hu, Daniel Müller-Gritschneder, Martha Johanna Sepúlveda, Guy Gogniat, Ulf Schlichtmann:
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip. INA-OCMC@HiPEAC 2015: 9-12 - [c74]Ulf Schlichtmann:
Beyond GORDIAN and Kraftwerk: EDA Research at TUM. ISPD 2015: 133-140 - [c73]Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel:
Emulation of an ASIC power and temperature monitor system for FPGA prototyping. ReCoSoC 2015: 1-8 - [c72]Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann:
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES 2015: 121-124 - [c71]Qingqing Chen, Ulrich Rührmair, Spoorthy Narayana, Uzair Sharif, Ulf Schlichtmann:
MWA Skew SRAM Based SIMPL Systems for Public-Key Physical Cryptography. TRUST 2015: 268-282 - [c70]Shushanik Karapetyan, Ulf Schlichtmann:
Integrating aging aware timing analysis into a commercial STA tool. VLSI-DAT 2015: 1-4 - 2014
- [j22]Michael Linder, Alfred Eder, Ulf Schlichtmann, Klaus Oberländer:
An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms. IEEE Des. Test 31(3): 42-53 (2014) - [j21]Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou:
Special section reliability and variability of devices for circuits and systems. Microelectron. Reliab. 54(6-7): 1057 (2014) - [j20]Martin Barke, Michael Kärgel, Markus Olbrich, Ulf Schlichtmann:
Robustness measurement of integrated circuits and its adaptation to aging effects. Microelectron. Reliab. 54(6-7): 1058-1065 (2014) - [j19]Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich:
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. Microelectron. Reliab. 54(6-7): 1066-1074 (2014) - [j18]Dominik Lorenz, Martin Barke, Ulf Schlichtmann:
Monitoring of aging in integrated circuits by identifying possible critical paths. Microelectron. Reliab. 54(6-7): 1075-1082 (2014) - [j17]Veit B. Kleeberger, Martin Barke, Christoph Werner, Doris Schmitt-Landsiedel, Ulf Schlichtmann:
A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits. Microelectron. Reliab. 54(6-7): 1083-1089 (2014) - [j16]Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann:
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1503-1516 (2014) - [c69]Veit Kleeberger, Petra R. Maier, Ulf Schlichtmann:
Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience. DAC 2014: 49:1-49:6 - [c68]Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl:
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. DAC 2014: 113:1-113:6 - [c67]André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann:
Probabilistic standard cell modeling considering non-Gaussian parameters and correlations. DATE 2014: 1-4 - [c66]Ulrich Rührmair, Ulf Schlichtmann, Wayne P. Burleson:
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks. DATE 2014: 1-4 - [c65]Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn:
Connecting different worlds - Technology abstraction for reliability-aware design and Test. DATE 2014: 1-8 - [c64]Daniel Mueller-Gritschneder, Petra R. Maier, Marc Greim, Ulf Schlichtmann:
System C-based multi-level error injection for the evaluation of fault-tolerant systems. ISIC 2014: 460-463 - [c63]Dip Goswami, Daniel Mueller-Gritschneder, Twan Basten, Ulf Schlichtmann, Samarjit Chakraborty:
Fault-tolerant embedded control systems for unreliable hardware. ISIC 2014: 464-467 - [i3]Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel:
Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture. CoRR abs/1405.2909 (2014) - 2013
- [j15]Veit Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn:
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. IEEE Micro 33(4): 46-55 (2013) - [j14]Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann:
On Timing Model Extraction and Hierarchical Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 367-380 (2013) - [c62]Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software. ASP-DAC 2013: 729-734 - [c61]Veit Kleeberger, Helmut E. Graeb, Ulf Schlichtmann:
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. DAC 2013: 33:1-33:6 - [c60]Georg Georgakos, Ulf Schlichtmann, Reinhard Schneider, Samarjit Chakraborty:
Reliability challenges for electric vehicles: from devices to architecture and systems software. DAC 2013: 98:1-98:9 - [c59]Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fast cache simulation for host-compiled simulation of embedded software. DATE 2013: 637-642 - [c58]Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts. DATE 2013: 1161-1166 - [c57]Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann:
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot. DATE 2013: 1331-1334 - [c56]Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann:
A spectral clustering approach to application-specific network-on-chip synthesis. DATE 2013: 1783-1788 - [c55]Veit Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling. DFTS 2013: 118-124 - [c54]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-route refinement for high-frequency PCBs considering meander segment alleviation. ACM Great Lakes Symposium on VLSI 2013: 323-324 - [c53]Anja Boos, Luca Ramini, Ulf Schlichtmann, Davide Bertozzi:
PROTON: an automatic place-and-route tool for optical networks-on-chip. ICCAD 2013: 138-145 - [c52]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-route alleviation of dense meander segments in high-performance printed circuit boards. ICCAD 2013: 713-720 - [c51]Amit Verma, Pritpal S. Multani, Daniel Mueller-Gritschneder, Vladimir Todorov, Ulf Schlichtmann:
A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs. NOCS 2013: 1-7 - [c50]Carsten Uphoff, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty. SysCon 2013: 536-541 - 2012
- [j13]Ning Chen, Bing Li, Ulf Schlichtmann:
Iterative timing analysis based on nonlinear and interdependent flipflop modelling. IET Circuits Devices Syst. 6(5): 330-337 (2012) - [j12]Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou:
ICMAT 2011 - Reliability and variability of semiconductor devices and ICs. Microelectron. Reliab. 52(8): 1531 (2012) - [j11]Dominik Lorenz, Martin Barke, Ulf Schlichtmann:
Efficiently analyzing the impact of aging effects on large integrated circuits. Microelectron. Reliab. 52(8): 1546-1552 (2012) - [j10]Bing Li, Ning Chen, Ulf Schlichtmann:
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1670-1683 (2012) - [c49]Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann:
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. CODES+ISSS 2012: 181-186 - [c48]Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Accurately timed transaction level models for virtual prototyping at high abstraction level. DATE 2012: 135-140 - [c47]Christoph Knoth, Hela Jedda, Ulf Schlichtmann:
Current source modeling for power and timing analysis at different supply voltages. DATE 2012: 923-928 - [c46]Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann:
Automated construction of a cycle-approximate transaction level model of a memory controller. DATE 2012: 1066-1071 - [c45]Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair:
Characterization of the bistable ring PUF. DATE 2012: 1459-1462 - [c44]Kun Lu, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Hierarchical control flow matching for source-level simulation of embedded software. ISSoC 2012: 1-5 - [c43]Alejandro Masrur, Philipp H. Kindt, Martin Becker, Samarjit Chakraborty, Veit Kleeberger, Martin Barke, Ulf Schlichtmann:
Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling. RTCSA 2012: 11-20 - 2011
- [j9]Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Martin Stutzmann, Ulrich Rührmair:
Circuit-Based Approaches to Simpl Systems. J. Circuits Syst. Comput. 20(1): 107-123 (2011) - [j8]Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb:
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 180-193 (2011) - [c42]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich:
Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78 - [c41]Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann:
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level. DSD 2011: 600-607 - [c40]Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair:
The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions. HOST 2011: 134-141 - [c39]Ning Chen, Bing Li, Ulf Schlichtmann:
Timing Modeling of Flipflops Considering Aging Effects. PATMOS 2011: 63-72 - [c38]Ning Chen, Bing Li, Ulf Schlichtmann:
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. PATMOS 2011: 73-82 - [c37]Christoph Knoth, Carsten Uphoff, Sebastian Kiesel, Ulf Schlichtmann:
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging. PATMOS 2011: 193-203 - [c36]Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation. ICSAMOS 2011: 150-156 - 2010
- [j7]Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann:
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene). it Inf. Technol. 52(4): 181-188 (2010) - [c35]Dominik Lorenz, Martin Barke, Ulf Schlichtmann:
Aging analysis at gate and macro cell level. ICCAD 2010: 77-84 - [c34]Bing Li, Ning Chen, Ulf Schlichtmann:
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods. ICCAD 2010: 524-531 - [c33]Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann:
Automatic generation of hierarchical placement rules for analog integrated circuits. ISPD 2010: 47-54 - [c32]Christoph Knoth, Irina Eichwald, Petra Nordholz, Ulf Schlichtmann:
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation. PATMOS 2010: 200-210 - [c31]Ulrich Rührmair, Qingqing Chen, Martin Stutzmann, Paolo Lugli, Ulf Schlichtmann, György Csaba:
Towards Electrical, Integrated Implementations of SIMPL Systems. WISTP 2010: 277-292
2000 – 2009
- 2009
- [j6]Helmut Graeb, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Pareto optimization of analog circuits considering variability. Int. J. Circuit Theory Appl. 37(2): 283-299 (2009) - [j5]Daniel Mueller-Gritschneder, Helmut E. Graeb, Ulf Schlichtmann:
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. SIAM J. Optim. 20(2): 915-934 (2009) - [c30]Christoph Knoth, Veit B. Kleeberger, Petra Nordholz, Ulf Schlichtmann:
Fast and waveform independent characterization of current source models. BMAS 2009: 90-95 - [c29]Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann:
On hierarchical statistical static timing analysis. DATE 2009: 1320-1325 - [c28]Ulf Schlichtmann, Manuel Schmidt, Harald Kinzelbach, Michael Pronath, Volker Glöckel, Manfred Dietrich, Uwe Eichler, Joachim Haase:
Digital design at a crossroads How to make statistical design methodologies industrially relevant. DATE 2009: 1542-1547 - [c27]Engin Avci, Martin Strasser, Helmut Graeb, Ulf Schlichtmann:
A free-shape router for analog and RF applications. ECCTD 2009: 771-774 - [c26]Bing Li, Ning Chen, Ulf Schlichtmann:
Timing model extraction for sequential circuits considering process variations. ICCAD 2009: 333-343 - [c25]Ning Chen, Bing Li, Ulf Schlichtmann:
Sensitivity based parameter reduction for statistical analysis of circuit performance. ICECS 2009: 443-446 - [c24]Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann:
Aging analysis of circuit timing considering NBTI and HCI. IOLTS 2009: 3-8 - [i2]György Csaba, Xueming Ju, Qingqing Chen, Wolfgang Porod, Jürgen Schmidhuber, Ulf Schlichtmann, Paolo Lugli, Ulrich Rührmair:
On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions. IACR Cryptol. ePrint Arch. 2009: 246 (2009) - [i1]Ulrich Rührmair, Qingqing Chen, Paolo Lugli, Ulf Schlichtmann, Martin Stutzmann, György Csaba:
Towards Electrical, Integrated Implementations of SIMPL Systems. IACR Cryptol. ePrint Arch. 2009: 278 (2009) - 2008
- [j4]Peter Spindler, Ulf Schlichtmann, Frank M. Johannes:
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1398-1411 (2008) - [j3]Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2209-2222 (2008) - [c23]Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
Sizing Rules for Bipolar Analog Circuit Design. DATE 2008: 140-145 - [c22]Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann, Frank M. Johannes:
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. ICCAD 2008: 306-313 - [c21]Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD 2008: 188-193 - [c20]Peter Spindler, Ulf Schlichtmann, Frank M. Johannes:
Abacus: fast legalization of standard cell circuits with minimal movement. ISPD 2008: 47-53 - [c19]Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
Static Timing Model Extraction for Combinational Circuits. PATMOS 2008: 156-166 - [c18]Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann:
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. PATMOS 2008: 167-177 - 2007
- [c17]Jun Zou, Helmut Graeb, Daniel Mueller, Ulf Schlichtmann:
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. CICC 2007: 607-610 - [c16]Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann:
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE 2007: 75-80 - [c15]Helmut Graeb, Daniel Mueller, Ulf Schlichtmann:
Pareto optimization of analog circuits considering variability. ECCTD 2007: 28-31 - [c14]Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann:
Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED 2007: 481-486 - 2006
- [c13]Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann:
A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC 2006: 19-24 - [c12]Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp:
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE 2006: 387-392 - [c11]Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann:
Fast evaluation of analog circuit structures by polytopal approximations. ISCAS 2006 - 2005
- [c10]Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann:
Deterministic approaches to analog performance space exploration (PSE). DAC 2005: 869-874 - [c9]Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann:
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) 2005: 334-338 - 2004
- [c8]Christian Piguet, Jacques Gautier, Christoph Heer, Ian O'Connor, Ulf Schlichtmann:
Extremely Low-Power Logic. DATE 2004: 656-663 - [c7]Ulf Schlichtmann:
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance. DSD 2004: 52-59 - [p1]Christoph Heer, Ulf Schlichtmann:
Ultra-Low-Power Design: Device and Logic Design Approaches. Ultra Low-Power Electronics and Design 2004: 1-20 - 2002
- [c6]K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment:
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. DATE 2002: 538 - [c5]Ulf Schlichtmann:
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. DSD 2002: 2-3 - [c4]Ulf Schlichtmann:
Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today. ISQED 2002: 225-
1990 – 1999
- 1999
- [j2]Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich:
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 4(3): 313-350 (1999) - 1996
- [j1]Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth:
Fast Power Estimation of Large Circuits. IEEE Des. Test Comput. 13(1): 70-78 (1996) - 1995
- [b1]Ulf Schlichtmann:
Logiksynthese für komplexe anwenderprogrammierbare elektronische Bausteine. Technical University Munich, Germany, 1995, pp. 1-135 - 1994
- [c3]Peter H. Schneider, Kurt Antreich, Ulf Schlichtmann:
A new power estimation technique with application to decomposition of Boolean functions for low power. EURO-DAC 1994: 388-393 - 1992
- [c2]Ulf Schlichtmann, Franc Brglez, Michael Hermann:
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. DAC 1992: 374-379 - 1991
- [c1]Georg Sigl, Ulf Schlichtmann:
Goal oriented slicing enumeration through shape function clipping. EURO-DAC 1991: 361-365
Coauthor Index
[j83] [j82] [c236] [c235] [c232] [j76] [c209] [c208] [c205] [c204] [j69] [j67] [j66] [j65] [j63] [c196] [c190] [j58] [c182] [c179] [c174] [c170] [j53] [j52] [j51] [c159] [c158] [c157] [c154] [c148] [c143] [c142] [c139] [c137] [i22] [j40] [c128] [c127] [c118] [c116] [j35] [c111] [c110] [c109] [c108] [i15] [i14] [i13] [i11] [i5] [i4] [j28] [c92] [c91] [c85] [j27] [j24] [c77] [c54] [c52]
Veit Kleeberger
aka: Veit B. Kleeberger
aka: Veit B. Kleeberger
[j81] [c240] [c234] [c233] [c231] [c230] [c226] [c225] [i44] [i42] [i41] [i40] [i39] [i38] [i37] [j78] [j77] [j75] [j73] [c220] [c219] [c215] [c214] [c206] [c200] [c199] [i36] [i34] [i32] [i31] [j69] [j67] [j66] [j65] [j63] [j62] [c197] [c188] [i30] [i29] [i28] [i27] [j58] [c182] [c181] [c180] [c179] [c178] [c175] [c169] [j53] [j52] [j51] [j50] [c165] [c162] [c161] [c160] [c159] [c158] [c157] [c154] [i24] [j46] [c148] [c143] [c142] [c141] [c140] [j43] [j42] [j41] [j40] [c130] [c129] [c127] [c126] [c121] [c118] [c116] [c113] [c112] [j35] [j34] [c111] [c110] [c109] [c108] [c106] [c97] [i21] [i20] [i19] [i18] [i17] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [i9] [i8] [i7] [i6] [i5] [i4] [j28] [c96] [c94] [c93] [c92] [c91] [c90] [c86] [c85] [c84] [j27] [j24] [j23] [c77] [c76] [j14] [c54] [c52] [j13] [j10] [c39] [c38] [c34] [c29] [c26] [c25] [c19] [c18]
[c239] [c238] [c229] [c227] [c224] [c222] [c221] [c217] [c216] [c211] [c207] [i35] [i33] [j68] [c191] [c186] [c185] [j60] [j59] [j57] [c166] [j56] [j47] [c164] [c151] [c150] [c147] [c146] [c145] [c144] [c133] [c132] [j39] [j38] [c125] [c122] [c119] [c117] [c115] [c114] [c104] [c101] [c95] [c88] [c83] [j26] [c78] [c75] [j19] [j16] [c68] [c64] [c63] [j15] [c62] [c59] [c58] [c57] [c56] [c55] [c51] [c50] [c48] [c46] [c44] [c41] [c36] [j6] [j5] [c17] [c16] [c15] [c14] [c13] [c11] [c10] [c9]
[j81] [j79] [c240] [c234] [c233] [c231] [c230] [c226] [c225] [i44] [i42] [i41] [i40] [i39] [i38] [i37] [j77] [j75] [j73] [c220] [c219] [c215] [c214] [c206] [i36] [i34] [i32] [i31] [j66] [j62] [c197] [c194] [c188] [i30] [i29] [i28] [i27] [c182] [c181] [c180] [c179] [c178] [c175] [j50] [c165] [c162] [c159] [c158] [c157] [c154] [i24] [j46] [c140] [j41] [c130] [c126] [c112] [c97] [i10] [i8] [i7] [i6] [c94] [c90] [c86]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-20 21:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
