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ORCIDYoshihito Amemiya
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2010 – 2019
- 2011
[j40]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya:
Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. Int. J. Unconv. Comput. 7(1-2): 53-63 (2011)- [c22]Akira Kondou, Masayuki Ikebe, Junichi Motohisa, Yoshihito Amemiya, Eiichi Sano:
A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network. ICECS 2011: 326-329 - 2010
- [j39]Nobuo Akou, Tetsuya Asai
, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya:
A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. IEICE Electron. Express 7(19): 1467-1473 (2010) - [j38]Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Trans. Electron. 93-C(6): 741-746 (2010) - [j37]Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. 93-C(6): 835-841 (2010) - [j36]Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya:
A CMOS Phase-Shift oscillator Based on the conduction of Heat. J. Circuits Syst. Comput. 19(4): 763-772 (2010) - [j35]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 681-685 (2010) - [c21]Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya:
Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) 2010: 188-195
2000 – 2009
- 2009
- [j34]Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 436-442 (2009) - [j33]Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya:
Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2508-2513 (2009) - [j32]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3079-3081 (2009) - [j31]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits 44(7): 2047-2054 (2009) - [c20]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC 2009: 95-96 - [c19]Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. ESSCIRC 2009: 392-395 - [c18]Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya:
Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS 2009: 140-143 - [c17]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya:
Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) 2009: 384-391 - [c16]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya:
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN 2009: 1600-1605 - [c15]Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS 2009: 5-8 - [c14]Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose:
On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS 2009: 1565-1568 - [c13]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya:
Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet 2009: 51-56 - 2008
- [j30]Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express 5(6): 204-210 (2008) - [j29]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2475-2481 (2008) - [j28]Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. 4(1): 45-59 (2008) - [c12]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC 2008: 398-401 - [c11]Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya:
Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) 2008: 851-858 - 2007
- [j27]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10): 2108-2115 (2007) - [j26]Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos 17(5): 1713-1719 (2007) - [j25]Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya:
Discrete Dynamical Systems Consisting of Single-electron Circuits. Int. J. Bifurc. Chaos 17(10): 3613-3617 (2007) - [j24]Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya:
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71(1-3): 3-12 (2007) - [j23]Takahide Oya, Tetsuya Asai, Yoshihito Amemiya:
A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. Int. J. Unconv. Comput. 3(4): 271-284 (2007) - [j22]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits 42(4): 798-803 (2007) - [c10]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) 2007: 117-126 - [c9]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN 2007: 897-901 - [c8]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS 2007: 3748-3751 - 2006
- [j21]Kazuhito Yamada, Ikuko N. Motoike, Tetsuya Asai, Yoshihito Amemiya:
Design methodologies for compact logic circuits based on collision-based computing. IEICE Electron. Express 3(13): 292-298 (2006) - [j20]Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express 3(22): 464-468 (2006) - [j19]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 902-907 (2006) - [j18]Yoshihito Amemiya:
Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions. IEICE Trans. Electron. 89-C(11): 1504-1511 (2006) - [j17]Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya:
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos 16(1): 207-212 (2006) - 2005
- [j16]Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya:
On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express 2(3): 76-80 (2005) - [j15]Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya:
Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. 88-C(6): 1142-1147 (2005) - [j14]Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya:
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. 1(2): 123-147 (2005) - [j13]Takahide Oya, Tetsuya Asai, Takashi Fukui, Yoshihito Amemiya:
Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. Int. J. Unconv. Comput. 1(2): 179-196 (2005) - [j12]Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya:
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005) - [j11]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1095-1103 (2005) - [c7]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) 2005: 1923-1926 - [c6]Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici:
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) 2005: 2535-2538 - 2004
- [j10]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Design of an Artificial Central Pattern Generator with Feedback Controller. Intell. Autom. Soft Comput. 10(2): 185-192 (2004) - [j9]Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express 1(4): 73-76 (2004) - [j8]Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express 1(9): 248-252 (2004) - [j7]Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya:
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. 19(4) (2004) - [j6]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. J. Robotics Mechatronics 16(4): 397-403 (2004) - [c5]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) 2004: 1-4 - 2003
- [j5]Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya:
Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. J. Robotics Mechatronics 15(2): 208-218 (2003) - [j4]Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya:
A subthreshold MOS neuron circuit based on the Volterra system. IEEE Trans. Neural Networks 14(5): 1308-1312 (2003) - [j3]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. IEEE Trans. Neural Networks 14(5): 1356-1365 (2003) - [c4]Tetsuya Asai, Yoshihito Amemiya:
Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL 2003: 197-206 - 2002
- [j2]Tetsuya Asai, Yuusaku Nishimiya, Yoshihito Amemiya:
A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(9): 2093-2096 (2002) - [c3]Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya:
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. SMC 2002: 6 - 2000
- [c2]Tetsuya Asai, Masato Koutani, Yoshihito Amemiya:
An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) 2000: 494-499
1990 – 1999
- 1998
- [c1]Masayuki Ikebe, Masamichi Akazawa, Yoshihito Amemiya:
nu-MOS cellular-automaton devices for intelligent image sensors. KES (3) 1998: 447-453 - 1994
- [j1]Takashi Morie, Yoshihito Amemiya:
An all-analog expandable neural network LSI with on-chip backpropagation learning. IEEE J. Solid State Circuits 29(9): 1086-1093 (1994)
Coauthor Index
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