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2020 – today
- 2024
[j52]Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
Programmable Differential Bandgap Reference Circuit for Ultra-Low-Power CMOS LSIs. IEICE Trans. Electron. 107(10): 392-399 (2024)- [j51]Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting. IEICE Trans. Electron. 107(10): 400-407 (2024) - [c52]Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose:
Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements. ICCE 2024: 1-4 - [c51]Ryota Tsunaga, Daisuke Kanemoto, Tetsuya Hirose:
Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing. ICCE 2024: 1-5 - [c50]Riku Matsubara, Daisuke Kanemoto, Tetsuya Hirose:
Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing. ISCAS 2024: 1-5 - 2023
- [c49]Hikaru Sebe, Tomohisa Okumura, Shintaro Sumi, Daisuke Kanemoto, Po-Hung Chen, Tetsuya Hirose:
Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting. ESSCIRC 2023: 325-328 - [c48]Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices. ISCAS 2023: 1-5 - [c47]Daisuke Kanemoto, Tetsuya Hirose:
EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix. ISCAS 2023: 1-5 - [c46]Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose:
Random Undersampling Wireless EEG Measurement Device using a Small TEG. ISCAS 2023: 1-5 - [c45]Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata:
A Triturated Sensing System. ISSCC 2023: 216-217 - 2022
- [j50]Yuuki Harada, Daisuke Kanemoto, Takahiro Inoue, Osamu Maida, Tetsuya Hirose:
Image Quality Improvement for Capsule Endoscopy Based on Compressed Sensing with K-SVD Dictionary Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(4): 743-747 (2022) - [j49]Yuki Okabe, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose:
Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(10): 1429-1433 (2022) - [c44]Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting. ISCAS 2022: 2773-2777 - 2021
- [j48]Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs. IEICE Electron. Express 18(6): 20210065 (2021) - [j47]Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa:
Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning. IEICE Trans. Inf. Syst. 104-D(1): 183-193 (2021) - 2020
- [j46]Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems. IEICE Electron. Express 17(11): 20200103 (2020) - [j45]Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa:
Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(7): 955-958 (2020) - [j44]Tetsuya Hirose, Yuichiro Nakazawa:
Design of Switched-Capacitor Voltage Boost Converter for Low-Voltage and Low-Power Energy Harvesting Systems. IEICE Trans. Electron. 103-C(10): 446-457 (2020) - [j43]Ming-Jie Chung
, Tetsuya Hirose, Takahito Ono, Po-Hung Chen:
A 115× Conversion-Ratio Thermoelectric Energy-Harvesting Battery Charger for the Internet of Things. IEEE Trans. Circuits Syst. 67-I(11): 4110-4121 (2020) - [c43]Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting. NEWCAS 2020: 38-41 - [c42]Kunihiko Taya, Nobutaka Kuroki, Naoto Takeda, Tetsuya Hirose, Masahiro Numa:
Detecting tampered regions in JPEG images via CNN. NEWCAS 2020: 202-205
2010 – 2019
- 2019
- [c41]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto:
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - [c40]Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter. ICECS 2019: 530-533 - 2018
- [j42]Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems. IEICE Trans. Electron. 101-C(3): 161-169 (2018) - [c39]Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa:
Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices. ICECS 2018: 209-212 - [c38]Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting. ISCAS 2018: 1-5 - [c37]Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto:
A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes. NEWCAS 2018: 152-156 - [c36]Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa:
An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. VLSI-SoC 2018: 196-200 - 2017
- [j41]Shinya Ohtani, Yu Kato, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa:
Multi-Channel Convolutional Neural Networks for Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 572-580 (2017) - [j40]Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Kyohei Shinonaga, Nobutaka Kuroki, Masahiro Numa:
An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 2026-2035 (2017) - [c35]Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose:
Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes. ASICON 2017: 1065-1068 - [c34]Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems. ASP-DAC 2017: 35-36 - [c33]Takanori Sato, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting. ICECS 2017: 498-501 - [c32]Yuto Tsuji, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A 0.1-0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting. ICECS 2017: 502-505 - [c31]Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications. ISCAS 2017: 1-4 - [c30]Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto:
Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. ISCAS 2017: 1-4 - 2016
- [j39]Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2491-2499 (2016) - [j38]Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting. IEEE J. Solid State Circuits 51(10): 2398-2407 (2016) - [c29]Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management. A-SSCC 2016: 225-228 - [c28]Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability. ESSCIRC 2016: 149-152 - [c27]Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems. NEWCAS 2016: 1-4 - [c26]Yu Kato, Shinya Ohtani, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa:
Image super-resolution with multi-channel convolutional neural networks. NEWCAS 2016: 1-4 - 2015
- [j37]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. IEICE Electron. Express 12(4): 20141157 (2015) - [j36]Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs. IEICE Trans. Electron. 98-C(5): 446-453 (2015) - [j35]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2600-2606 (2015) - [c25]Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. ASP-DAC 2015: 30-31 - [c24]Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting. A-SSCC 2015: 1-4 - [c23]Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa:
A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs. ISCAS 2015: 2948-2951 - 2014
- [j34]Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit. IEICE Trans. Electron. 97-C(6): 512-518 (2014) - [c22]Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters. ESSCIRC 2014: 255-258 - [c21]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. NEWCAS 2014: 137-140 - 2013
- [j33]Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye:
A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation. IEICE Electron. Express 10(4): 20130022 (2013) - [j32]Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye:
Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 459-468 (2013) - [j31]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. IEEE J. Solid State Circuits 48(6): 1530-1538 (2013) - [c20]Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application. ESSCIRC 2013: 315-318 - 2012
- [j30]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. IEEE J. Solid State Circuits 47(7): 1776-1783 (2012) - [c19]Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi:
A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC 2012: 69-72 - [c18]Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator. ICECS 2012: 97-100 - [c17]Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A low-power single-slope analog-to-digital converter with digital PVT calibration. ICECS 2012: 613-616 - [c16]Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose:
Signal-dependent analog-to-digital converter based on MINIMAX sampling. ISOCC 2012: 120-123 - 2011
- [j29]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs. IEICE Electron. Express 8(12): 890-896 (2011) - [j28]Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa:
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Trans. Electron. 94-C(1): 80-88 (2011) - [j27]Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Trans. Electron. 94-C(6): 1042-1048 (2011) - [c15]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC 2011: 113-114 - [c14]Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 18.9-nA standby current comparator with adaptive bias current generator. A-SSCC 2011: 237-240 - [c13]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202 - [c12]Tetsuya Hirose:
Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications. ISOCC 2011: 24-27 - 2010
- [j26]Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. 93-C(6): 835-841 (2010) - [j25]Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
An Error Diagnosis Technique Based on Clustering of Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2490-2496 (2010) - [j24]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 681-685 (2010) - [c11]Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. ESSCIRC 2010: 114-117 - [c10]Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa:
Super-resolution technique for thermography with dual-camera system. ISCAS 2010: 1895-1898
2000 – 2009
- 2009
- [j23]Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi:
A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control. IEICE Electron. Express 6(8): 456-460 (2009) - [j22]Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 436-442 (2009) - [j21]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3079-3081 (2009) - [j20]Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3136-3142 (2009) - [j19]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits 44(7): 2047-2054 (2009) - [c9]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC 2009: 95-96 - [c8]Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose:
On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS 2009: 1565-1568 - 2008
- [j18]Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express 5(6): 204-210 (2008) - [j17]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2475-2481 (2008) - [j16]Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. 4(1): 45-59 (2008) - [c7]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC 2008: 398-401 - 2007
- [j15]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10): 2108-2115 (2007) - [j14]Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos 17(5): 1713-1719 (2007) - [j13]Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya:
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71(1-3): 3-12 (2007) - [j12]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits 42(4): 798-803 (2007) - [c6]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) 2007: 117-126 - [c5]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN 2007: 897-901 - [c4]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS 2007: 3748-3751 - 2006
- [j11]Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express 3(22): 464-468 (2006) - [j10]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 902-907 (2006) - [j9]Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya:
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos 16(1): 207-212 (2006) - 2005
- [j8]Sungwoo Cha, Tetsuya Hirose, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi:
A CMOS IF Variable Gain Amplifier with Exponential Gain Control. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(2): 410-415 (2005) - [j7]Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya:
Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. 88-C(6): 1142-1147 (2005) - [j6]Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya:
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. 1(2): 123-147 (2005) - [j5]Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya:
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005) - 2004
- [j4]Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express 1(4): 73-76 (2004) - [j3]Masayuki Furuhashi, Tetsuya Hirose, Hiroshi Tsuji, Masayuki Tachi, Kenji Taniguchi:
Atomic configuration of boron pile-up at the Si/SiO2 interface. IEICE Electron. Express 1(6): 126-130 (2004) - [j2]Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express 1(9): 248-252 (2004) - 2000
- [c3]Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose:
A DSM Architecture for a Parallel Computer Cenju-4. HPCA 2000: 287-298
1990 – 1999
- 1999
- [c2]Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose, Takeo Hosomi, Hirokazu Takayama, Toshiyuki Nakata:
Message Passing Communication in a Parallel Computer Cenju-4. ISHPC 1999: 55-70 - 1995
- [j1]Tsutomu Maruyama, Yasushi Kanoh, Tetsuya Hirose, Kazuhiro Muramatsu, Toshiyuki Nakata, Yoshihiro Asano, Yu Inamura:
Architecture of a parallel machine: Cenju-3. Syst. Comput. Jpn. 26(14): 26-36 (1995) - 1993
- [c1]Tsutomu Maruyama, Tetsuya Hirose, Akihiko Konagaya:
A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems. ICGA 1993: 184-190
Coauthor Index
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