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2020 – today
- 2022
[j43]Kuen-Jong Lee
, Zheng-Yao Lu, Shih-Chun Yeh:
A Secure JTAG Wrapper for SoC Testing and Debugging. IEEE Access 10: 37603-37612 (2022)- [j42]Zhi-Wei Lai, Po-Hua Huang, Kuen-Jong Lee:
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function. J. Electron. Test. 38(5): 511-525 (2022) - [j41]Kuen-Jong Lee, Cheng-Hung Wu, Tsung-Yu Hou:
An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 737-749 (2022) - [j40]Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski:
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2323-2336 (2022) - [j39]Kuen-Jong Lee, Ching-An Liu, Chia-Chi Wu:
A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing. IEEE Trans. Emerg. Top. Comput. 10(1): 373-385 (2022) - [c86]Shih-Chun Yeh, Kuen-Jong Lee, Dong-Yi Chen:
An Authentication-Based Secure IJTAG Network. ATS 2022: 25-30 - [c85]Yan-Fu Chen, Duo-Yao Kang, Kuen-Jong Lee:
Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks. ITC 2022: 82-91 - [c84]Duo-Yao Kang, Shiou-Ning Lin, Kuen-Jong Lee:
Diagnosing Transition Delay Faults under Scan-Based Logic Array. ITC-Asia 2022: 13-18 - [c83]Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy:
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS 2022: 1-7 - 2021
- [j38]Yu-Hsiang Chen, Chia-Ming Hsu, Kuen-Jong Lee:
Test Chips With Scan-Based Logic Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 790-802 (2021) - [c82]Hung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao:
Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors. ATS 2021: 13-18 - 2020
- [j37]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1340-1345 (2020) - [c81]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski:
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS 2020: 1-2 - [c80]Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada:
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC 2020: 1-10 - [c79]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng:
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia 2020: 130-135
2010 – 2019
- 2019
- [j36]Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte:
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 309-321 (2019) - [j35]Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2105-2118 (2019) - [c78]Zhi-Wei Lai, Kuen-Jong Lee:
Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM. APCCAS 2019: 41-44 - [c77]Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye:
Deep Learning Based Test Compression Analyzer. ATS 2019: 1-6 - [c76]Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian:
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC 2019: 1-4 - [c75]Man-Hsuan Kuo, Chun-Ming Hu, Kuen-Jong Lee:
Time-Related Hardware Trojan Attacks on Processor Cores. ITC-Asia 2019: 43-48 - [c74]Chao-Jun Shang, Cheng-Hung Wu, Kuen-Jong Lee, Yu-Hsiang Chen:
A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model. VLSI-DAT 2019: 1-4 - 2018
- [j34]Chun-Wei Wu, Kuen-Jong Lee, Alan P. Su:
A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip. IEEE Trans. Computers 67(9): 1231-1245 (2018) - [j33]Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy:
A Repair-for-Diagnosis Methodology for Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2254-2267 (2018) - [c73]Chia-Chi Wu, Man-Hsuan Kuo, Kuen-Jong Lee:
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks. ATS 2018: 48-53 - [c72]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. ITC 2018: 1-10 - [c71]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. ITC-Asia 2018: 1-6 - 2017
- [j32]Jhen-Zong Chen, Kuen-Jong Lee:
Test Stimulus Compression Based on Broadcast Scan With One Single Input. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 184-197 (2017) - [j31]Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee:
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 1004-1017 (2017) - [c70]Chang-Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee:
Test Compression with Single-Input Data Spreader and Multiple Test Sessions. ATS 2017: 28-33 - [c69]Shuo-Lian Hong, Kuen-Jong Lee:
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. ITC 2017: 1-10 - [c68]Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
Test generation for open and delay faults in CMOS circuits. ITC-Asia 2017: 21-26 - [c67]Shuo-Lian Hong, Kuen-Jong Lee:
A run-pause-resume silicon debug technique for multiple clock domain systems. ITC-Asia 2017: 46-51 - [c66]Hsin-Pang Kuo, Alan P. Su, Kuen-Jong Lee:
A low power synthesis flow for multi-rate systems. VLSI-DAT 2017: 1-4 - 2016
- [c65]Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin:
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC 2016: 17-18 - [c64]Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee:
Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults. ASP-DAC 2016: 755-760 - [c63]Sheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee:
Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis. ATS 2016: 25-30 - [c62]Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich:
Autonomous Testing for 3D-ICs with IEEE Std. 1687. ATS 2016: 215-220 - [c61]Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte:
An on-chip self-test architecture with test patterns recorded in scan chains. ITC 2016: 1-10 - [c60]Wei-Cheng Lien, Kuen-Jong Lee:
Output bit selection methodology for test response compaction. ITC 2016: 1-10 - [c59]Cheng-Hung Wu, Kuen-Jong Lee:
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement. ITC 2016: 1-10 - 2015
- [c58]Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee:
Distinguishing dynamic bridging faults and transition delay faults. ASICON 2015: 1-4 - [c57]Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu:
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. ASP-DAC 2015: 520-525 - [c56]Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee:
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. DATE 2015: 1281-1284 - [c55]Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee:
Improve transition fault diagnosability via observation point insertion. VLSI-DAT 2015: 1-4 - 2014
- [j30]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty:
Efficient LFSR Reseeding Based on Internal-Response Feedback. J. Electron. Test. 30(6): 673-685 (2014) - [j29]Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee:
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 127-138 (2014) - [j28]Chin-Yao Chang, Kuen-Jong Lee:
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 484-496 (2014) - [c54]Cheng-Hung Wu, Kuen-Jong Lee:
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults. ATS 2014: 306-311 - [c53]Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh:
Output-bit selection with X-avoidance using multiple counters for test-response compaction. ETS 2014: 1-6 - [c52]Kuen-Jong Lee, Cheng-Hung Wu:
An efficient diagnosis-aware pattern generation procedure for transition faults. ITC 2014: 1-10 - [c51]Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh:
Output selection for test response compaction based on multiple counters. VLSI-DAT 2014: 1-4 - [c50]Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien:
An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. VTS 2014: 1-6 - 2013
- [j27]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu:
Counter-Based Output Selection for Test Response Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 152-164 (2013) - [j26]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Wee-Lung Ang:
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1254-1264 (2013) - [c49]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty:
A New LFSR Reseeding Scheme via Internal Response Feedback. Asian Test Symposium 2013: 97-102 - [c48]Kuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang:
An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip. VLSI-DAT 2013: 1-4 - 2012
- [j25]Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 754-764 (2012) - [c47]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh:
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. Asian Test Symposium 2012: 278-283 - [c46]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty:
Accumulator-based output selection for test response compaction. ISCAS 2012: 2313-2316 - [c45]Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee:
Routing-efficient implementation of an internal-response-based BIST architecture. VLSI-DAT 2012: 1-4 - 2011
- [j24]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 930-934 (2011) - [j23]Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh:
Test Response Compaction via Output Bit Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(10): 1534-1544 (2011) - [j22]Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Kuen-Jong Lee, Chin-Long Wey:
Programmable System-on-Chip for Silicon Prototyping. IEEE Trans. Ind. Electron. 58(3): 830-838 (2011) - [j21]Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 516-520 (2011) - [c44]Kuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu:
A software/hardware co-debug platform for multi-core systems. ASICON 2011: 259-262 - [c43]Kuen-Jong Lee, Chin-Yao Chang, I-Jou Chen:
EPIDETOX: an ESL platform for integrated circuit design and tool exploration. CODES+ISSS 2011: 381-384 - 2010
- [j20]Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang:
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1134-1139 (2010) - [c42]Wei-Cheng Lien, Kuen-Jong Lee:
A Complete Logic BIST Technology with No Storage Requirement. Asian Test Symposium 2010: 129-134
2000 – 2009
- 2009
- [j19]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. 26(1): 26-35 (2009) - [c41]Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao:
Full System Simulation and Verification Framework. IAS 2009: 165-168 - [c40]Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su:
Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. Asian Test Symposium 2009: 200-205 - [c39]Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee:
Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10 - [c38]Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su:
A low-cost SOC debug platform based on on-chip test architectures. SoCC 2009: 161-164 - 2008
- [j18]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. 57(1): 204-214 (2008) - [c37]Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen:
A Software-Based Test Methodology for Direct-Mapped Data Cache. ATS 2008: 363-368 - [c36]Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
A hybrid self-testing methodology of processor cores. ISCAS 2008: 3378-3381 - [c35]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9 - [c34]Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee:
A hybrid software-based self-testing methodology for embedded processor. SAC 2008: 1528-1534 - 2007
- [c33]Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You:
Test Efficiency Analysis and Improvement of SOC Test Platforms. ATS 2007: 463-466 - [c32]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE 2007: 1599-1604 - 2006
- [c31]Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou:
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC 2006: 137-140 - [c30]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS 2006: 130-135 - 2005
- [c29]Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong:
An embedded processor based SOC test platform. ISCAS (3) 2005: 2983-2986 - [c28]Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
A novel test methodology based on error-rate to support error-tolerance. ITC 2005: 9 - [c27]Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee:
A high speed BIST architecture for DDR-SDRAM testing. MTDT 2005: 52-57 - [c26]Wei-Lun Wang, Kuen-Jong Lee:
A complete memory address generator for scan based March algorithms. MTDT 2005: 83-88 - 2004
- [c25]Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho:
Test Power Reduction with Multiple Capture Orders. Asian Test Symposium 2004: 26-31 - [c24]Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang:
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Asian Test Symposium 2004: 296-301 - 2003
- [j17]Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee:
Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 363-370 (2003) - [c23]Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng:
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Asian Test Symposium 2003: 124-129 - 2002
- [j16]Kuen-Jong Lee, Chau-Chin Su:
Guest Editorial. J. Electron. Test. 18(1): 15-16 (2002) - [j15]Wei-Lun Wang, Kuen-Jong Lee:
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. J. Electron. Test. 18(1): 43-53 (2002) - [j14]Kuen-Jong Lee, Tsung-Chu Huang:
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electron. Test. 18(6): 627-636 (2002) - [j13]Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee:
An efficient BIST method for distributed small buffers. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 512-515 (2002) - [c22]Kuen-Jong Lee, Jih-Jeen Chen:
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium 2002: 338- - 2001
- [j12]Yun-Che Wen, Kuen-Jong Lee:
Analysis and generation of control and observation structures foranalog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 165-171 (2001) - [j11]Tsung-Chu Huang, Kuen-Jong Lee:
Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7): 911-917 (2001) - [j10]Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang:
An on-chip march pattern generator for testing embedded memory cores. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 730-735 (2001) - [c21]Tsung-Chu Huang, Kuen-Jong Lee:
A Low-Power LFSR Architecture. Asian Test Symposium 2001: 470 - [c20]Tsung-Chu Huang, Kuen-Jong Lee:
A token scan architecture for low power testing. ITC 2001: 660-669 - 2000
- [c19]Kuen-Jong Lee, Cheng-I Huang:
A hierarchical test control architecture for core based design. Asian Test Symposium 2000: 248-253 - [c18]Wei-Lun Wang, Kuen-Jong Lee:
Accelerated test pattern generators for mixed-mode BIST environments. Asian Test Symposium 2000: 368-373 - [c17]Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen:
Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458 - [c16]Yun-Che Wen, Kuen-Jong Lee:
An on Chip ADC Test Structure. DATE 2000: 221-225
1990 – 1999
- 1999
- [j9]Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang:
Broadcasting test patterns to multiple circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1793-1802 (1999) - [j8]Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang:
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999) - [c15]Tsung-Chu Huang, Kuen-Jong Lee:
An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium 1999: 315-320 - [c14]Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee:
An Efficient BIST Method for Small Buffers. VTS 1999: 246-251 - 1998
- [j7]Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang:
A General Structure of Feedback Shift Registers for Built-In Self Test. J. Inf. Sci. Eng. 14(3): 645-667 (1998) - [j6]Kuen-Jong Lee, Cheng-Hsuing Kuo:
Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. J. Inf. Sci. Eng. 14(4): 863-890 (1998) - [j5]Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
A graph representation for programmable logic arrays to facilitate testing and logic design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1030-1043 (1998) - [c13]Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh:
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. Asian Test Symposium 1998: 113-118 - [c12]Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang:
Using a single input to support multiple scan chains. ICCAD 1998: 74-78 - 1997
- [c11]Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee:
Built-in current sensor designs based on the bulk-driven technique. Asian Test Symposium 1997: 384- - 1996
- [c10]Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium 1996: 100- - [c9]Kuen-Jong Lee, Jing-Jou Tang:
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. Asian Test Symposium 1996: 165-171 - 1995
- [j4]Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer:
An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1445-1458 (1995) - [j3]Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
A practical current sensing technique for IDDQ testing. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 302-310 (1995) - [c8]Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
Built-in intermediate voltage testing for CMOS circuits. ED&TC 1995: 372-377 - [c7]Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee:
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). ISCAS 1995: 393-396 - [c6]Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee:
A New Architecture for Analog Boundary Scan. ISCAS 1995: 409-412 - 1994
- [j2]Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 625-637 (1994) - 1992
- [j1]Kuen-Jong Lee, Melvin A. Breuer:
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 659-670 (1992) - [c5]Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29 - [c4]Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee:
A Fast Testing Method for Sequential Circuits at the State Trasition Level. ITC 1992: 514-519 - 1991
- [c3]Kuen-Jong Lee, Melvin A. Breuer:
Constraints for using IDDQ testing to detect CMOS bridging faults. VTS 1991: 303-308 - 1990
- [c2]Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer:
A New Method for Assigning Signal Flow Directions to MOS Transistors. ICCAD 1990: 492-495 - [c1]Kuen-Jong Lee, Melvin A. Breuer:
On the charge sharing problem in CMOS stuck-open fault testing. ITC 1990: 417-426
Coauthor Index
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to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 23:03 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
