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ORCIDSybille Hellebrand
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2020 – today
- 2024
[j21]Somayeh Sadeghi Kohan
, Sybille Hellebrand, Hans-Joachim Wunderlich:
Workload-Aware Periodic Interconnect BIST. IEEE Des. Test 41(4): 50-55 (2024)- [c57]Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. ETS 2024: 1-6 - [c56]Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Vmin Testing under Variations: Defect vs. Fault Coverage. LATS 2024: 1-6 - 2023
- [c55]Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Optimizing the Streaming of Sensor Data with Approximate Communication. ATS 2023: 1-6 - [c54]Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich:
Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. DSN-W 2023: 203-206 - [c53]Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand:
Approximate Communication: Balancing Performance, Power, Reliability, and Safety. ETS 2023: 1-6 - [c52]Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Robust Pattern Generation for Small Delay Faults Under Process Variations. ITC 2023: 111-116 - 2021
- [j20]Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich:
Stress-Aware Periodic Test of Interconnects. J. Electron. Test. 37(5): 715-728 (2021) - 2020
- [c51]Alexander Sprenger, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand:
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. DFT 2020: 1-6 - [c50]Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen:
Logic Fault Diagnosis of Hidden Delay Defects. ITC 2020: 1-10 - [c49]Somayeh Sadeghi Kohan, Sybille Hellebrand:
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. VTS 2020: 1-6
2010 – 2019
- 2019
- [j19]Alexander Sprenger, Sybille Hellebrand:
Divide and Compact - Stochastic Space Compaction for Faster-than-at-Speed Test. J. Circuits Syst. Comput. 28(Supplement-1): 1940001:1-1940001:23 (2019) - [j18]Matthias Kampmann, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, Hans-Joachim Wunderlich:
Built-In Test for Hidden Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1956-1968 (2019) - [c48]Mohammad Urf Maaz, Alexander Sprenger, Sybille Hellebrand:
A Hybrid Space Compactor for Adaptive X-Handling. ITC 2019: 1-8 - 2018
- [j17]Sybille Hellebrand, Jörg Henkel, Anand Raghunathan, Hans-Joachim Wunderlich:
Guest Editors' Introduction. IEEE Embed. Syst. Lett. 10(1): 1 (2018) - [j16]Matthias Kampmann, Sybille Hellebrand:
Design for Small Delay Test - A Simulation Study. Microelectron. Reliab. 80: 124-133 (2018) - [c47]Chang Liu, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, Hans-Joachim Wunderlich:
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. ATS 2018: 92-97 - [c46]Alexander Sprenger, Sybille Hellebrand:
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. DDECS 2018: 73-78 - 2017
- [c45]Matthias Kampmann, Sybille Hellebrand:
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. DDECS 2017: 35-41 - [c44]Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken:
Foreword. ETS 2017: 1-2 - [c43]Jyotirmoy V. Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand:
Special session on early life failures. VTS 2017: 1 - 2016
- [c42]Matthias Kampmann, Sybille Hellebrand:
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. ATS 2016: 1-6 - 2015
- [j15]Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand:
A High Performance SEU Tolerant Latch. J. Electron. Test. 31(4): 349-359 (2015) - [c41]Matthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Optimized Selection of Frequencies for Faster-Than-at-Speed Test. ATS 2015: 109-114 - 2014
- [j14]Laura Rodríguez Gómez, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Adaptive Bayesian Diagnosis of Intermittent Faults. J. Electron. Test. 30(5): 527-540 (2014) - [j13]Sybille Hellebrand, Hans-Joachim Wunderlich:
SAT-based ATPG beyond stuck-at fault testing. it Inf. Technol. 56(4): 165-172 (2014) - [c40]Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich:
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. ITC 2014: 1-8 - 2013
- [c39]Sybille Hellebrand:
Analyzing and quantifying fault tolerance properties. LATW 2013: 1 - 2012
- [c38]Alejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich:
Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. ETS 2012: 1-6 - [c37]Alejandro Cook, Sybille Hellebrand, Michael E. Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich:
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test. LATW 2012: 1-4 - 2011
- [j12]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich:
Variation-aware fault modeling. Sci. China Inf. Sci. 54(9): 1813-1826 (2011) - [c36]Alejandro Cook, Sybille Hellebrand, Thomas Indlekofer, Hans-Joachim Wunderlich:
Diagnostic Test of Robust Circuits. Asian Test Symposium 2011: 285-290 - [c35]Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell:
Towards Variation-Aware Test Methods. ETS 2011: 219-225 - 2010
- [j11]Sybille Hellebrand:
Nano-electronic Systems (Nano-elektronische Systeme). it Inf. Technol. 52(4): 179-180 (2010) - [c34]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich:
Variation-Aware Fault Modeling. Asian Test Symposium 2010: 87-93 - [c33]Marc Hunger, Sybille Hellebrand:
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. DFT 2010: 101-108 - [c32]Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich:
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. DSN Workshops 2010: 95-100 - [c31]Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand:
Efficient test response compaction for robust BIST using parity sequences. ICCD 2010: 480-485 - [c30]Viktor Froese, Rüdiger Ibers, Sybille Hellebrand:
Reusing NoC-infrastructure for test data compression. VTS 2010: 227-231
2000 – 2009
- 2009
- [c29]Sybille Hellebrand, Marc Hunger:
Are Robust Circuits Really Robust? DFT 2009: 77-77 - [c28]Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker:
ATPG-based grading of strong fault-secureness. IOLTS 2009: 269-274 - 2008
- [c27]Marc Hunger, Sybille Hellebrand:
Verification and Analysis of Self-Checking Properties through ATPG. IOLTS 2008: 25-30 - [c26]Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand:
A Modular Memory BIST for Optimized Memory Repair. IOLTS 2008: 171-172 - [c25]Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich:
Signature Rollback - A Technique for Testing Robust Circuits. VTS 2008: 125-130 - 2007
- [j10]Muhammad Ali, Michael Welzl, Sven Hessler, Sybille Hellebrand:
An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip. Int. J. High Perform. Syst. Archit. 1(2): 113-123 (2007) - [c24]Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. DDECS 2007: 185-190 - [c23]Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube:
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. DFT 2007: 50-58 - [c22]Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. ETS 2007: 91-96 - 2006
- [j9]Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich:
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). it Inf. Technol. 48(5): 304- (2006) - 2005
- [c21]Philipp Öhler, Sybille Hellebrand:
Low power embedded DRAMs with high quality error correcting capabilities. ETS 2005: 148-153 - 2004
- [c20]Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand:
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. ITC 2004: 926-935 - 2003
- [c19]Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand:
A Hybrid Coding Strategy For Optimized Test Data Compression. ITC 2003: 451-459 - 2002
- [j8]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. J. Electron. Test. 18(2): 159-170 (2002) - [j7]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
A Mixed-Mode BIST Scheme Based on Folding Compression. J. Comput. Sci. Technol. 17(2): 203-212 (2002) - [j6]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
Efficient Online and Offline Testing of Embedded DRAMs. IEEE Trans. Computers 51(7): 801-809 (2002) - 2001
- [j5]Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich:
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. J. Electron. Test. 17(3-4): 341-349 (2001) - [c18]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
Two-dimensional test data compression for scan-based deterministic BIST. ITC 2001: 894-902 - 2000
- [c17]Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang:
A mixed mode BIST scheme based on reseeding of folding counters. ITC 2000: 778-784
1990 – 1999
- 1999
- [c16]Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik:
Symmetric Transparent BIST for RAMs. DATE 1999: 702-707 - [c15]Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich:
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. EDCC 1999: 339-350 - [c14]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
Error Detecting Refreshment for Embedded DRAMs. VTS 1999: 384-390 - 1998
- [j4]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig:
Synthesizing Fast, Online-Testable Control Units. IEEE Des. Test Comput. 15(4): 36-41 (1998) - [j3]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig:
Mixed-Mode BIST Using Embedded Processors. J. Electron. Test. 12(1-2): 127-138 (1998) - [c13]Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich:
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. DATE 1998: 173-179 - [c12]Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich:
Fast Self-Recovering Controllers. VTS 1998: 296-302 - 1997
- [c11]Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477 - 1996
- [c10]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig:
Mixed-Mode BIST Using Embedded Processors. ITC 1996: 195-204 - 1995
- [j2]Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois:
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. Computers 44(2): 223-233 (1995) - [c9]Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich:
Pattern generation for a deterministic BIST scheme. ICCAD 1995: 88-94 - 1994
- [c8]Sybille Hellebrand, Hans-Joachim Wunderlich:
Synthesis of Self-Testable Controllers. EDAC-ETC-EUROASIC 1994: 580-585 - [c7]Sybille Hellebrand, Hans-Joachim Wunderlich:
An efficient procedure for the synthesis of fast self-testable controller structures. ICCAD 1994: 110-116 - 1992
- [j1]Hans-Joachim Wunderlich, Sybille Hellebrand:
The pseudoexhaustive test of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1): 26-33 (1992) - [c6]Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski:
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. ITC 1992: 120-129 - 1991
- [b1]Sybille Hellebrand:
Synthese vollstaendig testbarer Schaltungen. Karlsruhe University, Germany, 1991 - 1990
- [c5]Sybille Hellebrand, Hans-Joachim Wunderlich:
Tools and devices supporting the pseudo-exhaustive test. EURO-DAC 1990: 13-17 - [c4]Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl:
Generating pseudo-exhaustive vectors for external testing. ITC 1990: 670-679
1980 – 1989
- 1989
- [c3]Sybille Hellebrand, Hans-Joachim Wunderlich:
The Pseudo-Exhaustive Test of Sequential Circuits. ITC 1989: 19-27 - 1988
- [c2]Hans-Joachim Wunderlich, Sybille Hellebrand:
Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits. FTCS 1988: 36-41 - [c1]Sybille Hellebrand, Hans-Joachim Wunderlich:
Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI Jahrestagung (2) 1988: 145-159
Coauthor Index
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last updated on 2024-07-20 21:18 CEST by the dblp team
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