lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
RISC-V Debug Support for our PULP RISC-V Cores
Common SystemVerilog components
HW Design Collateral for Caliptra RoT IP