Zero-Drift, Single-Supply, Rail-to-Rail

Input/Output Operational Amplifiers

Data Sheet
AD8551/AD8552/AD8554


Rev. E Document Feedback
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FEATURES
Low offset voltage: 1 V
Input offset drift: 0.005 V/C
Rail-to-rail input and output swing
5 V/2.7 V single-supply operation
High gain, CMRR, PSRR: 130 dB
Ultralow input bias current: 20 pA
Low supply current: 700 A/op amp
Overload recovery time: 50 s
No external capacitors required
APPLICATIONS
Temperature sensors
Pressure sensors
Precision current sensing
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
GENERAL DESCRIPTION
This family of amplifiers has ultralow offset, drift, and bias
current. The AD8551, AD8552, and AD8554 are single, dual,
and quad amplifiers featuring rail-to-rail input and output swings.
All are guaranteed to operate from 2.7 V to 5 V with a single supply.
The AD855x family provides the benefits previously found only
in expensive auto-zeroing or chopper-stabilized amplifiers.
Using Analog Devices, Inc. topology, these new zero-drift
amplifiers combine low cost with high accuracy. No external
capacitors are required.
With an offset voltage of only 1 V and drift of 0.005 V/C, the
AD855x are perfectly suited for applications in which error
sources cannot be tolerated. Temperature, position and pressure
sensors, medical equipment, and strain gage amplifiers benefit
greatly from nearly zero drift over their operating temperature
range. The rail-to-rail input and output swings provided by the
AD855x family make both high-side and low-side sensing easy.
The AD855x family is specified for the extended industrial/auto
motive temperature range (40C to +125C). The AD8551
single amplifier is available in 8-lead MSOP and 8-lead narrow
SOIC packages. The AD8552 dual amplifier is available in 8-lead
narrow SOIC and 8-lead TSSOP surface-mount packages. The
AD8554 quad is available in 14-lead narrow SOIC and 14-lead
TSSOP packages.
PIN CONFIGURATIONS
IN A
+IN A
V
V+
OUT A
NC
NC
NC = NO CONNECT
NC 1 8
AD8551
4 5
0
1
1
0
1
-
0
0
1

Figure 1. 8-Lead MSOP (RM Suffix)
IN A
V
+IN A
V+
OUT A
NC
NC
NC
NC = NO CONNECT
AD8551
1
2
3
4
8
7
6
5
0
1
1
0
1
-
0
0
2

Figure 2. 8-Lead SOIC (R Suffix)
IN A
+IN A
V
OUT B
IN B
+IN B
OUT A V+ 1 8
AD8552
4 5
0
1
1
0
1
-
0
0
3

Figure 3. 8-Lead TSSOP (RU Suffix)
IN A
V
+IN A
OUT B
IN B
V+
+IN B
OUT A
AD8552
1
2
3
4
8
7
6
5
0
1
1
0
1
-
0
0
4

Figure 4. 8-Lead SOIC (R Suffix)
OUT A
IN A
+IN A
V+
IN D
+IN D
V
OUT D
+IN B
IN B
OUT B
IN C
OUT C
+IN C
AD8554
1 14
7 8
0
1
1
0
1
-
0
0
5

Figure 5. 14-Lead TSSOP (RU Suffix)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN A
+IN A
V+
+IN B
IN B
OUT B
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
OUT A
AD8554
0
1
1
0
1
-
0
0
6

Figure 6. 14-Lead SOIC (R Suffix)


AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description .................................................................. 14
Amplifier Architecture .............................................................. 14
Basic Auto-Zero Amplifier Theory .......................................... 14
High Gain, CMRR, PSRR .......................................................... 16
Maximizing Performance Through Proper Layout ............... 16
1/f Noise Characteristics ........................................................... 17
Intermodulation Distortion ...................................................... 17
Broadband and External Resistor Noise Considerations ...... 18
Output Overdrive Recovery ...................................................... 18
Input Overvoltage Protection ................................................... 18
Output Phase Reversal ............................................................... 19
Capacitive Load Drive ............................................................... 19
Power-Up Behavior .................................................................... 19
Applications Information .............................................................. 20
A 5 V Precision Strain Gage Circuit ........................................ 20
3 V Instrumentation Amplifier ................................................ 20
A High Accuracy Thermocouple Amplifier ........................... 21
Precision Current Meter ............................................................ 21
Precision Voltage Comparator .................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 24

REVISION HISTORY
11/12Rev.D to Rev. E
Changes to Figure 68 ...................................................................... 21
Updated Outline Dimensions (RM-8) ......................................... 22
Changes to Ordering Guide .......................................................... 24

9/08Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 23

3/07Rev. B to Rev. C
Changes to Specifications Section .................................................. 3

2/07Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Figure 54 ...................................................................... 16
Deleted Spice Model Section ........................................................ 19
Deleted Figure 63, Renumbered Sequentially ............................ 19
Changes to Ordering Guide .......................................................... 24

11/02Rev. 0 to Rev. A
Edits to Figure 60 ............................................................................ 16
Updated Outline Dimensions ....................................................... 20

Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
S
= 5 V, V
CM
= 2.5 V, V
O
= 2.5 V, T
A
= 25C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
1 5 V
40C T
A
+125C 10 V
Input Bias Current I
B
10 50 pA
AD8551/AD8554 40C T
A
+125C 1.0 1.5 nA
AD8552 40C T
A
+85C 160 300 pA
AD8552 40C T
A
+125C 2.5 4 nA
Input Offset Current I
OS
20 70 pA
AD8551/AD8554 40C T
A
+125C 150 200 pA
AD8552 40C T
A
+85C 30 150 pA
AD8552 40C T
A
+125C 150 400 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR V
CM
= 0 V to +5 V 120 140 dB
40C T
A
+125C 115 130 dB
Large Signal Voltage Gain
1
A
VO
R
L
= 10 k, V
O
= 0.3 V to 4.7 V 125 145 dB
40C T
A
+125C 120 135 dB
Offset Voltage Drift V
OS
/T 40C T
A
+125C 0.005 0.04 V/C
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
R
L
= 100 k to GND 4.99 4.998 V
R
L
= 100 k to GND @ 40C to +125C 4.99 4.997 V
R
L
= 10 k to GND 4.95 4.98 V
R
L
= 10 k to GND @ 40C to +125C 4.95 4.975 V
Output Voltage Low V
OL
R
L
= 100 k to V+ 1 10 mV
R
L
= 100 k to V+ @ 40C to +125C 2 10 mV
R
L
= 10 k to V+ 10 30 mV
R
L
= 10 k to V+ @ 40C to +125C 15 30 mV
Output Short-Circuit Limit Current I
SC
25 50 mA
40C to +125C 40 mA
Output Current I
O
30 mA
40C to +125C 15 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
S
= 2.7 V to 5.5 V 120 130 dB
40C T
A
+125C 115 130 dB
Supply Current/Amplifier I
SY
V
O
= 0 V 850 975 A
40C T
A
+125C 1000 1075 A
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 k 0.4 V/s
Overload Recovery Time 0.05 0.3 ms
Gain Bandwidth Product GBP 1.5 MHz
NOISE PERFORMANCE
Voltage Noise e
n
p-p 0 Hz to 10 Hz 1.0 V p-p
e
n
p-p 0 Hz to 1 Hz 0.32 V p-p
Voltage Noise Density e
n
f = 1 kHz 42 nV/Hz
Current Noise Density i
n
f = 10 Hz 2 fA/Hz

1
Gain testing is dependent upon test bandwidth.

AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 4 of 24
V
S
= 2.7 V, V
CM
= 1.35 V, V
O
= 1.35 V, T
A
= 25C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
1 5 V
40C T
A
+125C 10 V
Input Bias Current I
B
10 50 pA
AD8551/AD8554 40C T
A
+125C 1.0 1.5 nA
AD8552 40C T
A
+85C 160 300 pA
AD8552 40C T
A
+125C 2.5 4 nA
Input Offset Current I
OS
10 50 pA
AD8551/AD8554 40C T
A
+125C 150 200 pA
AD8552 40C T
A
+85C 30 150 pA
AD8552 40C T
A
+125C 150 400 pA
Input Voltage Range 0 2.7 V
Common-Mode Rejection Ratio CMRR V
CM
= 0 V to 2.7 V 115 130 dB
40C T
A
+125C 110 130 dB
Large Signal Voltage Gain
1
A
VO
R
L
= 10 k, V
O
= 0.3 V to 2.4 V 110 140 dB
40C T
A
+125C 105 130 dB
Offset Voltage Drift V
OS
/T 40C T
A
+125C 0.005 0.04 V/C
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
R
L
= 100 k to GND 2.685 2.697 V
R
L
= 100 k to GND @ 40C to +125C 2.685 2.696 V
R
L
= 10 k to GND 2.67 2.68 V
R
L
= 10 k to GND @ 40C to +125C 2.67 2.675 V
Output Voltage Low V
OL
R
L
= 100 k to V+ 1 10 mV
R
L
= 100 k to V+ @ 40C to +125C 2 10 mV
R
L
= 10 k to V+ 10 20 mV
R
L
= 10 k to V+ @ 40C to +125C 15 20 mV
Short-Circuit Limit I
SC
10 15 mA
40C to +125C 10 mA
Output Current I
O
10 mA
40C to +125C 5 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
S
= 2.7 V to 5.5 V 120 130 dB
40C T
A
+125C 115 130 dB
Supply Current/Amplifier I
SY
V
O
= 0 V 750 900 A
40C T
A
+125C 950 1000 A
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 k 0.5 V/s
Overload Recovery Time 0.05 ms
Gain Bandwidth Product GBP 1 MHz
NOISE PERFORMANCE
Voltage Noise e
n
p-p 0 Hz to 10 Hz 1.6 V p-p
Voltage Noise Density e
n
f = 1 kHz 75 nV/Hz
Current Noise Density i
n
f = 10 Hz 2 fA/Hz

1
Gain testing is dependent upon test bandwidth.

Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 6 V
Input Voltage GND to V
S
+ 0.3 V
Differential Input Voltage
1
5.0 V
ESD (Human Body Model) 2000 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range 65C to +150C
Operating Temperature Range 40C to +125C
Junction Temperature Range 65C to +150C
Lead Temperature Range (Soldering, 60 sec) 300C

1
Differential input voltage is limited to 5.0 V or the supply voltage,
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS
Table 4.
Package Type
JA

JC
Unit
8-Lead MSOP (RM) 190 44 C/W
8-Lead TSSOP (RU) 240 43 C/W
8-Lead SOIC (R) 158 43 C/W
14-Lead TSSOP (RU) 180 36 C/W
14-Lead SOIC (R) 120 36 C/W
ESD CAUTION




AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE (V)
N
U
M
B
E
R

O
F

A
M
P
L
I
F
I
E
R
S
180
0
2.5 0.5
120
100
60
20
2.5
40
80
140
160
1.5 0.5 1.5
V
SY
= 2.7V
V
CM
= 1.35V
T
A
= 25C
0
1
1
0
1
-
0
0
7

Figure 7. Input Offset Voltage Distribution at 2.7 V
INPUT COMMON-MODE VOLTAGE (V)
I
N
P
U
T

B
I
A
S

C
U
R
R
E
N
T

(
p
A
)
50
30
5
40
30
20
10
20
10
0
V
SY
= 5V
T
A
= 40C, +25C, +85C
+85C
+25C
40C
0 1 2 3 4
0
1
1
0
1
-
0
0
8

Figure 8. Input Bias Current vs. Common-Mode Voltage
INPUT COMMON-MODE VOLTAGE (V)
I
N
P
U
T

B
I
A
S

C
U
R
R
E
N
T

(
p
A
)
1500
2000
1000
500
0
1000
1500
500
0 1 2 3 4 5
V
SY
= 5V
T
A
= 125C
0
1
1
0
1
-
0
0
9

Figure 9. Input Bias Current vs. Common-Mode Voltage
N
U
M
B
E
R

O
F

A
M
P
L
I
F
I
E
R
S
180
0
120
100
60
20
40
80
140
160
2.5 1.5 0.5 1.5
OFFSET VOLTAGE (V)
0.5 2.5
V
SY
= 5V
V
CM
= 2.5V
T
A
= 25C
0
1
1
0
1
-
0
1
0

Figure 10. Input Offset Voltage Distribution at 5 V
N
U
M
B
E
R

O
F

A
M
P
L
I
F
I
E
R
S
12
0
10
8
4
2
6
INPUT OFFSET DRIFT (nV/C)
0 1 2 3 4 5 6
V
SY
= 5V
V
CM
= 2.5V
T
A
= 40C TO +125C
0
1
1
0
1
-
0
1
1

Figure 11. Input Offset Voltage Drift Distribution at 5 V
LOAD CURRENT (mA)
10
0.1
O
U
T
P
U
T

V
O
L
T
A
G
E

(
m
V
)
1
100
10k
1k
0.0001 0.001 0.01 0.1 1 10 100
V
SY
= 5V
T
A
= 25C
SOURCE
SINK
0
1
1
0
1
-
0
1
2

Figure 12. Output Voltage to Supply Rail vs. Load Current at 5 V
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 7 of 24
LOAD CURRENT (mA)
10
0.1
O
U
T
P
U
T

V
O
L
T
A
G
E

(
m
V
)
1
100
10k
1k
0.0001 0.001 0.01 0.1 1 10 100
V
SY
= 2.7V
T
A
= 25C
SOURCE
SINK
0
1
1
0
1
-
0
1
3

Figure 13. Output Voltage to Supply Rail vs. Load Current at 2.7 V
I
N
P
U
T

B
I
A
S

C
U
R
R
E
N
T

(
p
A
)
0
1000
75 50 125 25 100
250
500
750
150
V
CM
= 2.5V
V
SY
= 5V
TEMPERATURE (C)
0 25 50 75
0
1
1
0
1
-
0
1
4

Figure 14. Input Bias Current vs. Temperature

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
1.0
0
75 50 125 25 100 150
TEMPERATURE (C)
0 25 50 75
0.8
0.6
0.4
0.2
V
CM
= 2.5V
V
SY
= 5V
5V
2.7V
0
1
1
0
1
-
0
1
5

Figure 15. Supply Current vs. Temperature
SUPPLY VOLTAGE (V)
S
U
P
P
L
Y

C
U
R
R
E
N
T

P
E
R

A
M
P
L
I
F
I
E
R

(

A
)
800
0
700
400
300
200
100
600
500
0 6 1
T
A
= +25C
2 3 4 5
0
1
1
0
1
-
0
1
6

Figure 16. Supply Current per Amplifier vs. Supply Voltage
FREQUENCY (Hz)
O
P
E
N
-
L
O
O
P

G
A
I
N

(
d
B
)
60
50
40
40
30
20
10
0
10
20
30
45
90
135
180
225
270
0
P
H
A
S
E

S
H
I
F
T

(
D
e
g
r
e
e
s
)
V
SY
= 2.7V
C
L
= 0pF
R
L
=
10k 100k 1M 10M 100M
0
1
1
0
1
-
0
1
7

Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V
FREQUENCY (Hz)
O
P
E
N
-
L
O
O
P

G
A
I
N

(
d
B
)
60
50
40
40
30
20
10
0
10
20
30
45
90
135
180
225
270
0
P
H
A
S
E

S
H
I
F
T

(
D
e
g
r
e
e
s
)
V
SY
= 5V
C
L
= 0pF
R
L
=
10k 100k 1M 10M 100M
0
1
1
0
1
-
0
1
8

Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 V
AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 8 of 24
C
L
O
S
E
D
-
L
O
O
P

G
A
I
N

(
d
B
)
FREQUENCY (Hz)
60
50
40
40
30
20
10
0
10
20
30
10k 100k 1M 10M 100
V
SY
= 2.7V
C
L
= 0pF
R
L
= 2k
A
V
= 100
A
V
= 10
A
V
= +1
1k
0
1
1
0
1
-
0
1
9

Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V
C
L
O
S
E
D
-
L
O
O
P

G
A
I
N

(
d
B
)
FREQUENCY (Hz)
60
50
40
40
30
20
10
0
10
20
30
10k 100k 1M 10M 100
V
SY
= 5V
C
L
= 0pF
R
L
= 2k
A
V
= 100
A
V
= 10
A
V
= +1
1k
0
1
1
0
1
-
0
2
0

Figure 20. Closed-Loop Gain vs. Frequency at 5 V
O
U
T
P
U
T

I
M
P
E
D
A
N
C
E

(

)
300
270
0
240
210
180
150
120
90
60
30
FREQUENCY (Hz)
10k 100k 1M 10M 100 1k
V
SY
= 2.7V
A
V
= 100
A
V
= 10
A
V
= 1
0
1
1
0
1
-
0
2
1

Figure 21. Output Impedance vs. Frequency at 2.7 V
O
U
T
P
U
T

I
M
P
E
D
A
N
C
E

(

)
300
270
0
240
210
180
150
120
90
60
30
FREQUENCY (Hz)
10k 100k 1M 10M 100 1k
V
SY
= 5V
A
V
= 100
A
V
= 10
A
V
= 1
0
1
1
0
1
-
0
2
2

Figure 22. Output Impedance vs. Frequency at 5 V
2s
V
SY
= 2.7V
C
L
= 300pF
R
L
= 2k
A
V
= 1
500mV
0
1
1
0
1
-
0
2
3

Figure 23. Large Signal Transient Response at 2.7 V
5s
V
SY
= 5V
C
L
= 300pF
R
L
= 2k
A
V
= 1
1V
0
1
1
0
1
-
0
2
4

Figure 24. Large Signal Transient Response at 5 V
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 9 of 24
5s
V
SY
= 1.35V
C
L
= 50pF
R
L
=
A
V
= 1
50mV
0
1
1
0
1
-
0
2
5

Figure 25. Small Signal Transient Response at 2.7 V
5s
V
SY
= 2.5V
C
L
= 50pF
R
L
=
A
V
= 1
50mV
0
1
1
0
1
-
0
2
6

Figure 26. Small Signal Transient Response at 5 V
CAPACITANCE (pF)
S
M
A
L
L

S
I
G
N
A
L

O
V
E
R
S
H
O
O
T

(
%
)
50
45
0
40
35
30
25
20
15
10
5
+OS
OS
10 100 1k 10k
V
SY
= 1.35V
R
L
= 2k
T
A
= 25C
0
1
1
0
1
-
0
2
7

Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V
CAPACITANCE (pF)
S
M
A
L
L

S
I
G
N
A
L

O
V
E
R
S
H
O
O
T

(
%
)
45
0
40
35
30
25
20
15
10
5
10 100 1k 10k
V
SY
= 2.5V
R
L
= 2k
T
A
= 25C
OS
+OS
0
1
1
0
1
-
0
2
8

Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V
20s
V
SY
= 2.5V
V
IN
= 200mV p-p
(RET TO GND)
C
L
= 0pF
R
L
= 10k
A
V
= 100
1V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
0V
V
IN
V
OUT
0V
0
1
1
0
1
-
0
2
9

Figure 29. Positive Overvoltage Recovery
20s
V
SY
= 2.5V
V
IN
= 200mV p-p
(RET TO GND)
C
L
= 0pF
R
L
= 10k
A
V
= 100
1V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
0V
V
IN
V
OUT
0V
0
1
1
0
1
-
0
3
0

Figure 30. Negative Overvoltage Recovery
AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 10 of 24
200s 1V
V
S
= 2.5V
R
L
= 2k
A
V
= 100
V
IN
= 60mV p-p
0
1
1
0
1
-
0
3
1

Figure 31. No Phase Reversal
FREQUENCY (Hz)
C
M
R
R

(
d
B
)
140
80
0
60
120
20
40
100
10k 100k 1M 10M 100 1k
V
SY
= 2.7V
0
1
1
0
1
-
0
3
2

Figure 32. CMRR vs. Frequency at 2.7 V
FREQUENCY (Hz)
C
M
R
R

(
d
B
)
140
80
0
60
120
20
40
100
10k 100k 1M 10M 100 1k
V
SY
= 5V
0
1
1
0
1
-
0
3
3

Figure 33. CMRR vs. Frequency at 5 V
FREQUENCY (Hz)
P
S
R
R

(
d
B
)
140
80
0
60
120
20
40
100
10k 100k 1M 10M 100 1k
V
SY
= 1.35V
PSRR
+PSRR
0
1
1
0
1
-
0
3
4

Figure 34. PSRR vs. Frequency at 1.35 V
FREQUENCY (Hz)
P
S
R
R

(
d
B
)
140
80
0
60
120
20
40
100
10k 100k 1M 10M 100 1k
V
SY
= 2.5V
PSRR
+PSRR
0
1
1
0
1
-
0
3
5

Figure 35. PSRR vs. Frequency at 2.5 V
O
U
T
P
U
T

S
W
I
N
G

(
V

p
-
p
)
3.0
2.5
0
2.0
1.5
0.5
1.0
V
SY
= 1.35V
R
L
= 2k
A
V
= 1
THD+N < 1%
T
A
= 25C
FREQUENCY (Hz)
10k 100k 1M 100 1k
0
1
1
0
1
-
0
3
6

Figure 36. Maximum Output Swing vs. Frequency at 2.7 V
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 11 of 24
3.0
2.5
2.0
1.5
0.5
1.0
3.5
4.0
4.5
5.0
5.5
0
O
U
T
P
U
T

S
W
I
N
G

(
V

p
-
p
)
FREQUENCY (Hz)
10k 100k 1M 100 1k
V
SY
= 2.5V
R
L
= 2k
A
V
= 1
THD+N < 1%
T
A
= 25C
0
1
1
0
1
-
0
3
7

Figure 37. Maximum Output Swing vs. Frequency at 5 V
0V
1s 2mV
V
SY
= 1.35V
A
V
= 10000
0
1
1
0
1
-
0
3
8

Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V
1s 2mV
V
SY
= 2.5V
A
V
= 10000
0
1
1
0
1
-
0
3
9

Figure 39. 0.1 Hz to 10 Hz Noise at 5 V
0.5
FREQUENCY (kHz)
0
52
78
104
130
156
182
26
V
SY
= 2.7V
R
S
= 0
e
n

(
n
V
/

H
z
)
1.0 1.5 2.0 2.5
0
1
1
0
1
-
0
4
0

Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz
5
FREQUENCY (kHz)
0
32
48
64
80
96
112
16
V
SY
= 2.7V
R
S
= 0
e
n

(
n
V
/

H
z
)
10 15 20 25
0
1
1
0
1
-
0
4
1

Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz
0.5
FREQUENCY (kHz)
0
26
39
52
65
78
91
13
V
SY
= 5V
R
S
= 0
e
n

(
n
V
/

H
z
)
1.0 1.5 2.0 2.5
0
1
1
0
1
-
0
4
2

Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz
AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 12 of 24
5
FREQUENCY (kHz)
0
32
48
64
80
96
112
16
V
SY
= 5V
R
S
= 0
e
n

(
n
V
/

H
z
)
10 15 20 25
0
1
1
0
1
-
0
4
3

Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz
FREQUENCY (Hz)
0
48
72
96
120
144
168
24
V
SY
= 5V
R
S
= 0
e
n

(
n
V
/

H
z
)
5 10
0
1
1
0
1
-
0
4
4

Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz
TEMPERATURE (C)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N

(
d
B
)
150
145
125
140
135
130
75 50 25 0 25 50 75 100 125 150
V
SY
= 2.7V TO 5.5V
0
1
1
0
1
-
0
4
5

Figure 45. Power Supply Rejection vs. Temperature
10
50
30
50
10
40
30
20
0
20
40
TEMPERATURE (C)
S
H
O
R
T
-
C
I
R
C
U
I
T

C
U
R
R
E
N
T

(
m
A
)
75 50 25 0 25 50 75 100 125 150
V
SY
= 2.7V
I
SC
I
SC+
0
1
1
0
1
-
0
4
6

Figure 46. Output Short-Circuit Current vs. Temperature
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 13 of 24
20
100
60
100
20
80
60
40
0
40
80
TEMPERATURE (C)
S
H
O
R
T
-
C
I
R
C
U
I
T

C
U
R
R
E
N
T

(
m
A
)
75 50 25 0 25 50 75 100 125 150
V
SY
= 5.0V
I
SC
I
SC+
0
1
1
0
1
-
0
4
7

Figure 47. Output Short-Circuit Current vs. Temperature
100
250
200
0
150
25
50
75
125
175
225
TEMPERATURE (C)
O
U
T
P
U
T

V
O
L
T
A
G
E

T
O

S
U
P
P
L
Y

R
A
I
L

(
m
V
)
75 50 25 0 25 50 75 100 125 150
V
SY
= 2.7V
R
L
= 1k
R
L
= 100k
R
L
= 10k
0
1
1
0
1
-
0
4
8

Figure 48. Output Voltage to Supply Rail vs. Temperature
100
250
200
0
150
25
50
75
125
175
225
TEMPERATURE (C)
O
U
T
P
U
T

V
O
L
T
A
G
E

T
O

S
U
P
P
L
Y

R
A
I
L

(
m
V
)
75 50 25 0 25 50 75 100 125 150
V
SY
= 5.0V
R
L
= 1k
R
L
= 100k
R
L
= 10k
0
1
1
0
1
-
0
4
9

Figure 49. Output Voltage to Supply Rail vs. Temperature


AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 14 of 24
FUNCTIONAL DESCRIPTION
The AD855x family of amplifiers are high precision, rail-to-rail
operational amplifiers that can be run from a single-supply voltage.
Their typical offset voltage of less than 1 V allows these amplifiers
to be easily configured for high gains without risk of excessive
output voltage errors. The extremely small temperature drift of
5 nV/C ensures a minimum of offset voltage error over its
entire temperature range of 40C to +125C, making the AD855x
amplifiers ideal for a variety of sensitive measurement applications
in harsh operating environments, such as underhood and
braking/suspension systems in automobiles.
The AD855x family are CMOS amplifiers and achieve their
high degree of precision through auto-zero stabilization. This
autocorrection topology allows the AD855x to maintain its low
offset voltage over a wide temperature range and over its
operating lifetime.
AMPLIFIER ARCHITECTURE
Each AD855x op amp consists of two amplifiers, a main ampli-
fier and a secondary amplifier, used to correct the offset voltage
of the main amplifier. Both consist of a rail-to-rail input stage,
allowing the input common-mode voltage range to reach both
supply rails. The input stage consists of an NMOS differential pair
operating concurrently with a parallel PMOS differential pair.
The outputs from the differential input stages are combined in
another gain stage whose output is used to drive a rail-to-rail
output stage.
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain-to-source resistance of
these transistors. As the amplifier is required to source or sink
more output current, the r
DS
of these transistors increases, raising
the voltage drop across these transistors. Simply put, the output
voltage does not swing as close to the rail under heavy output
current conditions as it does with light output current. This is a
characteristic of all rail-to-rail output amplifiers. Figure 12 and
Figure 13 show how close the output voltage can get to the rails
with a given output current. The output of the AD855x is short-
circuit protected to approximately 50 mA of current.
The AD855x amplifiers have exceptional gain, yielding greater than
120 dB of open-loop gain with a load of 2 k. Because the output
transistors are configured in a common-source configuration,
the gain of the output stage, and thus the open-loop gain of the
amplifier, is dependent on the load resistance. Open-loop gain
decreases with smaller load resistances. This is another
characteristic of rail-to-rail output amplifiers.
BASIC AUTO-ZERO AMPLIFIER THEORY
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for more than 15 years with
some improvements made over time. The AD855x design offers
a number of significant performance improvements over previous
versions while attaining a very substantial reduction in device
cost. This section offers a simplified explanation of how the
AD855x is able to offer extremely low offset voltages and high
open-loop gains.
As noted in the Amplifier Architecture section, each AD855x
op amp contains two internal amplifiers. One is used as the
primary amplifier, the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figure 50 and Figure 51 these are labeled
as V
OSX
, where x denotes the amplifier associated with the offset:
A for the nulling amplifier and B for the primary amplifier. The
open-loop gain for the +IN and IN inputs of each amplifier is
given as A
X
. Both amplifiers also have a third voltage input with
an associated open-loop gain of B
X
.
There are two modes of operation determined by the action of
two sets of switches in the amplifier: an auto-zero phase and an
amplification phase.
Auto-Zero Phase
In this phase, all A switches are closed and all B switches are
opened. Here, the nulling amplifier is taken out of the gain loop
by shorting its two inputs together. Of course, there is a degree
of offset voltage, shown as V
OSA
, inherent in the nulling amplifier
which maintains a potential difference between the +IN and
IN inputs. The nulling amplifier feedback loop is closed through
B
2
and V
OSA
appears at the output of the nulling amp and on
C
M1
, an internal capacitor in the AD855x. Mathematically, this
is expressed in the time domain as
V
OA
[t] = A
A
V
OSA
[t] B
A
V
OA
[t] (1)
which can be expressed as
| |
| |
A
OSA A
OA
B
t V A
t V
+
=
1
(2)
This demonstrates that the offset voltage of the nulling amplifier
times a gain factor appears at the output of the nulling amplifier
and, thus, on the C
M1
capacitor.
+
A
B
B
B
C
M2
V
IN+
V
NB
C
M1
V
OA
B
A
V
NA
B
A
A
A
V
OSA
B
A
V
OUT
V
IN
0
1
1
0
1
-
0
5
0

Figure 50. Auto-Zero Phase of the AD855x
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 15 of 24
Amplification Phase
When the B switches close and the A switches open for the
amplification phase, this offset voltage remains on C
M1
and,
essentially, corrects any error from the nulling amplifier. The
voltage across C
M1
is designated as V
NA
. Furthermore, V
IN
is
designated as the potential difference between the two inputs to
the primary amplifier, or V
IN
= (V
IN+
V
IN
). Thus, the nulling
amplifier can be expressed as
| | | | ( ) | | t V B t V t V A t V
NA A OSA IN A OA
= ] [ (3)
+
A
B
B
B
C
M2
V
IN+
V
NB
C
M1
V
OA
B
A
V
NA
B
A
A
A
V
OSA
B
A
V
OUT
V
IN
0
1
1
0
1
-
0
5
1

Figure 51. Output Phase of the Amplifier
Because A is now open and there is no place for C
M1
to discharge,
the voltage (V
NA
), at the present time (t), is equal to the voltage
at the output of the nulling amp (V
OA
) at the time when A was
closed. If the period of the autocorrection switching frequency is
labeled t
S
, then the amplifier switches between phases every 0.5 t
S
.
Therefore, in the amplification phase
| |
(

=
S NA NA
t t V t V
2
1
(4)
Substituting Equation 4 and Equation 2 into Equation 3 yields
| | | | | |
A
S OSA A A
OSA A IN A OA
B
t t V B A
t V A t V A t V
+
(

+ =
1
2
1
(5)
For the sake of simplification, assume that the autocorrection
frequency is much faster than any potential change in V
OSA
or
V
OSB
. This is a valid assumption because changes in offset voltage
are a function of temperature variation or long-term wear time,
both of which are much slower than the auto-zero clock frequency
of the AD855x. This effectively renders V
OS
time invariant;
therefore, Equation 5 can be rearranged and rewritten as
| | | |
( )
A
OSA A A OSA A A
IN A OA
B
V B A V B A
t V A t V
+
+
+ =
1
1
(6)
or
| | | |
|
|
.
|

\
|
+
+ =
A
OSA
IN A OA
B
V
t V A t V
1
(7)


From these equations, the auto-zeroing action becomes evident.
Note the V
OS
term is reduced by a 1 + B
A
factor. This shows how
the nulling amplifier has greatly reduced its own offset voltage
error even before correcting the primary amplifier. This results
in the primary amplifier output voltage becoming the voltage at
the output of the AD855x amplifier. It is equal to
| | | | ( )
NB B OSB IN B OUT
V B V t V A t V + + = (8)
In the amplification phase, V
OA
= V
NB
, so this can be rewritten as
| | | | | |
(
(

|
|
.
|

\
|
+
+ + + =
A
OSB
IN A B OSB B IN B OUT
B
V
t V A B V A t V A t V
1
(9)
Combining terms,
| | | |( )
OSA B
A
OSA A A
B B B IN OUT
V A
B
V B A
B A A t V t V +
+
+ + =
1
(10)
The AD855x architecture is optimized in such a way that
A
A
= A
B
and B
A
= B
B
and B
A
>> 1
Also, the gain product of A
A
B
B
is much greater than A
B
. These
allow Equation 10 to be simplified to
| | | | ( )
OSB OSA A A A IN OUT
V V A B A t V t V + + (11)
Most obvious is the gain product of both the primary and nulling
amplifiers. This A
A
B
A
term is what gives the AD855x its extremely
high open-loop gain. To understand how V
OSA
and V
OSB
relate to
the overall effective input offset voltage of the complete amplifier,
establish the generic amplifier equation of
( )
EFF OS IN OUT
V V k V
,
+ = (12)
where k is the open-loop gain of an amplifier and V
OS, EFF
is its
effective offset voltage.
Putting Equation 12 into the form of Equation 11 gives
| | | |
A A EFF OS A A IN OUT
B A V B A t V t V
,
+ (13)
Thus, it is evident that
A
OSB OSA
EFF OS
B
V V
V
+

,
(14)
The offset voltages of both the primary and nulling amplifiers
are reduced by the Gain Factor B
A
. This takes a typical input
offset voltage from several millivolts down to an effective input
offset voltage of submicrovolts. This autocorrection scheme is
the outstanding feature of the AD855x series that continues to
earn the reputation of being among the most precise amplifiers
available on the market.



AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 16 of 24
HIGH GAIN, CMRR, PSRR
Common-mode and power supply rejection are indications of
the amount of offset voltage an amplifier has as a result of a change
in its input common-mode or power supply voltages. As shown
in the previous section, the autocorrection architecture of the
AD855x allows it to quite effectively minimize offset voltages.
The technique also corrects for offset errors caused by common-
mode voltage swings and power supply variations. This results
in superb CMRR and PSRR figures in excess of 130 dB. Because
the autocorrection occurs continuously, these figures can be
maintained across the entire temperature range of the device,
from 40C to +125C.
MAXIMIZING PERFORMANCE THROUGH
PROPER LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD855x, care is
needed in laying out the circuit board. The PC board surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier,
reducing parasitic resistance on the board. The use of guard
rings around the amplifier inputs further reduces leakage currents.
Figure 52 shows proper guard ring configuration, and Figure 53
shows the top view of a surface-mount layout. The guard ring
does not need to be a specific width, but it should form a
continuous loop around both inputs. By setting the guard ring
voltage equal to the voltage at the noninverting input, parasitic
capacitance is minimized as well. For further reduction of leakage
currents, components can be mounted to the PC board using
Teflon standoff insulators.
AD8552
AD8552
AD8552
V
OUT
V
OUT
V
OUT
V
IN
V
IN
V
IN
0
1
1
0
1
-
0
5
2

Figure 52. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
V+
AD8552
V
R
2
R
1
R
1
R
2
V
REF
V
REF
V
IN2
GUARD
RING
GUARD
RING
V
IN1
0
1
1
0
1
-
0
5
3

Figure 53. Top View of AD8552 SOIC Layout with Guard Rings

Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the temperature of the junction. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
of the thermal voltage error sources. If the temperature of the
PC board at one end of the component (T
A1
) is different from
the temperature at the other end (T
A2
), the resulting Seebeck
voltages are not equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
both Seebeck voltages are equal, thus canceling the thermocouple
error. Maintaining a constant ambient temperature on the circuit
board further reduces this error. The use of a ground plane helps
distribute heat throughout the board and reduces EMI noise
pickup.
SOLDER
+
+
+
+
COMPONENT
LEAD
COPPER
TRACE
V
SC1
V
TS1
T
A1
SURFACE-MOUNT
COMPONENT
PC BOARD
T
A2
V
SC2
V
TS2
IF T
A1
T
A2
, THEN
V
TS1
+ V
SC1
V
TS2
+ V
SC2
0
1
1
0
1
-
0
5
4

Figure 54. Mismatch in Seebeck Voltages Causes
Thermoelectric Voltage Error
AD8551/
AD8552/
AD8554
A
V
= 1 + (R
F
/R
1
)
NOTES
1. R
S
SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R
1
TO BALANCE SEEBECK VOLTAGES.
R
S
= R
1
R
1
R
F
V
IN
V
OUT
0
1
1
0
1
-
0
5
5

Figure 55. Using Dummy Components to Cancel
Thermoelectric Voltage Errors







Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 17 of 24
1/f NOISE CHARACTERISTICS
Another advantage of auto-zero amplifiers is their ability to
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices, and it
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the
flicker noise is equal to the broadband noise of the amplifier.
At lower frequencies, flicker noise dominates, causing higher
degrees of error for sub-Hertz frequencies or dc precision
applications.
Because the AD855x amplifiers are self-correcting op amps, they
do not have increasing flicker noise at lower frequencies. In
essence, low frequency noise is treated as a slowly varying offset
error and is greatly reduced as a result of autocorrection. The
correction becomes more effective as the noise frequency
approaches dc, offsetting the tendency of the noise to increase
exponentially as frequency decreases. This allows the AD855x
to have lower noise near dc than standard low noise amplifiers
that are susceptible to 1/f noise.
INTERMODULATION DISTORTION
The AD855x can be used as a conventional op amp for gain/
bandwidth combinations up to 1.5 MHz. The auto-zero correction
frequency of the device is fixed at 4 kHz. Although a trace amount
of this frequency feeds through to the output, the amplifier can
be used at much higher frequencies. Figure 56 shows the spectral
output of the AD8552 with the amplifier configured for unity
gain and the input grounded.
The 4 kHz auto-zero clock frequency appears at the output with
less than 2 V of amplitude. Harmonics are also present, but at
reduced levels from the fundamental auto-zero clock frequency.
The amplitude of the clock frequency feedthrough is proportional
to the closed-loop gain of the amplifier. Like other autocorrection
amplifiers, at higher gains there is more clock frequency
feedthrough. Figure 57 shows the spectral output with the
amplifier configured for a gain of 60 dB.
FREQUENCY (kHz)
0
140
0 10 1
O
U
T
P
U
T

S
I
G
N
A
L

(
d
B
)
20
40
60
80
100
120
2 3 4 5 6 7 8 9
V
SY
= 5V
A
V
= 0dB
0
1
1
0
1
-
0
5
6

Figure 56. Spectral Analysis of AD8552 Output in Unity Gain Configuration
FREQUENCY (kHz)
0
140
0 10 1
O
U
T
P
U
T

S
I
G
N
A
L

(
d
B
)
20
40
60
80
100
120
2 3 4 5 6 7 8 9
V
SY
= 5V
A
V
= 60dB
0
1
1
0
1
-
0
5
7

Figure 57. Spectral Analysis of AD855x Output with +60 dB Gain
When an input signal is applied, the output contains some
degree of intermodulation distortion (IMD). This is another
characteristic feature of all autocorrection amplifiers. IMD
appears as sum and difference frequencies between the input
signal and the 4 kHz clock frequency (and its harmonics) and is
at a level similar to, or less than, the clock feedthrough at the
output. The IMD is also proportional to the closed-loop gain of
the amplifier. Figure 58 shows the spectral output of an AD8552
configured as a high gain stage (+60 dB) with a 1 mV input signal
applied. The relative levels of all IMD products and harmonic
distortion add up to produce an output error of 60 dB relative
to the input signal. At unity gain, these add up to only 120 dB
relative to the input signal.
IMD < 100V rms
OUTPUT SIGNAL
1V rms @ 200Hz
FREQUENCY (kHz)
0
0 10 1
O
U
T
P
U
T

S
I
G
N
A
L

(
d
B
)
20
40
60
80
100
120
2 3 4 5 6 7 8 9
V
SY
= 5V
A
V
= 60dB
0
1
1
0
1
-
0
5
8

Figure 58. Spectral Analysis of AD8552 in High Gain with a 1 mV Input Signal
For most low frequency applications, the small amount of auto-
zero clock frequency feedthrough does not affect the precision
of the measurement system. If it is desired, the clock frequency
feedthrough can be reduced through the use of a feedback
capacitor around the amplifier. However, this reduces the
bandwidth of the amplifier. Figure 59 and Figure 60 show a
configuration for reducing the clock feedthrough and the
corresponding spectral analysis at the output. The 3 dB
bandwidth of this configuration is 480 Hz.
AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 18 of 24
100
100k
3.3nF
V
IN
= 1mV rms
@ 200Hz
0
1
1
0
1
-
0
5
9

Figure 59. Reducing Autocorrection Clock Noise Using a Feedback Capacitor
FREQUENCY (kHz)
0
0 10 1
O
U
T
P
U
T

S
I
G
N
A
L
20
40
60
80
100
120
2 3 4 5 6 7 8 9
V
SY
= 5V
A
V
= 60dB
0
1
1
0
1
-
0
6
0

Figure 60. Spectral Analysis Using a Feedback Capacitor
BROADBAND AND EXTERNAL RESISTOR NOISE
CONSIDERATIONS
The total broadband noise output from any amplifier is primarily
a function of three types of noise: input voltage noise from the
amplifier, input current noise from the amplifier, and Johnson
noise from the external resistors used around the amplifier.
Input voltage noise, or e
n
, is strictly a function of the amplifier
used. The Johnson noise from a resistor is a function of the re-
sistance and the temperature. Input current noise, or i
n
, creates
an equivalent voltage noise proportional to the resistors used
around the amplifier. These noise sources are not correlated
with each other and their combined noise sums in a root-
squared-sum fashion. The full equation is given as
( ) | |
2
1
2 2
_
4
S n S n TOTAL n
R i kTr e e + + = (15)
Where:
e
n
= the input voltage noise density of the amplifier.
i
n
= the input current noise of the amplifier.
R
S
= source resistance connected to the noninverting terminal.
k = Boltzmanns constant (1.38 10
23
J/K).
T = ambient temperature in Kelvin (K = 273.15 + C).
The input voltage noise density (e
n
) of the AD855x is 42 nV/Hz,
and the input noise, i
n
, is 2 fA/Hz. The e
n, TOTAL
is dominated by
the input voltage noise, provided the source resistance is less
than 106 k. With source resistance greater than 106 k, the
overall noise of the system is dominated by the Johnson noise of
the resistor itself.
Because the input current noise of the AD855x is very small,
it does not become a dominant term unless R
S
is greater than
4 G, which is an impractical value of source resistance.
The total noise (e
n, TOTAL
) is expressed in volts per square root
Hertz, and the equivalent rms noise over a certain bandwidth
can be found as
BW e e
TOTAL n n
=
,
(16)
where BW is the bandwidth of interest in Hertz.
OUTPUT OVERDRIVE RECOVERY
The AD855x amplifiers have an excellent overdrive recovery
of only 200 s from either supply rail. This characteristic is
particularly difficult for autocorrection amplifiers because the
nulling amplifier requires a nontrivial amount of time to error
correct the main amplifier back to a valid output. Figure 29 and
Figure 30 show the positive and negative overdrive recovery
times for the AD855x.
The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to halfway between the supplies. The time from the input signal
stepdown to the output settling to within 100 V of its final
value is the overdrive recovery time.
INPUT OVERVOLTAGE PROTECTION
Although the AD855x is a rail-to-rail input amplifier, exercise
care to ensure that the potential difference between the inputs
does not exceed 5 V. Under normal operating conditions, the
amplifier corrects its output to ensure the two inputs are at the
same voltage. However, if the device is configured as a comparator,
or is under some unusual operating condition, the input voltages
may be forced to different potentials. This can cause excessive
current to flow through internal diodes in the AD855x used to
protect the input stage against overvoltage.
If either input exceeds either supply rail by more than 0.3 V, large
amounts of current begin to flow through the ESD protection
diodes in the amplifier. These diodes connect between the inputs
and each supply rail to protect the input transistors against an
electrostatic discharge event and are normally reverse-biased.
However, if the input voltage exceeds the supply voltage, these
ESD diodes become forward-biased. Without current limiting,
excessive amounts of current can flow through these diodes,
causing permanent damage to the device. If inputs are subjected
to overvoltage, appropriate series resistors should be inserted to
limit the diode current to less than 2 mA maximum.
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 19 of 24
OUTPUT PHASE REVERSAL
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage moves outside of the common-mode range, the outputs
of these amplifiers suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair
shutting down and causing a radical shifting of internal
voltages, resulting in the erratic output behavior.
The AD855x amplifiers have been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
within the supply voltages. If there is the potential of one or
both inputs exceeding either supply voltage, place a resistor in
series with the input to limit the current to less than 2 mA to
ensure the output does not reverse its phase.
CAPACITIVE LOAD DRIVE
The AD855x family has excellent capacitive load driving
capabilities and can safely drive up to 10 nF from a single 5 V
supply. Although the device is stable, capacitive loading limits
the bandwidth of the amplifier. Capacitive loads also increase
the amount of overshoot and ringing at the output. An R-C
snubber network, shown in Figure 61, can be used to compensate
the amplifier against capacitive load ringing and overshoot.
5V
V
IN
200mV p-p
R
X
60
C
X
0.47F
C
L
4.7nF
V
OUT
AD8551/
AD8552/
AD8554
0
1
1
0
1
-
0
6
1

Figure 61. Snubber Network Configuration for Driving Capacitive Loads
Although the snubber does not recover the loss of amplifier
bandwidth from the load capacitance, it does allow the amplifier to
drive larger values of capacitance while maintaining a minimum of
overshoot and ringing. Figure 62 shows the output of an AD855x
driving a 1 nF capacitor with and without a snubber network.
WITH
SNUBBER
WITHOUT
SNUBBER
10s
100mV
V
SY
= 5V
C
LOAD
= 4.7nF
0
1
1
0
1
-
0
6
2

Figure 62. Overshoot and Ringing are Substantially Reduced
Using a Snubber Network
The optimum value for the resistor and capacitor is a function
of the load capacitance and is best determined empirically because
actual C
LOAD
(C
L
) includes stray capacitances and may differ
substantially from the nominal capacitive load. Table 5 shows
some snubber network values that can be used as starting points.
Table 5. Snubber Network Values for Driving Capacitive Loads
C
LOAD
R
X
C
X

1 nF 200 1 nF
4.7 nF 60 0.47 F
10 nF 20 10 F
POWER-UP BEHAVIOR
At power-up, the AD855x settles to a valid output within 5 s.
Figure 63 shows an oscilloscope photo of the output of the
amplifier with the power supply voltage, and Figure 64 shows
the test circuit. With the amplifier configured for unity gain, the
device takes approximately 5 s to settle to its final output voltage.
This turn-on response time is much faster than most other
autocorrection amplifiers, which can take hundreds of
microseconds or longer for their output to settle.
V+
0V
0V
V
OUT
5s 1V
0
1
1
0
1
-
0
6
3
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV

Figure 63. AD855x Output Behavior on Power-Up
V
OUT
AD8551/
AD8552/
AD8554
V
SY
= 0V TO 5V 100k
100k
0
1
1
0
1
-
0
6
4

Figure 64. AD855x Test Circuit for Turn-On Time



AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 20 of 24
APPLICATIONS INFORMATION
A 5 V PRECISION STRAIN GAGE CIRCUIT
The extremely low offset voltage of the AD8552 makes it an
ideal amplifier for any application requiring accuracy with high
gains, such as a weigh scale or strain gage. Figure 65 shows a
configuration for a single-supply, precision, strain gage
measurement system.
A REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference
for the top of the strain gage resistor bridge. Q1 provides the
current drive for the 350 bridge network. A1 is used to
amplify the output of the bridge with the full-scale output
voltage equal to
( )
B
2 1
R
R R + 2
(17)
where R
B
is the resistance of the load cell.
Using the values given in Figure 65, the output voltage linearly
varies from 0 V with no strain to 4.0 V under full strain.
NOTES
1. USE 0.1% TOLERANCE RESISTORS.
AD8552-A
AD8552-B
REF192
5V
2.5V
6
4
3
2
4.0V
A2
A1
V
OUT
0V TO 4.0V
40mV
FULL-SCALE
Q1
2N2222
OR
EQUIVALENT
350
LOAD
CELL
1k
12.0k 20k
R
1
17.4k
R
2
100
R
3
17.4k
R
4
100
0
1
1
0
1
-
0
6
5

Figure 65. A 5 V Precision Strain Gage Amplifier
3 V INSTRUMENTATION AMPLIFIER
The high common-mode rejection, high open-loop gain, and
operation down to 3 V of supply voltage makes the AD855x
an excellent choice of op amp for discrete single-supply
instrumentation amplifiers. The common-mode rejection ratio
of the AD855x is greater than 120 dB, but the CMRR of the system
is also a function of the external resistor tolerances. The gain of
the difference amplifier shown in Figure 66 is given as
|
|
.
|

\
|

|
|
.
|

\
|
+
|
|
.
|

\
|
+
=
1
2
2
1
4 3
4
OUT
R
R
V
R
R
R R
R
V V 2 1 1 (18)
V2
V1
R
1
R
2
V
OUT
AD8551/
AD8552/
AD8554
R
3
R
4
IF
R
4
R
3
R
2
R
1
R
2
R
1
= , THEN V
OUT
= (V1 V2)
0
1
1
0
1
-
0
6
6

Figure 66. Using the AD855x as a Difference Amplifier
In an ideal difference amplifier, the ratio of the resistors are set
exactly equal to
3
4
1
2
V
R
R
R
R
A = = (19)
Which sets the output voltage of the system to
V
OUT
= A
V
(V1 V2) (20)
Due to finite component tolerance, the ratio between the four
resistors is not exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 66, the exact common-mode rejection ratio can be
expressed as
3 2 4 1
3 2 4 2 4 1
R R R R
R R R R R R
CMRR
2 2
2

+ +
= (21)
In the three-op amp, instrumentation amplifier configuration
shown in Figure 67, the output difference amplifier is set to
unity gain with all four resistors equal in value. If the tolerance
of the resistors used in the circuit is given as , the worst-case
CMRR of the instrumentation amplifier is

CMRR
MIN
2
1
= (22)
V
OUT
= 1 +
2R
R
G
(V1 V2)
R
R
R
R
AD8554-C
V2
R
R
V1
AD8554-B
AD8554-A
R
TRIM
R
G
V
OUT
0
1
1
0
1
-
0
6
7

Figure 67. A Discrete Instrumentation Amplifier Configuration
Consequently, using 1% tolerance resistors results in a worst-case
system CMRR of 0.02, or 34 dB. Therefore, either high precision
resistors or an additional trimming resistor, as shown in Figure 67,
must be used to achieve high common-mode rejection. The
value of this trimming resistor must be equal to the value of R
multiplied by its tolerance. For example, using 10 k resistors
with 1% tolerance requires a series trimming resistor equal to
100 .
Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 21 of 24
A HIGH ACCURACY THERMOCOUPLE AMPLIFIER
Figure 68 shows a K-type thermocouple amplifier configuration
with cold junction compensation. Even from a 5 V supply, the
AD8551 can provide enough accuracy to achieve a resolution of
better than 0.02C from 0C to 500C. D1 is used as a tempera-
ture measuring device to correct the cold junction error from
the thermocouple and should be placed as close as possible to
the two terminating junctions. With the thermocouple measuring
tip immersed in a 0C ice bath, R
6
should be adjusted until the
output is at 0 V.
Using the values shown in Figure 68, the output voltage tracks
temperature at 10 mV/C. For a wider range of temperature
measurement, R
9
can be decreased to 62 k. This creates a
5 mV/C change at the output, allowing measurements of up
to 1000C.
3
2 7
4
5V
+
REF02EZ
12V 2 6
4
D1
1N4148
5.000V
1

+
AD8551
0.1F
0.1F
10F
K-TYPE
THERMOCOUPLE
40.7V/C
0V TO 5.00V
(0C TO 500C)
R
4
5.62k
R
6
200
R
3
53.6
R
2
2.74k
R
1
10.7k
R
5
40.2k
R
8
124k
R
7
453
0
1
1
0
1
-
0
6
8

Figure 68. A Precision K-Type Thermocouple Amplifier with
Cold Junction Compensation
PRECISION CURRENT METER
Because of its low input bias current and superb offset voltage at
single supply voltages, the AD855x is an excellent amplifier for
precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or low-side current
monitor. Using both amplifiers in the AD8552 provides a simple
method to monitor both current supply and return paths for
load or fault detection.
Figure 69 shows a high-side current monitor configuration. In
this configuration, the input common-mode voltage of the
amplifier is at or near the positive supply voltage. The rail-to-
rail input of the amplifier provides a precise measurement even
with the input common-mode voltage at the supply voltage. The
CMOS input structure does not draw any input bias current,
ensuring a minimum of measurement error.
The 0.1 resistor creates a voltage drop to the noninverting
input of the AD855x. The output of the amplifier is corrected
until this voltage appears at the inverting input. This creates a
current through R
1
, which in turn flows through R
2
. The
monitor output is given by
L
1
SENSE
2
I
R
R
R Output Monitor
|
|
.
|

\
|
= (23)
Using the components shown in Figure 69, the monitor output
transfer function is 2.5 V/A.
Figure 70 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8552 is at or near
ground. Again, a 0.1 resistor provides a voltage drop propor-
tional to the return current. The output voltage is given as
( )
|
|
.
|

\
|
+ =
L SENSE OUT
I R
R
R
V V
1
2
(24)
For the component values shown in Figure 70, the output
transfer function decreases from V+ at 2.5 V/A.
8
1
4
3
3V
V+
G
S
D
2
3V
1/2
AD8552
MONITOR
OUTPUT
M1
Si 9433
R
1
100
R
2
2.49k
R
SENSE
0.1
I
L
0.1F
0
1
1
0
1
-
0
6
9

Figure 69. A High-Side Load Current Monitor
V+
1/2 AD8552
V+
Q1
RETURN TO
GROUND
V
OUT
R
2
2.49k
R
1
100
R
SENSE
0.1
0
1
1
0
1
-
0
7
0

Figure 70. A Low-Side Load Current Monitor
PRECISION VOLTAGE COMPARATOR
The AD855x can be operated open-loop and used as a precision
comparator. The AD855x has less than 50 V of offset voltage
when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed-loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the
device has a propagation delay of 15 s on the rising edge and
8 s on the falling edge. Ensure the maximum differential
voltage of the device is not exceeded. For more information,
refer to the Input Overvoltage Protection section.

AD8551/AD8552/AD8554 Data Sheet

Rev. E | Page 22 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6
0
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15 MAX 0.95
0.85
0.75
0.15
0.05
1
0
-
0
7
-
2
0
0
9
-
B

Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters

8 5
4 1
PIN 1
0.65 BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
0.20
0.09
8
0
6.40 BSC
4.50
4.40
4.30
3.10
3.00
2.90
COPLANARITY
0.10
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA

Figure 72. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters

Data Sheet AD8551/AD8552/AD8554

Rev. E | Page 23 of 24
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
0
1
2
4
0
7
-
A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10

Figure 73. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 0
6
1
9
0
8
-
A
8
0
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE

Figure 74. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters

CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
0
6
0
6
0
6
-
A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8
0
45

Figure 75. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)

AD8551/AD8552/AD8554

Rev. E | Page 24 of 24
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option Branding
AD8551ARZ 40C to +125C 8-Lead SOIC_N R-8
AD8551ARZ-REEL 40C to +125C 8-Lead SOIC_N R-8
AD8551ARZ-REEL7 40C to +125C 8-Lead SOIC_N R-8
AD8551ARM-REEL 40C to +125C 8-Lead MSOP RM-8 AHA
AD8551ARMZ 40C to +125C 8-Lead MSOP RM-8 AHA#
AD8551ARMZ-REEL 40C to +125C 8-Lead MSOP RM-8 AHA#
AD8552AR 40C to +125C 8-Lead SOIC_N R-8
AD8552AR-REEL 40C to +125C 8-Lead SOIC_N R-8
AD8552AR-REEL7 40C to +125C 8-Lead SOIC_N R-8
AD8552ARZ 40C to +125C 8-Lead SOIC_N R-8
AD8552ARZ-REEL 40C to +125C 8-Lead SOIC_N R-8
AD8552ARZ-REEL7 40C to +125C 8-Lead SOIC_N R-8
AD8552ARU 40C to +125C 8-Lead TSSOP RU-8
AD8552ARU-REEL 40C to +125C 8-Lead TSSOP RU-8
AD8552ARUZ 40C to +125C 8-Lead TSSOP RU-8
AD8552ARUZ-REEL 40C to +125C 8-Lead TSSOP RU-8
AD8554ARZ 40C to +125C 14-Lead SOIC_N R-14
AD8554ARZ-REEL 40C to +125C 14-Lead SOIC_N R-14
AD8554ARZ-REEL7 40C to +125C 14-Lead SOIC_N R-14
AD8554ARUZ 40C to +125C 14-Lead TSSOP RU-14
AD8554ARUZ-REEL 40C to +125C 14-Lead TSSOP RU-14

1
Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.



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