AD8541
AD8541
AD8541
FEATURES
Single-supply operation: 2.7 V to 5.5 V Low supply current: 45 A/amplifier Wide bandwidth: 1 MHz No phase reversal Low input currents: 4 pA Unity gain stable Rail-to-rail input and output
PIN CONFIGURATIONS
OUT A 1 V 2 +IN A 3 4 IN A
00935-001
AD8541
5 V+
APPLICATIONS
ASIC input or output amplifiers Sensor interfaces Piezoelectric transducer amplifiers Medical instrumentations Mobile communications Audio outputs Portable systems
NC 1 IN A 2
AD8541
8 7 6 5
NC V+ OUT A
00935-002
+IN A 3 V 4
NC
NC = NO CONNECT
GENERAL DESCRIPTION
The AD8541/AD8542/AD8544 are single, dual, and quad railto-rail input and output single-supply amplifiers featuring very low supply current and 1 MHz bandwidth. All are guaranteed to operate from a 2.7 V single supply as well as a 5 V supply. These parts provide 1 MHz bandwidth at a low current consumption of 45 A per amplifier. Very low input bias currents enable the AD8541/AD8542/AD8544 to be used for integrators, photodiode amplifiers, piezoelectric sensors, and other applications with high source impedance. The supply current is only 45 A per amplifier, ideal for battery operation. Rail-to-rail inputs and outputs are useful to designers buffering ASICs in single-supply systems. The AD8541/AD8542/AD8544 are optimized to maintain high gains at lower supply voltages, making them useful for active filters and gain stages. The AD8541/AD8542/AD8544 are specified over the extended industrial temperature range (40C to +125C). The AD8541 is available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23 packages. The AD8542 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead TSSOP surface-mount packages. The AD8544 is available in 14-lead narrow SOIC and 14-lead TSSOP surface-mount packages. All MSOP, SC70, and SOT versions are available in tape and reel only.
OUT A IN A +IN A V 1 2 3 4
AD8542
8 7 6 5
V+ OUT B IN B +IN B
00935-003
00935-004
Figure 3. 8-Lead SOIC, 8-Lead MSOP, and 8-Lead TSSOP (R, RM, and RU Suffixes)
1 2 3 4 5 6 7
14 OUT D 13 IN D 12 +IN D
AD8544
11 V 10 +IN C 9 8 IN C OUT C
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2007 Analog Devices, Inc. All rights reserved.
REVISION HISTORY
1/07Rev. D to Rev. E Updated Format..................................................................Universal Changes to Photodiode Application Section .............................. 14 Changes to Ordering Guide .......................................................... 17 8/04Rev. C to Rev. D Changes to Ordering Guide ............................................................ 5 Changes to Figure 3........................................................................ 10 Updated Outline Dimensions ....................................................... 12 1/03Rev. B to Rev. C Updated Format..................................................................Universal Changes to General Description .................................................... 1 Changes to Ordering Guide ............................................................ 5 Changes to Outline Dimensions................................................... 12
Rev. E | Page 2 of 20
AD8541/AD8542/AD8544 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Symbol VOS 40C TA +125C IB 40C TA +85C 40C TA +125C Input Offset Current IOS 40C TA +85C 40C TA +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain CMRR AVO VCM = 0 V to 2.7 V 40C TA +125C RL = 100 k , VO = 0.5 V to 2.2 V 40C TA +85C 40C TA +125C 40C TA +125C 40C TA +85C 40C TA +125C 40C TA +125C IL = 1 mA 40C TA +125C IL = 1 mA 40C TA +125C VOUT = VS 1 V f = 200 kHz, AV = 1 VS = 2.5 V to 6 V 40C TA +125C VO = 0 V 40C TA +125C RL = 100 k To 0.1% (1 V step) 65 60 0 40 38 100 50 2 45 500 0.1 4 Conditions Min Typ 1 Max 6 7 60 100 1000 30 50 500 2.7 Unit mV mV pA pA pA pA pA pA V dB dB V/mV V/mV V/mV V/C fA/C fA/C fA/C V V mV mV mA mA dB dB A A V/s s kHz Degrees nV/Hz nV/Hz pA/Hz
Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Density Current Noise Density
VOS/T IB/T IOS/T VOH VOL IOUT ISC ZOUT PSRR ISY
SR tS GBP o en en in
0.4
f = 1 kHz f = 10 kHz
Rev. E | Page 3 of 20
AD8541/AD8542/AD8544
VS = 3.0 V, VCM = 1.5 V, TA = 25C, unless otherwise noted. Table 2.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Symbol VOS 40C TA +125C IB 40C TA +85C 40C TA +125C Input Offset Current IOS 40C TA +85C 40C TA +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain CMRR AVO VCM = 0 V to 3 V 40C TA +125C RL = 100 k , VO = 0.5 V to 2.2 V 40C TA +85C 40C TA +125C 40C TA +125C 40C TA +85C 40C TA +125C 40C TA +125C IL = 1 mA 40C TA +125C IL = 1 mA 40C TA +125C VOUT = VS 1 V f = 200 kHz, AV = 1 VS = 2.5 V to 6 V 40C TA +125C VO = 0 V 40C TA +125C RL = 100 k To 0.01% (1 V step) 65 60 0 40 38 100 50 2 45 500 0.1 4 Conditions Min Typ 1 Max 6 7 60 100 1000 30 50 500 3 Unit mV mV pA pA pA pA pA pA V dB dB V/mV V/mV V/mV V/C fA/C fA/C fA/C V V mV mV mA mA dB dB A A V/s s kHz Degrees nV/Hz nV/Hz pA/Hz
Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Density Current Noise Density
VOS/T IB/T IOS/T VOH VOL IOUT ISC ZOUT PSRR ISY
SR tS GBP o en en in
0.4
f = 1 kHz f = 10 kHz
Rev. E | Page 4 of 20
AD8541/AD8542/AD8544
VS = 5.0 V, VCM = 2.5 V, TA = 25C, unless otherwise noted. Table 3.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Symbol VOS 40C TA +125C IB 40C TA +85C 40C TA +125C Input Offset Current IOS 40C TA +85C 40C TA +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain CMRR AVO VCM = 0 V to 5 V 40C TA +125C RL = 100 k , VO = 0.5 V to 2.2 V 40C TA +85C 40C TA +125C 40C TA +125C 40C TA +85C 40C TA +125C 40C TA +125C IL = 1 mA 40C TA +125C IL = 1 mA 40C TA +125C VOUT = VS 1 V f = 200 kHz, AV = 1 VS = 2.5 V to 6 V 40C TA +125C VO = 0 V 40C TA +125C RL = 100 k, CL = 200 pF 1% distortion To 0.1% (1 V step) 65 60 0 40 38 20 10 2 48 40 0.1 4 Conditions Min Typ 1 Max 6 7 60 100 1000 30 50 500 5 Unit mV mV pA pA pA pA pA pA V dB dB V/mV V/mV V/mV V/C fA/C fA/C fA/C V V mV mV mA mA dB dB A A V/s kHz s kHz Degrees nV/Hz nV/Hz pA/Hz
Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Density Current Noise Density
VOS/T IB/T IOS/T VOH VOL IOUT ISC ZOUT PSRR ISY
SR BWP tS GBP o en en in
0.45
f = 1 kHz f = 10 kHz
Rev. E | Page 5 of 20
THERMAL RESISTANCE
Rating 6V GND to VS 6 V 65C to +150C 40C to +125C 65C to +150C 300C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5.
Package Type 5-Lead SC70 (KS) 5-Lead SOT-23 (RJ) 8-Lead SOIC (R) 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 14-Lead SOIC (R) 14-Lead TSSOP (RU) JA 376 230 158 210 240 120 240 JC 126 146 43 45 43 36 43 Unit C/W C/W C/W C/W C/W C/W C/W
For supplies less than 6 V, the differential input voltage is equal to VS.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. E | Page 6 of 20
NUMBER OF AMPLIFIERS
0 4.5
3.5
2.5 1.5 0.5 0.5 1.5 2.5 INPUT OFFSET VOLTAGE (mV)
3.5
4.5
0 40
20
20 40 60 80 TEMPERATURE (C)
100
120
140
5 4 3 2 1 0
00935-009
145
1 55
35
15
25 45 65 85 TEMPERATURE (C)
105
125
145
9 8
INPUT BIAS CURRENT (pA)
VS = 2.7V AND 5V VCM = VS/2
POWER SUPPLY REJECTION (dB)
7 6 5 4 3 2 1
0.5 1.5 2.5 3.5 COMMON-MODE VOLTAGE (V) 4.5 5.5
00935-007
0 0.5
40 100
1k
1M
10M
Rev. E | Page 7 of 20
AD8541/AD8542/AD8544
10k
VS = 2.7V TA = 25C
SMALL SIGNAL OVERSHOOT (%) 50 60
1k
OUTPUT VOLTAGE (mV)
40
30
OS
20
0.1
10
0.01
10
100
10
10k
2.5
50
2.0
40
+OS
1.5
30
OS
1.0
20
0.5
10
1k
10k
1M
10M
10
10k
50
40
30
OS
1.35V
20
50mV
10s
10
10k
00935-013
Rev. E | Page 8 of 20
00935-016
10
00935-015
00935-012
00935-014
00935-011
0.01 0.001
AD8541/AD8542/AD8544
VS = 2.7V RL = 2k AV = 1 TA = 25C
90 80
COMMON-MODE REJECTION (dB)
VS = 5V TA = 25C
70 60 50 40 30 20 10 0
1k 10k 100k FREQUENCY (Hz) 1M 10M
00935-020
1.35V
500mV
10s
00935-017
10
1k
OUTPUT VOLTAGE (mV)
VS = 5V TA = 25C
100
SOURCE SINK
GAIN (dB)
60 40 20 0
10
0.1
00935-018
1k
10k
1M
10M
0.01
10
100
140 120
VS = 5V TA = 25C
4.5 4.0
100 80 60 40 20 0 20
1k 10k 100k FREQUENCY (Hz) 1M 10M
00935-019
3.5 3.0 2.5 2.0 1.5 1.0 0.5 1k 10k 100k FREQUENCY (Hz) 1M 10M
00935-022
PSRR +PSRR
40 100
Rev. E | Page 9 of 20
00935-021
0.01 0.001
AD8541/AD8542/AD8544
5.0 4.5 4.0 VS = 5V VIN = 4.9V p-p RL = 2k TA = 25C
60
VS = 5V RL = TA = 25C
50
40 +OS 30 OS 20
10
1k
10k
1M
10M
10k
60
VS = 5V RL = 10k TA = 25C
50
40 +OS 30 OS 20
2.5V
50mV
10 100 1k CAPACITANCE (pF) 10k
00935-024
10s
50
VS = 5V RL = 2k AV = 1 TA = 25C
40 +OS 30 OS 20
2.5V
1V
10s
10
10k
00935-025
Rev. E | Page 10 of 20
00935-028
10
00935-027
10
00935-026
0 10
AD8541/AD8542/AD8544
VS = 5V RL = NO LOAD TA = 25C
PHASE SHIFT (Degrees)
55 50
80
GAIN (dB)
45 90 135 180
VS = 5V
45 40
60 40 20 0
VS = 2.7V
35 30 25 20 55
00935-029
1k
10k
1M
10M
35
15
25 45 65 85 TEMPERATURE (C)
105
125
145
VIN VOUT
VS = 5V RL = 10k AV = 1 TA = 25C
IMPEDANCE ()
2.5V
00935-030
1V
20s
0 1k
50
40
30
20
10
15nV/DIV
00935-031
10 15 FREQUENCY (kHz)
20
25
Rev. E | Page 11 of 20
00935-034
00935-032
Rev. E | Page 12 of 20
AD8541/AD8542/AD8544 APPLICATIONS
NOTCH FILTER
The AD854x have very high open-loop gain (especially with a supply voltage below 4 V), which makes it useful for active filters of all types. For example, Figure 35 illustrates the AD8542 in the classic twin-T notch filter design. The twin-T notch is desired for simplicity, low output impedance, and minimal use of op amps. In fact, this notch filter can be designed with only one op amp if Q adjustment is not required. Simply remove U2 as illustrated in Figure 36. However, a major drawback to this circuit topology is ensuring that all the Rs and Cs closely match. The components must closely match or notch frequency offset and drift causes the circuit to no longer attenuate at the ideal notch frequency. To achieve desired performance, 1% or better component tolerances or special component screens are usually required. One method to desensitize the circuit-to-component mismatch is to increase R2 with respect to R1, which lowers Q. A lower Q increases attenuation over a wider frequency range but reduces attenuation at the peak notch frequency.
5.0V R 100k C2 53.6F 2.5VREF R/2 50k C 26.7nF C 26.7nF R2 2.5k R 100k 3 2 8 U1 4
Figure 37 is an example of the AD8544 in a notch filter circuit. The frequency dependent negative resistance (FNDR) notch filter has fewer critical matching requirements than the twin-T notch and for the FNDR Q is directly proportional to a single resistor R1. While matching component values is still important, it is also much easier and/or less expensive to accomplish in the FNDR circuit. For example, the twin-T notch uses three capacitors with two unique values, whereas the FNDR circuit uses only two capacitors, which may be of the same value. U3 is simply a buffer that is added to lower the output impedance of the circuit.
R1 Q ADJUST 200 C1 1F 2.5VREF R 2.61k C2 1F R 2.61k R 2.61k R 2.61k 2.5VREF 13 12 3 2 4 U1 11 9 10
1/4 AD8544
U3 8
VOUT
1/4 AD8544
1
1/4 AD8544
7 U2
6 5
1/2 AD8542
1
VOUT
f= 1 2 LC1
1/4 AD8544
U4 14 NC
00935-037
L = R2C2
1/2 AD8542
7 U2
f0 = f0 =
1 2RC 1 4 1
5 6
2.5VREF
00935-035
R1 R1 + R2
R1 97.5k
2.5VREF
COMPARATOR FUNCTION
A comparator function is a common application for a spare op amp in a quad package. Figure 38 illustrates of the AD8544 as a comparator in a standard overload detection application. Unlike many op amps, the AD854x family can double as comparators because this op amp family has a rail-to-rail differential input range, rail-to-rail output, and a great speed vs. power ratio. R2 is used to introduce hysteresis. The AD854x, when used as comparators, have 5 s propagation delay at 5 V and 5 s overload recovery time.
R2 1M
R1 1k
AD8541
4 6
VIN
2.5VREF
VOUT
R/2
00935-036
VIN
2.5VREF 2.5VDC
VOUT
00935-038
1/4 AD8541
Rev. E | Page 13 of 20
AD8541/AD8542/AD8544
PHOTODIODE APPLICATION
The AD854x family has very high impedance with an input bias current typically around 4 pA. This characteristic allows the AD854x op amps to be used in photodiode applications and other applications that require high input impedance. Note that the AD854x has significant voltage offset that can be removed by capacitive coupling or software calibration. Figure 39 illustrates a photodiode or current measurement application. The feedback resistor is limited to 10 M to avoid excessive output offset. Also, note that a resistor is not needed on the noninverting input to cancel bias current offset because the bias current-related output offset is not significant when compared to the voltage offset contribution. For best performance, follow the standard high impedance layout techniques, which include: Shielding the circuit. Cleaning the circuit board. Putting a trace connected to the noninverting input around the inverting input. Using separate analog and digital power supplies.
C 100pF R 10M OR V+ 2 3 D 4 7 6
VOUT
AD8541
00935-039
2.5VREF
2.5VREF
Rev. E | Page 14 of 20
1.60 BSC
1 2 3
2.80 BSC
4.50 4.40 4.30
14
6.40 BSC
1 7
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19
1.45 MAX
0.20 0.09
0.15 MAX
0.50 0.30
SEATING PLANE
8 0
Figure 40. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters
Figure 41. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
2.20 2.00 1.80 1.35 1.25 1.15 PIN 1 1.00 0.90 0.70
5 1 2 4 3
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
0.50 (0.0197) 0.25 (0.0098) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.10 MAX
0.30 0.15
SEATING PLANE
0.22 0.08
COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 42. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters
Figure 43. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches)
Rev. E | Page 15 of 20
060606-A
AD8541/AD8542/AD8544
3.20 3.00 2.80
3.10 3.00 2.90
6.40 BSC
0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING 0.20 PLANE 0.09
0.23 0.08
8 0
COPLANARITY 0.10
Figure 44. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890)
Figure 45. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters
8 1
5 4
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 46. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Rev. E | Page 16 of 20
060506-A
AD8541/AD8542/AD8544
ORDERING GUIDE
Model AD8541AKS-R2 AD8541AKS-REEL7 AD8541AKSZ-R21 AD8541AKSZ-REEL71 AD8541AR AD8541AR-REEL AD8541AR-REEL7 AD8541ARZ1 AD8541ARZ-REEL1 AD8541ARZ-REEL71 AD8541ART-R2 AD8541ART-REEL AD8541ART-REEL7 AD8541ARTZ-R21 AD8541ARTZ-REEL1 AD8541ARTZ-REEL71 AD8542AR AD8542AR-REEL AD8542AR-REEL7 AD8542ARZ1 AD8542ARZ-REEL1 AD8542ARZ-REEL71 AD8542ARM-R2 AD8542ARM-REEL AD8542ARMZ-R21 AD8542ARMZ-REEL1 AD8542ARU AD8542ARU-REEL AD8542ARUZ1 AD8542ARUZ-REEL1 AD8544AR AD8544AR-REEL AD8544AR-REEL7 AD8544ARZ1 AD8544ARZ-REEL1 AD8544ARZ-REEL71 AD8544ARU AD8544ARU-REEL AD8544ARUZ1 AD8544ARUZ-REEL1
1
Temperature Range 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C 40C to +125C
Package Description 5-Lead SC70 5-Lead SC70 5-Lead SC70 5-Lead SC70 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP
Package Option KS-5 KS-5 KS-5 KS-5 R-8 R-8 R-8 R-8 R-8 R-8 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RU-8 RU-8 RU-8 RU-8 R-14 R-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14
Rev. E | Page 17 of 20
AD8541/AD8542/AD8544 NOTES
Rev. E | Page 18 of 20
AD8541/AD8542/AD8544 NOTES
Rev. E | Page 19 of 20
AD8541/AD8542/AD8544 NOTES
2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00935-0-1/07(E)
Rev. E | Page 20 of 20