lEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 11, NO.

2, MARCH 1996 31 1

A High-Performance Single-phase Rectifier

with Input Power Factor Correction
Roberto Martinez, Member, IEEE, and Prasad N. Enjeti, Senior Member, IEEE

Abstruct- In this paper, a high-performance single-phase ac-

to-dc rectifier with input power factor correction is proposed. The
proposed approach has many advantages, including fewer semi-
conductor components, simplified control, and high-performance
features, and satisfies IEC 555 harmonic current standards.
Simulation and experimental results obtained on a laboratory
prototype are discussed. A hybrid power module of the proposed
approach is also shown.

N
I. INTRODUCTION Fig. 1. Conventional boost-type rectifier with input power factor correction.

M ANY conventional switching power supplies in data

processing equipment and low power motor drive sys-
tems operate by rectifying the input ac line voltage and filtering
it with large electrolytic capacitors. This process involves
both nonlinear and storage elements and results in undesirable
side effects such as the generation of distorted input current
waveform rich harmonics. The resulting input power factor
is also poor (0.6 or less). Further, the input current has the
shape of narrow pulses, which in turn increases its rms. value.
Buildings with large number of computers and data processing
equipment also experience large neutral currents rich in third Fig. 2. Proposed single-phase rectifier with input power factor correction.
(180 Hz) harmonic currents [9]. The reduction in input current
harmonics and improved power factor operation of motor drive 2) The diode Dd is in the series path of the power flow
systems and switching power supplies is important from the and contributes to voltage drop, increased power loss,
energy saving point of view and also to satisfy the forthcoming and reduced reliability (see Fig. 1).
harmonic standards such as IEC-555. The present IEC 555 3) Special design of the dc-side inductor is necessary to
regulations allow a third harmonic level of 2.3 A maximum for carry dc current as well as high frequency ripple current.
power levels above 200 W. These limits are further expected 4) At any given instant, three semiconductor device drops
to go down with future revisions. The expected new limit exist in the power flow path.
is 3.6 mA/W or 1.08 A maximum for the third harmonic In response to these concerns, this paper proposes and in-
with much lower limits for higher harmonic components. vestigates an alternative power factor correction and harmonic
Several switching regulator topologies are suitable for power current reduction topology for switching power converters and
factor improvement and harmonic current reduction. The most motor drive systems fed from single-phase ac mains. Analysis
popular among them is the boost topology in Fig. 1. Several and design of the proposed approach, along with experimental
dedicated power factor controller integrated circuits (IC's), results, are discussed. An integrated power module of the
such as Microlinear's MU812 [8] and Unitrode UC2854 [91, proposed topology is also shown.
are currently available. Despite the improved performance of
the existing boost topology shown in Fig. 1, there are several 11. PROPOSEDI POWER FACTOR
CORRECTION TOPOLOGY
disadvantages associated with this approach. Fig. 2 illustrates the proposed single-phase power factor
I) The required switching frequency of the boost switch correction approach. In this approach, series diode Dd in the
is high. This in turn increases the switching losses and boost topology has been eliminated. Another notable change is
lowers the efficiency. that the dc-side inductor is no longer necessary, and instead an
ac-side inductor is required. The advantages of the proposed
Manuscript received April 26, 1993; revised September 5 , 1995. approach are as follows:
The authors are with the Power Electronics Laboratory, Department of I) Improved characteristics in terms of high input power
Electrical Engineering, Texas A&M University, College Station, TX 77843-
3128 USA. factor and sinusoidal shape of the input current (see
Publisher Item Identifier S 0885-8993(96)01928-X. Figs. 7 and 9).
0885-8993/96$05.00 0 1996 IEEE

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 312 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 11, NO. 2, MARCH 1996

I
1-

(c)
Fig. 3. Modes of operation. (a) Mode 1. (b) ode 2. (e) Mode 3. (d) Mode 4.

2) At any given instant, only two semiconductor device

drops exist in the power flow path.
3) The rms current rating of the boost switches S1 and Sz
is low. Vin
4) The location of the boost inductor L on the ac side
contributes to reductions in EM1 interference.
5 ) The gate drives for switches SIand SZ are referenced
to the same ground.
Fig. 3 illustrates the various modes of operation for the
proposed approach. Mode 1 in Fig. 3(a) occurs when the
input ac voltage is positive and the switches are open (off).
Current flows-through diode D1, through the capacitor and
load, and back through the antiparallel diode of Tz. Fig. 3(b)
shows Mode 2, which occurs when the input ac voltage is
positive and the switches are closed (on). Input current flows
through switch TI and back through the antiparallel diode of
T2, thus providing a path for the input current. At the same
time, the bulk capacitor discharges and supplies current to the
load. Mode 3 in Fig. 3(c) occurs when the input ac voltage is Fig. 4. Circuit schematic used for PSPICE simulation.
negative and the switches are open (off). Current flows through
diode D z , through the capacitor and load, and back through input current. The simulation results demonstrate near unity
the antiparallel diode of T I .Fig. 3(d) shows Mode 4, which input power factor and near sinusoidal input current shape.
occurs when the input ac voltage is negative and the switches
are closed (on). Input current flows through switch Tz and IV. DESIGNEXAMPLE
back through the antiparallel diode of T I , thus providing a Fig. 6 shows the proposed rectifier circuit, designed for a 1.5
path for the input current. At the same time, the dc capacitor kW load specification from a 120 V,, single-phase source.
discharges and supplies current to the load. The output voltage of 200 Vdc requires minimal boosting.
Using per-unit values to simplify calculations we get
vbase = 120 v = 1 pu Phase = 1.5 kW = 1 pu.
111. PSPICE SIMULATION
Assuming zero switching losses, Pln M Pout= 1.0 pu. This
Fig. 4 shows the schematic of the circuit used to simulate on yields
PSPICE software. Suitable gating signals are generated to the
MOSFET switches by comparing a high frequency triangular
carrier with a rectified sine wave of line frequency [see Fig.
5 (a) and (b)]. The component values employed in simulation
are given in Section IV. Fig. 5(c) shows the resulting input
current, and Fig. 5(d) shows the input voltage and the output
dc voltage. Fig. 5(e) illustrates the frequency spectrum of the

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 MARTINEZ AND ENJETI: HIGH-PERFORMANCE SINGLE-PHASE RECTIFIER WITH INPUT POWER FACTO'R CORRECTION 313

#,//\-,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . j
,
I

,
I

Fig. 5. PSPICE simulation results. (a) Comparison of the rectified sine wave and the triangular carrier. (b) PWM gating signals for the switches. (c) Input
current. (d) Input voltage and output (dc) voltage. (e) Frequency spectrum of the input current.

.lout= __ 1500 = 7.5 A.

Ptmse = - (4)
The bulk output filter capacitor may be determined by setting
vout 200 the output ripple constraint. By allowing a 5% output voltage

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 314 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 11, NO. 2, MARCH 1996

1:

LF444CN

II

ICL8038

Fig. 6. Prototype circuit design used.

ripple and considering the ripple frequency to be twice the Letting n = fs/f = 36.5 kHz/60 Hz and assuming Vn =
line frequency, we get 1.0 pu

X L 10.15781 R (12)
= (0.05)V,,,(p~) = (0.05)(1.67) = 0.083 (5) XL
L = - 1419 pH. (13)
jKippie= 0.083 * 120 10 V (6) w
We chose an available 560-pH inductor.
The upper two diodes are fast-recovery diodes, while the
two lower diodes already exist as the antiparallel diodes
and I 2 is the twice the line frequency current. Equating of the power MOSFET’s; therefore, a total of only four
instantaneous input power to output dc power semiconductors need to be used. The diodes and MOSFET’s
need to be rated higher than the sum of the dc output rail
120 * 12.5 voltage plus the anticipated voltage ripple. Fig. 6 shows the
I2 = = 7.5 A. (8)
200 circuit diagram of the power circuit evaluated. Fig. 7 shows
the hybrid power module of the proposed approach. Fig. 7(b)
Therefore, from (7) and (c) shows the dimension diagram of the power module
(courtesy International Rectifier Corp.).
7.5 A As shown in Fig. 6, the PWM gating signals were generated
C= (9)
(2)(271-)(60 Hz)(lO V) = 99 pF. through a feed-forward approach. The input voltage was
sensed through a voltage transformer, then rectified by an
We chose G = 1300 ,LLF to assure a stiffer dc voltage. opamp full-wave rectifier. An opamp amplifier stage follows
The input inductor, L , may be determined knowing the to control the modulation by adjusting the gain. The rectified
switching frequency is 36.5 kHz.To obtain a 10% input current waveform is then compared, via an LM3 11 comparator, to a
ripple we find L by triangle wave generated by an ICL8038 function generator IC.
The comparison is such that the comparator output voltage is
high when the triangle signal is above the rectified reference
signal. A current buffer, MC34152, takes the output from
the comparator into both inputs of the UC3708 dual driver.
Finally, the outputs from the driver are given to the gates
of power MOSFET’s, SIand 5’2, while tying both MOSFET
sources and control circuit ground to the same node.

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 MARTINEZ AND ENJETI: HIGH-PERFORMANCE SINGLE-PHASE RECTIFIER WITH INPUT POWER FACTOR CORRECTION 315

I------- -?-------- I
I
1
I 4-4 D2
I
I1
0

ALL DlMENSlONS ARE SHOWN IN MILLIMETERS (INCHES)

(b)

(c)
Fig. 7. Hybrid power module of the proposed power factor corrected rectifier topology (courtesy International Rectifier Corp., CA). (a) Pin assignment
schematic diagram. (b) Power module dimension diagram. (c) Packaging and appearance.

V. EXPERIMENTAL
RESULTS current of the piroposed approach (Fig. 2 ) with power factor
Fig. 8(a) shows the input voltage and input current of the correction at kw and Fig. 8(d) shows the frequency
implemented circuit without power factor correction (switches spectrum of the input CUrrent of Fig. 8(C). Fig. and (b)
off) at 1.4 kW. Fig. 8(b) shows the frequency spectrum of illustrates the p e r f o m " of the proposed topology (Fig. 2)
the current of Fig. 8(a). The high harmonic content of the with power factor correction when the output power is 800 W.
current is observed. Fig. 8(c) shows the input voltage and The experimental results demonstrate that the line current is

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 316 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 11, NO. 2, MARCH 1996

(c) (d)
Fig. 8. Experimental results for Po = 1400 W. (a) Input voltage and current without power factor correction. (b) Fourier spectrum of the input current.
(c) Input voltage and current with power factor correction. (d) Fourier spectrum of the input current in (c).

(a) (b)
Fig. 9. Experimental results for Po = 800 W. (a) Input voltage and current with power factor correction. (b) Fourier spectrum of the input current in (a).

of high quality and near sinusoidal, with negligible harmonic gives the results without power factor correction, while Tables
content. I1 and I11 give the results with power factor correction. The
Tables 1-111 show the experimental data collected from the data are the measured percent harmonic content with respect to
circuit designed in the previous section. The load was varied the fundamental, the total harmonic distortion, and the power
at values of 300 W, 600 W, 800 W, 1 kW, and 1.4 kW. Table I factor. The table shows nearly unity power factor at 1.4 kW

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 MARTINEZ AND ENJETI: HIGH-PERFORMANCE SINGLE-PHASE RECTIFIER WITH INPUT POWER FACTOR CORRECTION 317

REFERENCES
Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics:
Converters, Applications, and Design. New York Wiley, 1989, pp.
25-39, 409, 429.
C. Zhou, “Desi,gn and analysis of an active power factor correction
circuit,” thesis, ‘VPI & State University, September 1989.
L. H. Dixon, “High power factor pre-regulator for off-line power
supplies,” Unitrode Linear Integrated Circuits Data and Applications
Handbook, April, 1990.
Schlecht, B. A. Miwa, “Active power factor correction for switching
power supplies,” IEEE Trans. Power Electron., vol. 2, no. 4, Oct. 1987.
Wenekink, A. Kawamura, and R. G. Hoft, “A high frequency ac/dc
converter with unity power factor and minimum harmonic distortion,”
I
1400 59.0 [ 10.6 I 11.3 1 5.42 1 4.09 I 2.70 1 1.70 61.44 I 0.8520 IEEE Trans. Power Electron., vol. 6, no. 3, July 1991.
A. R. Prasad, F’. D. Ziogas, and S. Manias, “An active power factor
correction technique for three phase diode rectifiers,” IEEE Trans. Power
TABLE I1 Electron., vol. 6 , no. 1, Jan. 1991.
MEASURED
DATAWITH POWERFACTORCORRECTION Hudson, S. Hong, and R. Hoft, “Modeling and simulation of a digitally
controlled active rectifier for power conditioning,” in Proc. APEC’91
Con$, 1991, pp. 423429.
Micro Linear Corp. Data Book, 1990, pp. 5-20-5-30. Unitrode Linear
Integrated Circuits Data and Applications Handbook, 1990, pp. 9-
287-9-296.
P. Enjeti, W. Shireen, P. Packebush, and I. Pitel, “Analysis and design
of a new active power filter to cancel neutral current harmonics in
three phase four wire electric distribution systems,” IEEE Trans. Ind.
Applicat., vol. 30, no. 6, Nov./Dec. 1994, pp. 1565-1572.

loo0 - 2.40 - 2.51 - 3.49 - 2.17

Roberto Martinez (S’90-M’94) received the B.S.
1400 - 3.33 - 1.77 - 3.10 - 1.66 and M.S. degrees in electrical engineering, with
a concentration in power electronics, from Texas
A&M University, College Station, in 1991 and
TABLE 111 1994, respectively.
MEASURED
DATAWITH POWER FACTORCORRECTION From 1990 to 1993 he was with the Texas A&M
University TEES Power Electronics Laboratory,
where he did work related to single-phase and
three-phase power factor correction, three-phase
inverters, and three-phase active filters. Since 1993
he has been with International Rectifier, first as
Rotation Engineer, working on the testing of Schottky diodes, fast recovery
diodes, power MOSFET’s, and IGBT’s at the manufacturing facility in Mexico
from 1993 to 1995. He helped develop next-generation fast-recovery diodes
at the Research and Development Group in El Segundo, CA, and then worked
on power MOSFET wafer fabrication issues at the Temecula, CA, HEXFET
America wafer fabrication facility. He is working currently as Applications
Engineer in the International Rectifier Applications Department, El Segundo,
CA, with a concentration on off-line power supplies and battery-charging,
1400 1 - I 1.11 [ - I 1.16 1 - I 0.86 I 5.47 I 0.9985 and power-management applications.

with diminishing power factor as the power decreases

In
I, % = -100%
Ii Prasad N. Enjeti (S’86-M’88-SM’88) received the
loo%J1, f I3 f 14 -!- 1 5 . . . f 115 B.E. degree in Hyderabad, India, in 1980, the M.
THD% = (15) Tech. degree from the Indian Institute of Technol-
I1 ogy, Kanpur, in 1982, and the Ph.D. degree from
I1 Concordia University, Montreal, Canada, in 1987,
PF = COS^. (16)
d11 f 1 2 + 1 3 f 14 f 1 5 +
all in electrical engineering.
”’ f 115 He joined the Electrical Engineering Department
at Texas A&M University, College Station, where
VI. CONCLUSION he is Associate Professor. His primary research
Typical ac current waveforms in single-phase rectifier cir- interests include advance converters for power sup-
plies and motor drives, power quality issues and
cuits are far from being sinusoidal. The theoretical and ex- active power filter development, utility interface issues, “clean” power con-
perimental results demonstrate that the power factor can be verter designs, and electronic ballasts for fluorescent HID lamps. He is actively
improved to almost unity by implementing the proposed involved in many prsojects with industries and is engaged in teaching, research,
and consulting in the area of power electronics.
topology with a simple control circuit. By having only two Dr. Enjeti received the second-best paper award in 1993 and the second-
semiconductors in the current path at any time, losses can best transaction paplEr published from midyear 1994 to midyear 1995 in IEEE
be reduced over the conventional boost topology. The pro- INDUSTRY APPLICATIONS. He is Chair of Special Activities for the Industrial
Power Converter Committee (IPCC) of the IEEE Industry Applications
posed topology is appropriate for low and medium power Society and Associate Editor of IEEE TRANSACTIONS ON POWERELECTRONICS.
applications, such as in power supplies and motor drives. He is a Registered Professional Engineer in Texas.

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