Annexure - e - Ecs351 (III)
Annexure - e - Ecs351 (III)
Annexure - e - Ecs351 (III)
LAB MANUAL
Semester :
THIRD
Sub Code :
ECS-351
Subject :
INDEX
Sl.
#
Experiment / Program
Page
#
1-2
3-4
5-6
9-11
12-13
A L U
14-15
16-17
THEORY:
TTL CHARACTERISTICS:
Fan-in is the maximum number of inputs to a gate. Although physical considerations
limit fan-in, more pragmatic factors, such as limitations on the number of pins possible
on IC packages and their standardization predominate. TTL NAND gates typically
provide 1, 2, 4, or 8 inputs.
If more than eight inputs are required, then a network of NAND gates must be
employed.
Fan-out specifies the number of standard loads that the output of a gate can drive
without impairing its normal operation. A standard load is defined to be the amount of
current required to drive an input of another gate in the same logic family. Due to the
nature of TTL gates, two different fan-out values are given, one for HIGH outputs and
one for LOW outputs.
Negative; hence, IILmax = -1.6mA. A typical TTL gate can source 400 A (I0H(max)) of
Current and can sink 16 mA (I0L(max)). Hence TTL gates typically have a HIGH (logic
level) fan-out of |I0H(max)/IIH(max)| = |-400 A / 40 A| = 10, and a LOW fan-out of |
I0L(max)/IIL(max)| = |16 mA / -1.6 mA| = 10. Exceeding these fan-out limits may
result in incorrect voltage levels at the output, as a gate cannot provide or sink
enough current. A
CIRCUIT DIAGRAM:
voltage transfer curve is a graph of the input voltage to a gate versus its output
voltage Figure 3.2 shows the transfer curve for TTL inverter without any fan out. When
the input voltage is 0 V, the output is HIGH at 3.3 V. As the input voltage is increased
from 0 to 0.7 V, the output
PROCEDURE:
OBSERVATIONS:
Sr.
1
2
3
4
5
6
7
Vi
Vo
THEORY:
Connecting wires.
CMOS FAMILY
CMOS logic is exemplified by its extremely low power consumption and high noise
immunity. Hence, it is prevalently used in devices demanding low power dissipation,
such as digital wristwatches and other battery powered devices, or in devices
operated in noisy environments, such as industrial plants. A wide variety of CMOS
logic devices in the 4000 series are available. Unlike TTL logic, CMOS logic requires
two supply voltages, VDD and VSS. In typical logical designs, VDD ranges from +3 V
to +16 V. The other supply, VSS, is normally grounded. Also, the physical
representation of the binary states in CMOS logic is not entirely compatible with TTL
logic. As a consequence of CMOS's extremely high input impedance, the logic levels in
CMOS systems are essentially VDD and ground. If, for example, a 5 volt power supply
is used, LOW typically ranges from 0 to 0.01 V and HIGH from 4.99 to 5.0 V for CMOS
outputs. Input voltages ranging from 3.5 to 5 V are recognized as HIGH and voltages
from 0 to 1.5 V as LOW. It may appear that CMOS output logic levels, using a 5 V
power supply, completely conform to the TTL logic level ranges of 0 to 0.8 V for LOW
and 2.0 to 5.5 V for HIGH. However, the Typical CMOS gates can sink about 0.4 mA in
the LOW state while maintaining an output voltage of 0.4 V or less. (A pull-up resistor
to +5 can be connected to the gate output to assure that the output is above 3.5V.)
Whether this is sufficient for reliable operation depends upon the exact specifications
for both the TTL outputs and the CMOS inputs.
CIRCUIT DIAGRAM:
CMOS CHARACTERISTICS:
The voltage transfer curve for a typical CMOS logic gate is shown in Figure 3.6. Note
that the curves in the transition region are almost vertical. This narrow transition
region is the reason for CMOS logic's high noise immunity. Not much voltage range is
covered in the transition from voltage and is approximately half the supply voltage.
As with TTL logic, current spiking occurs during switching. Hence, bypass capacitors
are used in CMOS logic design as well. However, they are not as critical as in TTL logic
design because of CMOS's high noise immunity. Whereas the typical quiescent (static)
PROCEDURE:
1) Connect the circuit as per circuit diagram for CMOS IC.
2) Vary the i/p voltage in steps & note down corresponding o/p voltage.
3) Plot graph of Vi Vs Vo.
OBSERVATIONS:
Sr.
1
2
3
4
5
6
7
Vi
Vo
THEORY:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock,
which has the output of any one but the last flip-flop connected to the "data" input of
the next one in the chain, resulting in a circuit that shifts by one position the onedimensional "bit array" stored in it, shifting in the data present at its input and shifting
out the last bit in the array, when enabled to do so by a transition of the clock input.
More generally, a shift register may be multidimensional; such that its "data in"
input and stage outputs are themselves bit arrays: this is implemented simply by
running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often
configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO).
There are also types that have both serial and parallel input and types with serial and
parallel output. There are also bi-directional shift registers which allow shifting in
both directions: LR or RL. The serial input and last output of a shift register can
also be connected together to create a circular shift register.
RESULT: The entire shift right & shift left operations are verified operations.
PRECAUTIONS:
(i)
(ii)
(iii)
(iv)
PIPO:Truth Table
Clock
Time
Clock-2
Clock-1
T0
T1
T2
T3
T4
Q3
1
Outputs
Q2 Q1
Q0
1
0
1
1
1
0
1
1
1
RESULT: The entire shift right & shift left operations are verified operations.
PRECAUTIONS:
(i)
Connections were given as per circuit diagram.
(ii)
Switch on the power supply after connecting circuit.
(iii)
Logical inputs were given as per truth table.
(iv)
Observe the logical output and verify with the truth tables.
The Common Cathode Display (CCD) - In the common cathode display, all the
cathode connections of the LED's are joined together to logic "0" and the
individual segments are illuminated by application of a "HIGH", logic "1" signal
to the individual Anode terminals.
The Common Anode Display (CAD) - In the common anode display, all the
anode connections of the LED's are joined together to logic "1" and the
individual segments are illuminated by connecting the individual Cathode
terminals to a "LOW", logic "0" signal.
3
4
6
7
Binary Coded Decimal (BCD or "8421" BCD) numbers are made up using just 4 data
bits (a nibble or half a byte) similar to the Hexadecimal numbers we saw in the
binary tutorial, but unlike hexadecimal numbers that range in full from 0 through to F,
BCD numbers only range from 0 to 9, with the binary number patterns of 1010
through to 1111 (A to F) being invalid inputs for this type of display and so are not
used as shown below.
Decim
al
0
1
2
3
4
5
6
7
Binary Pattern
8
4
2
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
BCD
Decim
al
0
1
2
3
4
5
6
7
8
9
Binary Pattern
8
4
2
1
1
0
0
0
1
0
0
1
10
11
12
13
14
BCD
8
9
Invali
d
Invali
d
Invali
d
Invali
d
Invali
d
15
Invali
d
The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits)
of data, allowing a single data byte to hold a BCD number in the range of 00 to 99.
An example of the 4-bit BCD input (0100) representing the number 4 is given below.
different types of display available, e.g. 74LS48 for common-cathode LED types,
74LS47 for common-anode LED types, or the CMOS CD4543 for liquid crystal display
(LCD) types.
RESULT: Output are observe on the 7-segment display for various combinations.
PRECAUTIONS:
1) Connect the circuit as shown fig.
2) Switch on the power supply & observe the output on 7-segment
display for different BCD input.
Y = S4 (S3 + S2)
TRUTH TABLE:
BCD SUM
S4
0
0
0
S3
0
0
0
CARRY
S2
0
0
1
S1
0
1
0
C
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
OPCOD
E
2000
2003
2004
2005
2006
2007
2008
2009
200A
200B
21 09
20
7E
23
86
23
77
EF
EXAMPLE:
Address
2009
200A
200B
RESULT:
LABEL
MNEMONI
C
LXI
MOV
INX
ADD
INX
MOV
RST
OPRAND
H 2009
A,M
H
M
H
M,A
5
COMMENTS
DATA
DATA
RESULT
Result
Data
23 Data in decimal
32 Data in decimal
55 Answer in decimal
23H+32H=55H
OPCOD
E
2000
2003
2004
2005
2006
2007
2008
2009
200A
200B
21 09
20
7E
23
96
23
77
EF
LABEL
MNEMONI
C
LXI
MOV
INX
SUB
INX
MOV
RST
DATA
DATA
OPRAND
H 2009
A,M
H
M
H
M,A
5
COMMENTS
RESULT
Result
EXAMPLE:
Address
2009
200A
200B
RESULT:
Data
32 Data in decimal
12 Data in decimal
20 Answer in decimal
32H-12H=20H