Data Sheet
Data Sheet
Data Sheet
NCP1077A/B, NCP1079A/B
PIN CONNECTIONS
GND GND
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
Figure 1. Typical Isolated Application (Flyback Converter), Enable Brown−out, Ac Line OVP and OPP Functions
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
DRAIN
VCC
VCC Management
VCC OVP
ISTOP Line
Line detection Line Detection
detection TSD enable
enable
S
BO enable Q DRV
AC OVP
R
Feedback control
VFB(REF)
Slope
Sawtooth compensation
RFB(UP)
LEB 1
FB
Current set−point
BO/AC_OVP
OPP Soft−Start GND
Ifreeze IPK(0)
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
iD(t)
< 1.5 x IDS(PK)
< tLEB
IDS(PK)
Transformer
Saturation
t
Figure 4. Spike Limits
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC(ON) VCC increasing level at which the switcher starts operation 1 (2) 8.0 8.4 8.9 V
VCC(MIN) VCC decreasing level at which the HV current source restarts 1 (2) 6.5 6.9 7.3 V
VCC(OFF) VCC decreasing level at which the switcher stops operation (UVLO) 1 (2) 6.1 6.5 6.9 V
VCC(reset) VCC voltage at which the internal latch is reset (Guaranteed by design) 1 (2) 4 V
ICC1 Internal IC consumption, MOSFET switching (fSW = 65 kHz) 1 (2) mA
NCP1075uz − 1.10 −
NCP1076uz/77uz − 1.26 −
NCP1079uz − 1.40 −
ICC(skip) Internal IC consumption, VFB is 0 V (No switching on MOSFET) 1 (2) − 400 − mA
POWER SWITCH CIRCUIT
RDS(ON) Power Switch Circuit on−state resistance (IDRAIN = 50 mA) 5 (4) W
NCP1075uz
TJ = 25°C − 13.5 16.8
TJ = 125°C − 26.0 31.6
NCP1076uz/77uz
TJ = 25°C − 4.8 6.8
TJ = 125°C − 9.3 11.6
NCP1079uz
TJ = 25°C − 2.9 3.9
TJ = 125°C − 5.3 7.5
BVDSS Power Switch Circuit & Start−up breakdown voltage 5 (4) 700 − − V
(IDRAIN(OFF) = 120 mA, TJ = 25°C)
IDSS(OFF) Power Switch & Start−up breakdown voltage off−state leakage current 5 (4) − 85 − mA
TJ = 125°C (VDS = 700 V)
Switching characteristics (RL = 50 W, VDS set for IDRAIN = 0.7 x Ilim) 5 (4) ns
tR Turn−on time (90% − 10%) − 20 −
tF Turn−off time (10% − 90%) − 10 −
INTERNAL START−UP CURRENT SOURCE
Istart1 High−voltage current source, VCC = VCC(ON) – 200 mV 5 (4) 4.0 9.0 12.0 mA
Istart2 High−voltage current source, VCC = 0 V 5 (4) − 0.5 − mA
VHV(MIN) Minimum start−up voltage, VCC = 0 V 5 (4) − 21 − V
VCC(TH) VCC Transient level for Istart1 to Istart2 toggling point 1 (2) − 1.6 − V
CURRENT COMPARATOR
IPK Maximum internal current set−point at 50% duty−cycle mA
FB pin open, TJ = 25°C
NCP1075uz − − 400 −
NCP1076uz − − 650 −
NCP1077uz − − 800 −
NCP1079uz − − 1050 −
IPK(0) Maximum internal current set−point at beginning of switching cycle mA
FB pin open, BO/AC_OVP pin voltage v 0.8 V, TJ = 25°C
NCP1075uz − 420 470 520
NCP1076uz − 690 765 840
NCP1077uz − 850 940 1030
NCP1079uz − 1110 1230 1350
3. The final switch current is: IPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP
the primary inductor in a flyback, and tprop the propagation delay.
4. Oscillator frequency is measured with disabled jittering.
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
CURRENT COMPARATOR
IPKSW(65) Final switch current with a primary slope of 200 mA/ms, mA
fSW = 65 kHz (Note 3)
NCP1075uz − − 450 −
NCP1076uz − − 710 −
NCP1077uz − − 860 −
NCP1079uz − − 1100 −
IPKSW(100) Final switch current with a primary slope of 200 mA/ms, mA
fSW =100 kHz (Note 3)
NCP1075uz − − 440 −
NCP1076uz − − 685 −
NCP1077uz − − 825 −
NCP1079uz − − 1040 −
IPKSW(130) Final switch current with a primary slope of 200 mA/ms, mA
fSW =130 kHz (Note 3)
NCP1075uz − − 450 −
NCP1076uz − − 685 −
NCP1077uz − − 820 −
NCP1079uz − − 1020 −
IPK(OPP) Maximum internal current set−point at beginning of switching cycle mA
FB pin open, BO/AC_OVP pin voltage = 2.65 V, TJ = 25°C
NCP1075uz − − 375 −
NCP1076uz − − 610 −
NCP1077uz − − 750 −
NCP1079uz − − 985 −
tSS Soft−start duration (Guaranteed by design) − − 10 − ms
tprop Propagation delay from current detection to drain OFF state − − 100 − ns
tLEB1 Leading Edge Blanking Duration 1 − − 300 − ns
tLEB2 Leading Edge Blanking Duration 2 (NCP107xuA version only) − − 100 − ns
INTERNAL OSCILLATOR
fOSC(65) Oscillation frequency, 65 kHz version, TJ = 25°C (Note 4) − 59 65 71 kHz
fOSC(100) Oscillation frequency, 100 kHz version, TJ = 25°C (Note 4) − 90 100 110 kHz
fOSC(130) Oscillation frequency, 130 kHz version, TJ = 25°C (Note 4) − 117 130 143 kHz
fjitter Frequency jittering in percentage of fOSC − − ±6 − %
fswing Jittering modulation frequency − − 300 − Hz
DMAX Maximum duty−cycle − 64 68 72 %
FEEDBACK SECTION
IFB(fault) FB current for which Fault is detected 4 (1) − −35 − mA
IFB100% FB current for which internal current set−point is 100% (IPK(0)) 4 (1) − −44 − mA
IFB(freeze) FB current for which internal current set-point is Ifreeze 4 (1) − −90 − mA
VFB(REF) Equivalent pull−up voltage in linear regulation range 4 (1) − 3.3 − V
(Guaranteed by design)
RFB(UP) Equivalent feedback resistor in linear regulation range 4 (1) − 19.5 − kΩ
(Guaranteed by design)
FREQUENCY FOLDBACK & SKIP
IFBfold Start of frequency foldback FB pin current level 4 (1) − −68 − mA
IFBfold(END) End of frequency foldback FB pin current level, fSW = fMIN 4 (1) − −100 − mA
3. The final switch current is: IPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP
the primary inductor in a flyback, and tprop the propagation delay.
4. Oscillator frequency is measured with disabled jittering.
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
FREQUENCY FOLDBACK & SKIP
fMIN The frequency below which skip−cycle occurs, TJ = 25°C (Note 4) − 23 27 31 kHz
IFB(skip) The FB pin current level to enter skip mode 4 (1) − −120 − mA
Ifreeze Internal minimum current set−point (IFB = IFB(freeze)) mA
NCP1075uz − − 165 −
NCP1076uz − − 270 −
NCP1077uz − − 330 −
NCP1079uz − − 430 −
SLOPE COMPENSATION
Sa(65) The internal slope compensation @ 65 kHz: mA/ms
NCP1075uz − − 9 −
NCP1076uz − − 15 −
NCP1077uz − − 18 −
NCP1079uz − − 23 −
Sa(100) The internal slope compensation @ 100 kHz: mA/ms
NCP1075uz − − 14 −
NCP1076uz − − 23 −
NCP1077uz − − 28 −
NCP1079uz − − 36 −
Sa(130) The internal slope compensation @ 130 kHz: mA/ms
NCP1075uz − − 18 −
NCP1076uz − − 30 −
NCP1077uz − − 36 −
NCP1079uz − − 46 −
PROTECTIONS
tSCP Fault validation further to error flag assertion − 35 48 − ms
trecovery OFF phase in fault mode − − 420 − ms
VOVP VCC voltage at which the switcher stops pulsing 1 (5) 17.0 18.0 18.8 V
tOVP The filter of VCC OVP comparator − − 80 − ms
VBO(EN) Brown−out level detection 2 (8) − 50 − mV
VBO(ON) Brown−out level, the switcher starts pulsing, OPP starts to decrease IPK 2 (8) 0.76 0.80 0.84 V
VBO(HYST) Brown−out hysteresis (Guaranteed by design) 2 (8) − 100 − mV
VACOVP(ON) OVP level when the switcher stops pulsing 2 (8) 2.755 2.900 3.045 V
VACOVP(OFF) OVP level when the switcher starts pulsing 2 (8) 2.3 2.6 2.9 V
tBOfilter VBO filter − − 20 − ms
tBO Brown−out timer − − 50 − ms
VHV(EN) The drain pin voltage above which the MOSFET operates. Checked after one 5 (4) 72 91 110 V
of the following events: TSD, UVLO, SCP, or VCC OVP mode, BO/AC_OVP
pin = 0 V
IPK(150) High current protection, percent of max limit IPK (NCP107xuA version only) − − 150 − %
TEMPERATURE MANAGEMENT
TSD Temperature shutdown (Guaranteed by design) − 150 − − °C
TSDHYST Hysteresis in shutdown (Guaranteed by design) − − 20 − °C
3. The final switch current is: IPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP
the primary inductor in a flyback, and tprop the propagation delay.
4. Oscillator frequency is measured with disabled jittering.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
TYPICAL CHARACTERISTICS
8.50 6.98
6.96
8.45 6.94
6.92
VCC(min) (V)
VCC(on) (V)
8.40 6.90
6.88
8.35 6.86
6.84
8.30 6.82
6.80
8.25 6.78
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. VCC(on) vs. Temperature Figure 6. VCC(min) vs. Temperature
6.49 130
120
6.48
110
6.47 100
IDSS(off) (mA)
VCC(off) (V)
90
6.46
80
6.45
70
6.44 60
50
6.43
40
6.42 30
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 7. VCC(off) vs. Temperature Figure 8. IDSS(off) vs. Temperature
1.16 1.28
1.14 1.27
1.26
1.12
ICC1(1076uz/77uz) (mA)
1.25
ICC1(1075uz) (mA)
1.10 1.24
1.08 1.23
1.06 1.22
1.21
1.04
1.20
1.02 1.19
1.00 1.18
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. ICC1(1075uz) vs. Temperature Figure 10. ICC1(1076uz/77uz) vs. Temperature
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
TYPICAL CHARACTERISTICS
1.39 460
1.37
1.35 450
ICC1(1079uz) (mA)
IPK(0)1075uz (mA)
1.33
1.31
440
1.29
1.27
1.25 430
1.23
1.21 420
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 11. ICC1(1079uz) vs. Temperature Figure 12. IPK(0)1075uz vs. Temperature
780 960
940
760
IPK(0)1076uz (mA)
IPK(0)1077uz (mA)
920
740
900
720
880
700
860
680 840
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 13. IPK(0)1076uz vs. Temperature Figure 14. IPK(0)1077uz vs. Temperature
1200 12
10
1160
IPK(0)1079uz (mA)
8
ISTART1 (mA)
1120
6
1080
4
1040
2
1000 0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 15. IPK(0)1079uz vs. Temperature Figure 16. ISTART1 vs. Temperature
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TYPICAL CHARACTERISTICS
0.65 30
0.60 NCP1075uz
25
0.55
20
ISTART2 (mA)
0.50
RDS(on) (W)
0.45 15
0.40
10 NCP1076uz/77uz
0.35
5 NCP1079uz
0.30
0.25 0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 17. ISTART2 vs. Temperature Figure 18. RDS(on) vs. Temperature
66 99
98
65
97
64
fOSC100 (kHz)
fOSC65 (kHz)
96
63 95
94
62
93
61
92
60 91
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 19. fOSC65 vs. Temperature Figure 20. fOSC100 vs. Temperature
131 67.5
129
67.4
127
fOSC130 (kHz)
DMAX (%)
125 67.3
123
67.2
121
119 67.1
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 21. fOSC130 vs. Temperature Figure 22. DMAX vs. Temperature
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
TYPICAL CHARACTERISTICS
28.0 380
375
27.5
tRECOVERY (ms)
370
fMIN (kHz)
27.0 365
360
26.5
355
26.0 350
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 23. fMIN vs. Temperature Figure 24. tRECOVERY vs. Temperature
52 18.4
51 18.3
18.2
tSCP (ms)
50
VOVP (V)
49 18.1
48 18.0
47 17.9
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 25. tSCP vs. Temperature Figure 26. VOVP vs. Temperature
92 0.810
91
0.805
90
VHV(en) (V)
VBO(on) (V)
0.800
89
0.795
88
87 0.790
86 0.785
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 27. VHV(en) vs. Temperature Figure 28. VBO(on) vs. Temperature
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
TYPICAL CHARACTERISTICS
2.99 2.620
2.97 2.615
2.95
2.610
VACOVP(on) (V)
VACOVP(off) (V)
2.93
2.605
2.91
2.600
2.89
2.87 2.595
2.85 2.590
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 29. VACOVP(on) vs. Temperature Figure 30. VACOVP(off) vs. Temperature
1.100 10
NCP1079uz
1.075
8
BVDSS/BVDSS(25°C) [−]
1.050
IDS(pk) (A)
6 NCP1076uz/77uz
1.025
1.000
4
0.975
NCP1075uz
2
0.950
0.925 0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 31. BVDSS/BVDSS(255C) vs. Figure 32. Drain Current Peak during
Temperature Transformer Saturation vs. Junction
Temperature
1.7
NCP1079uz
1.6
1.5 NCP1076uz/77uz
ICC1 (mA)
1.4
1.3
NCP1075uz
1.2
1.1
1.0
7 8 9 10 11 12 13 14 15 16 17
VCC (V)
Figure 33. ICC1 vs. VCC
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
APPLICATION INFORMATION
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
9
8.4 V
8
6 6.9 V
VCC
5
V [V]
4
Device
Internal
3 Pulses
VCC(TH)
2
0
0 1 2 3 4 5 6 7 8
Startup Duration time [ms]
Figure 35. The Charge / Discharge Cycle Over a 1 mF VCC Capacitor
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
As one can see, even if there is auxiliary winding to controller includes a novel circuitry made of two start−up
provide energy for VCC, it happens that the device is still levels, Istart1 and Istart2. At power−up, as long as VCC is
biased by DSS during start−up time or some fault mode below a 1.6 V level, the source delivers Istart2 (around
when the voltage on auxiliary winding is not ready yet. The 500 mA typical), then, when VCC reaches 1.6 V, the source
VCC capacitor shall be dimensioned to avoid VCC crosses smoothly transitions to Istart1 and delivers its nominal value.
VCC(OFF) level, which stops operation. The ΔV between As a result, in case of short−circuit between VCC and GND,
VCC(MIN) and VCC(OFF) is 0.5 V. There is no current source the power dissipation will drop to 370 x 500 x 10−6 =
to charge VCC capacitor when driver is on, i.e. drain voltage 185 mW. Figure 35 portrays this particular behavior.
is close to zero. Hence the VCC capacitor can be calculated The first start−up period is calculated by the formula
using C x V = I x t, which implies a 1 x 10−6 x 1.6
6
/ (500 x 10− ) = 3.2 ms start−up time for the first sequence.
I CC1 @ D MAX
C VCC w (eq. 1) The second sequence is obtained by toggling the source to
f OSC @ DV
8.9 mA with a ΔV of VCC(ON) − VCC(TH) =
Take the 65 kHz device as an example. CVCC should be 8.4 V – 1.6 V = 6.8 V, which finally leads to a second
above start−up time of 1 x 10−6 x 6.8 / (8.9 x 10−3) = 0.76 ms.
C VCC + 1.45 @ 10 3 @ 0.73 + 36 nF
−3
The total start−up time becomes 3.2 ms + 0.76 ms =
59 @ 10 @ 0.5 3.96 ms. Please note that this calculation is approximated by
A margin that covers the temperature drift and the voltage the presence of the knee in the vicinity of the transition.
drop due to switching inside FET should be considered, and
thus a capacitor above 0.1 mF is appropriate. Fault Condition – Output Short−circuit
The VCC capacitor has only a supply role and its value As soon as VCC reaches VCC(ON), drive pulses are
does not impact other parameters such as fault duration or internally enabled. If everything is correct, the auxiliary
the frequency sweep period for instance. As one can see on winding increases the voltage on the VCC pin as the output
Figure 34, an internal OVP comparator protects the switcher voltage rises. During the start−sequence, the controller
against lethal VCC runaways. This situation can occur if the smoothly ramps up the peak drain current to maximum
feedback loop opto−coupler fails, for instance, and you setting, i.e. IPK, which is reached after a typical period of
would like to protect the converter against an over−voltage 10 ms. When the output voltage is not regulated, the current
event. In that case, the over−voltage protection (OVP) coming through FB pin is below IFBfault level (35 mA
circuit immediately stops the output pulses for trecovery typically), which is not only during the start−up period but
duration (420 ms typically). Then a new start−up attempt also anytime an overload occurs, an internal error flag is
takes place to check whether the fault has disappeared or not. asserted, IpFlag, indicating that the system has reached its
The OVP paragraph gives more design details on this maximum current limit set−point. The assertion of this flag
particular section. triggers a fault counter tSCP (48 ms typically). If at counter
completion, IpFlag remains asserted, all driving pulses are
Fault Condition – Short−circuit on VCC stopped and the part stays off in trecovery duration (about
In some fault situations, a short−circuit can purposely 420 ms). A new attempt to re−start occurs and will last
occur between VCC and GND. In high line conditions 48 ms providing the fault is still present. If the fault still
(VHV = 370 V dc) the current delivered by the start−up affects the output, a safe burst mode is entered, affected by
device will seriously increase the junction temperature. For a low duty−cycle operation (11%). When the fault
instance, since Istart1 equals 4.9 mA (the min corresponds to disappears, the power supply quickly resumes operation.
the highest TJ), the device would dissipate Figure 36 depicts this particular mode:
370 x 4.9 x 10−3 = 1.81 W. To avoid this situation, the
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
VCC(ON)
VCC(MIN)
VCC
IpFlag
Open loop FB
VFB 48 ms typ.
Fault level
Timer
420 ms typ.
DRV
internal
Figure 36. In Case of Short−circuit or Overload, the NCP107xuz Protects Itself and the Power Supply Via a Low
Frequency Burst Mode. The VCC is Maintained by the Current Source and Self−supplies the Controller.
DRAIN
Shut down
Internal DRV CVCC CAUX N AUX
80 ms
filter V OVP GND
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
VOVP
VCC(ON)
VCC(MIN)
VCC
I FB
48 ms typ.
Fault level
Timer
420 ms typ.
DRV
internal
Figure 38. Describes the Main Signal Variations When the Part Operates in Auto−recovery OVP
VCC VCC(ON)
0V (fresh PON)
10 ms
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
Jittering
Frequency jittering is a method used to soften the EMI sawtooth is internally generated and modulates the clock up
signature by spreading the energy in the vicinity of the main and down with a fixed frequency of 300 Hz. Figure 40 shows
switching component. The NCP107xuz offers a ±6% the relationship between the jitter ramp and the frequency
deviation of the nominal switching frequency. The sweeping deviation. It is not possible to externally disable the jitter.
Jitter ramp
68.9 kHz
65 kHz
Figure 40. Modulation Effects on the Clock Signal by the Jittering Sawtooth
Line Detection If the drain voltage is lower than the internal threshold
When BO/AC_OVP pin is grounded (voltage on this pin VHV(EN) (91 V dc typically), the internal power switch is
is below VBO(EN)) Figure 2, then an internal comparator inhibited. This avoids operating at too low ac input.
monitors the drain voltage as recovering from one of the
following situations: Brown−out Function, Ac Line Over−voltage Protection
• Short−Circuit Protection, The Brown−out circuitry offers a way to protect the
application from operation under too low an input voltage.
• VCC OVP is Confirmed, Below a given level, the controller blocks the output pulses,
• UVLO above it, it authorizes them. The internal circuitry, depicted
• TSD by Figure 41, offers a way to observe the high−voltage (HV)
rail.
VBULK
RUPPER BO/AC_OVP
20μs Line
detection
filter
RLOWER disable
CBO
VBO(EN)
20μs
tBO BO enable
filter
VBO(ON)
20μs
AC OVP
filter
VAC(OVP)
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
A resistive divider made of RUPPER and RLOWER, brings higher than VBO(ON), switcher starts pulsing. If voltage falls
a portion of the HV rail on BO/AC_OVP pin. Below the down under VBO(OFF) − level VBO(ON) minus VBO(HYST),
VBO(EN) = 50 mV is the Brown−out function disabled, over the switcher waits 50 ms and then stops pulsing, depicted by
the VBO(EN) Brown−out function is enable and against Line Figure 42. Bulk voltage at which IC starts switching is set by
detection is inhibited. If voltage on BO/AC_OVP pin is resistive divider.
VCC(ON)
VCC(MIN)
VCC
VBO(ON)
V BO(OFF)
V BO/AC_OVP
50 ms 50 ms
Timer
DRV
internal
Figure 42. Brown−out Input Functionality with 50 ms Timer
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
The IC also includes over−voltage protection. If the voltage on BO/AC_OVP pin exceed VACOVP(ON), the switcher
immediately stops pulsing until the voltage on BO/AC_OVP pin drops under VACOVP(OFF), depicted by Figure 43.
VCC(ON)
VCC(MIN)
VCC
VACOVP(ON)
VAVOVP(OFF)
VBO(ON)
VBO(OFF)
VBO/AC_OVP
DRV
internal
7.1 @ 10
Then power losses on resistive divider for worst case (VBULK = 409 V dc)
2 U2 409 2
P+U@I+U + + + 12 mW (eq. 3)
R R UPPER ) R LOWER 14 @ 10 6 ) 100 @ 10 3
For VBULK(ON) = 113 V dc will be over−voltage protection (voltage when the switcher stops pulsing):
R LOWER ) R UPPER V BULK(ON)
V BULK(OVP) + V ACOVP(ON) @ + V ACOVP(ON) @ + 29 @ 113 + 409 Vdc + 290 Vrms (eq. 4)
R LOWER V BO(ON) 0.8
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
VCC(ON)
VCC(MIN)
VCC
VBO(ON)
VBO(OFF)
VBO/AC_OVP
50 ms
Timer
Soft−start Soft−start
Drain
current
If voltage on VCC pin is higher than VCC(ON) and voltage around 68 mA. At this point, the oscillator enters frequency
on BO/AC_OVP pin is higher than VBO(ON) then IC starts foldback and reduces its switching frequency.
pulsing, drain current is increasing for 10 ms (Soft−start). The internal peak current set−point is following the
Brown−out is inhibited during Soft−start, when Soft−start feedback current information until its level reaches the
ended, Brown−out checked if is voltage on BO/AC_OVP minimal freezing level point of Ifreeze. Below this value, the
pin higher than VBO(OFF). If the voltage is lower, timer count peak current set−point is frozen to 30% of the IPK(0). The
50 ms and if the voltage don’t increase over VBO(OFF) then only way to further reduce the transmitted power is to
IC stops switching as one can see on Figure 44. diminish the operating frequency down to fMIN (27 kHz
typically). This value is reached at a feedback current level
Frequency Foldback of IFBfold(END) (100 mA typically). Below this point, if the
The reduction of no−load standby power associated with output power continues to decrease, the part enters skip
the need for improving the efficiency, requires to change the cycle for the best noise−free performance in no−load
traditional fixed−frequency type of operation. This device conditions. Figures 45 and 46 depict the adopted scheme for
implements a switching frequency folback when the the part.
feedback current passes above a certain level, IFBfold, set
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
140
130 kHz
120
100 kHz
100 65 kHz
Frequency [kHz] 80
60
40
20
0
50 60 70 80 90 100
IFB [mA]
Figure 45. By Observing the Current on the FB pin, the Controller Reduces its
Switching Frequency for an Improved Performance at Light Load
1400
NCP1079uz
1200 NCP1077uz
Current set point [mA]
1000 NCP1076uz
NCP1075uz
800
600
400
200
0
40 50 60 70 80 90 100 110
IFB [mA]
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
Figure 47 depicts the skip mode block diagram. When the comparator is minimized to lower the ripple of the auxiliary
FB current information reaches IFB(skip), the internal clock voltage for VCC pin and VOUT of power supply during skip
to set the flip−flop is blanked and the internal consumption mode. It easies the design of VCC overload range.
of the controller is decreased. The hysteresis of internal skip
Jittering OSC
V FB (REF ) S
Foldback
Q DRV stage
R
R FB (UP )
IFB (skip )
SKIP
FB CS comparator
Over−power Protection
This function lets you limit the maximum dc output current regardless of the operating input voltage. For a correct operation,
the BO/AC_OVP pin must be connected via a resistive divider to observe the bulk voltage.
OSC
S
MOSFET
Q
R
Vramp + Vsense
VBULK
IFB
IFB to CS setpoint
RUPPER
Ifreeze IPK(0)
BO/AC_OVP IPK (0)
IPK (OPP )
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
1300
1200
There are several known ways to implement Over−power Maximum peak current is reduced internally according to
Protection (OPP), all suffering from particular problems. bulk voltage. When VBO(OPP) is maximum, the peak current
These problems range from the added consumption burden set−point is reduced by 10%. Bulk voltage at which will be
on the converter or the skip−cycle disturbance brought by maximum current peak reduced by 20% (10% in
the current−sense offset. In this case is added consumption NCP1075uz):
due to resistive divider (Equation 2).
(eq. 5)
R ) R UPPER
V BULK(ON)
+ 2.65 @ 100 @ 10 ) 143 @ 10 + 375 Vdc + 265 Vrms
3 6
V BULK(OPP) + V BO(OPP) @ + V BO(OPP) @ LOWER
V BO(ON) R LOWER 100 @ 10
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
Second LEB – Peak Current Protection (NCP107xuA Slope Compensation and IPK Set−point
only) In order to let the NCP107xuz operate in CCM with a
There is a second level of current protection with 100 ns duty−cycle above 50%, a fixed slope compensation is
propagation delay to prevent IC against high peak current. internally applied to the current−mode control.
If peak current is 150% max peak current limit, then the Below appears a table of the slope compensation level, the
controller stops switching after three pulses and waits for an initial current set−point, and the final current set−point of
auto−recovery period (trecovery) before attempting to different versions of switcher.
re−start.
Figure 50 depicts the variation of IPK set−point vs. the power switcher duty ratio, which is caused by the internal ramp
compensation.
1400
1200
1000
IIPK set-point [mA]
800 NCP1079uz
600 NCP1077uz
NCP1076uz
400
NCP1075uz
200
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Duty Ratio [%]
Figure 50. IPK Set−point varies with Power Switch On Time, which is Caused by the Ramp Compensation
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
design, we have selected our maximum voltage 5. To obtain the primary inductance, we have the
around 650 V (at VIN = 375 V dc). This voltage is choice between two equations:
given by the RCD clamp installed from the drain to
ǒV IN @ DǓ
2
If we take the maximum RDS(ON) for a 125°C junction temperature, i.e. 10.1 W, then conduction losses worse case are:
P COND + I D,RMS 2 @ R DS(ON) + ǒ154 @ 10 −3Ǔ @ 13.6 + 323 mW
2
(eq. 15)
7. Off−time and on−time switching losses can be estimated based on the following calculations:
I PEAK @ (V BULK ) V CLAMP) @ t F 0.335 @ (127 ) 120 @ 2) @ 10 @ 10 −9
P OFF + + + 40 mW (eq. 16)
2 @ T SW 2 @ 15.4 @ 10 −6
Where, assume the VCLAMP is equal to 2 times of reflected voltage.
I VALLEY @ ǒV BULK ) N @ (V OUT ) V F)Ǔ @ t R 0.112 @ (127 ) 100) @ 20 @ 10 −9
P ON + + + 5.5 mW (eq. 17)
6 @ T SW 6 @ 15.4 @ 10 −6
It is noted that the overlap of voltage and current seen on MOSFET during turning on and off duration is dependent on the
snubber and parasitic capacitance seen from drain pin. Therefore the tF and tR in Equations 16 and 17 have to be modified after
measuring on the bench.
8. The theoretical total power is then
P MOSFET + 323 ) 40 ) 5.5 + 368.5 mW
9. If the NCP107xuz operates at DSS mode, then the losses caused by DSS mode should be counted as losses of this
device on the following calculation:
P DSS + I CC1 @ V IN,MAX + 1.5 @ 10 −3 @ 375 + 563 mW (eq. 18)
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
MOSFET Protection
As in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the MOSFET BVDSS which
is 700 V. Figure 53 a−b−c present possible implementations:
Figure 53a: the simple capacitor limits the voltage and a MUR160 represents a good choice. One major
according to the lateral MOSFET body−diode shall never be drawback of the RCD network lies in its dependency upon
forward biased, either during start−up (because of a large the peak current. Worse case occurs when IPEAK and VIN are
leakage inductance) or in normal operation as shown by maximum and VOUT is close to reach the steady−state value.
Figure 51. This condition sets the maximum voltage that can Figure 53c: this option is probably the most expensive of
be reflected during tF. As a result, the flyback voltage which all three but it offers the best protection degree. If you need
is reflected on the drain at the switch opening cannot be a very precise clamping level, you must implement a Zener
larger than the input voltage. When selecting components, diode or a TVS. There are little technology differences
you must adopt a turn ratio which adheres to the following behind a standard Zener diode and a TVS. However, the die
Equation 6. This option is only valid for low power area is far bigger for a transient suppressor than that of Zener.
applications, e.g. below 5 W, otherwise chances exist to A 5 W Zener diode like the 1N5388B will accept 180 W
destroy the MOSFET. After evaluating the leakage peak power if it lasts less than 8.3 ms. If the peak current in
inductance, you can compute C with (Equation 7). Typical the worse case (e.g. when the PWM circuit maximum
values are between 100 pF and up to 470 pF. Large current limit works) multiplied by the nominal zener voltage
capacitors increase capacitive losses... exceeds these 180 W, then the diode will be destroyed when
Figure 53b: the most standard circuitry is called the RCD the supply experiences overloads. A transient suppressor
network. You calculate RCLAMP and CCLAMP using the like the P6KE200 still dissipates 5 W of continuous power
following formulae: but is able to accept surges up to 600 W @ 1 ms. Select the
2 @ V CLAMP ǒV CLAMP ) (V OUT ) V F) @ NǓ
Zener or TVS clamping level between 40 to 80 volts above
R CLAMP + the reflected output voltage when the supply is heavily
L LEAK @ I LEAK 2 @ f SW (eq. 19) loaded.
V CLAMP As a good design practice, it is recommended to
C CLAMP + (eq. 20) implement one of this protection to ensure a maximum drain
V RIPPLE @ f SW @ R CLAMP
pin voltage below 650 V (to have some margin between
VCLAMP is usually selected 50−80 V above the reflected drain pin voltage and BVDSS) during most stringent
value N x (VOUT + VF ). The diode needs to be a fast one operating conditions (high VIN and peak power condition).
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
Bill of Material:
C1 Bulk capacitor, input dc voltage is
connected to the capacitor
C2, R1, D1 Clamping elements
C3 VCC capacitor
OK1 Opto−coupler
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
ORDERING INFORMATION
Frequency RDS(ON) IPK
Device [kHz] [W] [mA] Soft−start Package Type Shipping
NCP1075AAP065G 65 13.5 400 enabled PDIP8 (Less pin#6)
NCP1075AAP100G 100 13.5 400 enabled PDIP8 (Less pin#6)
NCP1075BAP065G 65 13.5 400 enabled PDIP8 (Less pin#3)
NCP1075BAP100G 100 13.5 400 enabled PDIP8 (Less pin#3)
NCP1075BAP130G 130 13.5 400 enabled PDIP8 (Less pin#3)
NCP1076AAP065G 65 4.8 650 enabled PDIP8 (Less pin#6)
NCP1076AAP100G 100 4.8 650 enabled PDIP8 (Less pin#6)
NCP1076BAP065G 65 4.8 650 enabled PDIP8 (Less pin#3)
NCP1076BAP100G 100 4.8 650 enabled PDIP8 (Less pin#3)
NCP1076BAP130G 130 4.8 650 enabled PDIP8 (Less pin#3)
NCP1077AAP065G 65 4.8 800 enabled PDIP8 (Less pin#6)
NCP1077AAP100G 100 4.8 800 enabled PDIP8 (Less pin#6)
NCP1077BAP065G 65 4.8 800 enabled PDIP8 (Less pin#3)
NCP1077BAP100G 100 4.8 800 enabled PDIP8 (Less pin#3)
NCP1077BAP130G 130 4.8 800 enabled PDIP8 (Less pin#3)
NCP1079AAP065G 65 2.9 1050 enabled PDIP8 (Less pin#6)
NCP1079AAP100G 100 2.9 1050 enabled PDIP8 (Less pin#6)
NCP1079BAP065G 65 2.9 1050 enabled PDIP8 (Less pin#3)
NCP1079BAP100G 100 2.9 1050 enabled PDIP8 (Less pin#3)
NCP1079BAP130G 130 2.9 1050 enabled PDIP8 (Less pin#3) 50 Units /
NCP1075ABP065G 65 13.5 400 disabled PDIP8 (Less pin#6) Rail
NCP1075ABP100G 100 13.5 400 disabled PDIP8 (Less pin#6)
NCP1075BBP065G 65 13.5 400 disabled PDIP8 (Less pin#3)
NCP1075BBP100G 100 13.5 400 disabled PDIP8 (Less pin#3)
NCP1075BBP130G 130 13.5 400 disabled PDIP8 (Less pin#3)
NCP1076ABP065G 65 4.8 650 disabled PDIP8 (Less pin#6)
NCP1076ABP100G 100 4.8 650 disabled PDIP8 (Less pin#6)
NCP1076BBP065G 65 4.8 650 disabled PDIP8 (Less pin#3)
NCP1076BBP100G 100 4.8 650 disabled PDIP8 (Less pin#3)
NCP1076BBP130G 130 4.8 650 disabled PDIP8 (Less pin#3)
NCP1077ABP065G 65 4.8 800 disabled PDIP8 (Less pin#6)
NCP1077ABP100G 100 4.8 800 disabled PDIP8 (Less pin#6)
NCP1077BBP065G 65 4.8 800 disabled PDIP8 (Less pin#3)
NCP1077BBP100G 100 4.8 800 disabled PDIP8 (Less pin#3)
NCP1077BBP130G 130 4.8 800 disabled PDIP8 (Less pin#3)
NCP1079ABP065G 65 2.9 1050 disabled PDIP8 (Less pin#6)
NCP1079ABP100G 100 2.9 1050 disabled PDIP8 (Less pin#6)
NCP1079BBP065G 65 2.9 1050 disabled PDIP8 (Less pin#3)
NCP1079BBP100G 100 2.9 1050 disabled PDIP8 (Less pin#3)
NCP1079BBP130G 130 2.9 1050 disabled PDIP8 (Less pin#3)
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
PACKAGE DIMENSIONS
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NCP1075A/B, NCP1076A/B, NCP1077A/B, NCP1079A/B
PACKAGE DIMENSIONS
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33