NCP1203 PWM Current-Mode Controller For Universal Off-Line Supplies Featuring Standby and Short Circuit Protection
NCP1203 PWM Current-Mode Controller For Universal Off-Line Supplies Featuring Standby and Short Circuit Protection
NCP1203 PWM Current-Mode Controller For Universal Off-Line Supplies Featuring Standby and Short Circuit Protection
PWM Current-Mode
Controller for Universal
Off-Line Supplies Featuring
Standby and Short Circuit
Protection www.onsemi.com
Housed in SOIC−8 or PDIP−8 package, the NCP1203 represents a
major leap toward ultra−compact Switchmode Power Supplies and MARKING
represents an excellent candidate to replace the UC384X devices. Due DIAGRAM
to its proprietary SMARTMOS™ Very High Voltage Technology, the
circuit allows the implementation of complete off−line AC−DC 8
adapters, battery charger and a high−power SMPS with few external SOIC−8 203Dx
components. 8 D1, D2 SUFFIX ALYW
CASE 751 G
With an internal structure operating at a fixed 40 kHz, 60 kHz or 1
100 kHz switching frequency, the controller features a high−voltage 1
startup FET which ensures a clean and loss−less startup sequence. Its
x = 4, 6, or 1
current−mode control naturally provides good audio−susceptibility
A = Assembly Location
and inherent pulse−by−pulse control. L = Wafer Lot
When the current setpoint falls below a given value, e.g. the output Y = Year
power demand diminishes, the IC automatically enters the so−called W = Work Week
skip cycle mode and provides improved efficiency at light loads G = Pb−Free Package
while offering excellent performance in standby conditions. Because
this occurs at a user adjustable low peak current, no acoustic noise 8
takes place.
PDIP−8 1203Pxx
The NCP1203 also includes an efficient protective circuitry which, N SUFFIX AWL
in presence of an output over load condition, disables the output CASE 626 YYWWG
8
pulses while the device enters a safe burst mode, trying to restart.
1 1
Once the default has gone, the device auto−recovers. Finally, a
temperature shutdown with hysteresis helps building safe and robust xx = 40, 60, or 100
power supplies. A = Assembly Location
WL = Wafer Lot
Features YY = Year
• High−Voltage Startup Current Source WW = Work Week
G = Pb−Free Package
• Auto−Recovery Internal Output Short−Circuit Protection
• Extremely Low No−Load Standby Power
• Current−Mode with Adjustable Skip−Cycle Capability PIN CONNECTIONS
• Internal Leading Edge Blanking
• 250 mA Peak Current Capability Adj 1 8 HV
* VOUT
Aux. +
+
NCP1203
Adj HV
1 8
FB
2 7
EMI CS VCC
3 6
FILTER GND Drv
4 5
UNIVERSAL
INPUT +
2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. Skip cycle occurs when
FB falls below Vpin1.
3 CS Current sense input This pin senses the primary current and routes it to the internal comparator
via an L.E.B.
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NCP1203
Adj HV
1 8
HV CURRENT
SOURCE
80 k SKIP CYCLE
FB 1.2 V COMPARATOR NC
+
2 - UVLO HIGH AND LOW 7
INTERNAL VCC INTERNAL REGULATOR
24 k
CURRENT
Q FLIP−FLOP
SENSE VCC
DCmax = 80%
250 ns 40−60−100 kHz SET Q OVERLOAD
3 6
L.E.B. CLOCK MANAGEMENT
RESET
20 k 57 k +
-
GROUND Drv
VREF
4 + 25 k 1V ±250 mA 5
−
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC, Drv 16 V
Power Supply Voltage on all other pins except Pin 5 (Drv), Pin 6 (VCC) and Pin 8 (HV) − −0.3 to 10 V
Maximum Current into all pins except Pin 6 (VCC) and Pin 8 (HV) when − 5.0 mA
10 V ESD diodes are activated
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NCP1203
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted.)
Characteristic Symbol Pin Min Typ Max Unit
Drive Output
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Tr 5 − 67 − ns
Output Signal
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Tf 5 − 28 − ns
Output Signal
Source Resistance ROH 5 27 40 61 W
Sink Resistance ROL 5 5.0 10 20 W
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NCP1203
14.0 8.4
13.8
8.2
VCC(on) THRESHOLD (V)
13.6
13.2
7.8
13.0
12.8 7.6
12.6
7.4
12.4
12.2 7.2
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
900 2.0
860 1.9
820 1.8 100 kHz
780 1.7
740 1.6
700 1.5 60 kHz
660 1.4
620 1.3
580 1.2
540 1.1
40 kHz
500 1.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. IC Current Consumption (No Load) Figure 6. ICC Consumption (Loaded by 1 nF)
versus Temperature versus Temperature
8.0 400
7.5
HV CURRENT SOURCE (mA)
60 kHz 350
7.0
ICC @ VCC = 6 V (mA)
6.5
300
40 kHz
6.0
5.5 250
5.0
100 kHz 200
4.5
4.0 150
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
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NCP1203
60 20
DRIVE SOURCE RESISTANCE (W)
55 18
40 12
35 10
30 8
25 6
20 4
15 2
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. Drive Source Resistance versus Figure 10. Drive Sink Resistance versus
Temperature Temperature
0.99 120
MAXIMUM CURRENT SETPOINT (V)
0.97 100
100 kHz
f, FREQUENCY (kHz)
0.95
80
0.93 60 kHz
60
0.91
40
0.89 40 kHz
0.87 20
0.85 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 11. Maximum Current Setpoint versus Figure 12. Frequency versus Temperature
Temperature
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NCP1203
APPLICATION INFORMATION
8 HV
12.8 V/4.9 V +
- 6 mA or 0
CVCC Aux
Figure 13. The Current Source Brings VCC Above 12.8 V and then Turns Off
11.5
10.5
9.5
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NCP1203
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NCP1203
12.8 V
7.8 V
VCC
4.9 V
DRIVING PULSES
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NCP1203
Power P1
Power P2
Power P3
MAX PEAK
300 M CURRENT
100 M
Figure 18. The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise−Free Operation
We recommend a pin 1 operation between 400 mV and disappeared. This option can easily be accomplished
1.3 V that will fix the skip peak current level between through a single NPN bipolar transistor wired between FB
120 mV/Rsense and 390 mV/Rsense. and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
Non−Latching Shutdown pin 1. As soon as FB is relaxed, the IC resumes its operation.
In some cases, it might be desirable to shut off the part Figure 19 depicts the application example.
temporarily and authorize its restart once the default has
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NCP1203
1 8
2 7
3 6
ON/OFF Q1
4 5
Figure 19. Another Way of Shutting Down the IC without a Definitive Latch−Off State
Full Latching Shutdown When the VCC level exceeds the zener breakdown voltage,
Other applications require a full latching shutdown, e.g. the NPN biases the PNP and fires the equivalent SCR,
when an abnormal situation is detected (overtemperature or permanently bringing down the FB pin. The switching
overvoltage). This feature can easily be implemented pulses are disabled until the user unplugs the power supply.
through two external transistors wired as a discrete SCR.
Rhold
OVP 12 k
NCP1203
10 k
1 8
2 7
3 6
4 5 CVCC LAux
0.1 mF 10 k
Figure 20. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP
Rhold ensures that the SCR stays on when fired. The bias pin is often the seat of such spurious signals, the
current flowing through Rhold should be small enough to let high−voltage pin can also be the source of problems in
the VCC ramp up (12.8 V) and down (4.9 V) when the SCR certain circumstances. During the turn−off sequence, e.g.
is fired. The NPN base can also receive a signal from a when the user un−plugs the power supply, the controller is
temperature sensor. Typical bipolars can be MMBT2222 still fed by its VCC capacitor and keeps activating the
and MMBT2907 for the discrete latch. The MMBT3946 MOSFET ON and OFF with a peak current limited by
features two bipolars NPN+PNP in the same package and Rsense. Unfortunately, if the quality coefficient Q of the
could also be used. resonating network formed by Lp and Cbulk is low (e.g. the
MOSFET Rdson + Rsense are small), conditions are met to
Protecting the Controller Against Negative Spikes make the circuit resonate and thus negatively bias the
As with any controller built upon a CMOS technology, it controller. Since we are talking about ms pulses, the amount
is the designer’s duty to avoid the presence of negative of injected charge (Q = I x t) immediately latches the
spikes on sensitive pins. Negative signals have the bad habit controller which brutally discharges its VCC capacitor. If this
to forward bias the controller substrate and induce erratic VCC capacitor is of sufficient value, its stored energy
behaviors. Sometimes, the injection can be so strong that damages the controller. Figure 21 depicts a typical negative
internal parasitic SCRs are triggered, engendering shot occurring on the HV pin where the brutal VCC discharge
irremediable damages to the IC if they are a low impedance testifies for latchup.
path is offered between VCC and GND. If the current sense
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NCP1203
Figure 21. A negative spike takes place on the Bulk capacitor at the switch−off sequence
Simple and inexpensive cures exist to prevent from Another option (Figure 23) consists in wiring a diode from
internal parasitic SCR activation. One of them consists in VCC to the bulk capacitor to force VCC to reach UVLOlow
inserting a resistor in series with the high−voltage pin to sooner and thus stops the switching activity before the bulk
keep the negative current to the lowest when the bulk capacitor gets deeply discharged. For security reasons, two
becomes negative (Figure 22). Please note that the negative diodes can be connected in series.
spike is clamped to –2 x Vf due to the diode bridge. Also, the
power dissipation of this resistor is extremely small since it
only heats up during the startup sequence.
Rbulk
> 4.7 k
1 8 D3
1 8 +
+ Cbulk 2 7 1N4007
Cbulk 2 7
3 6
3 6
+ +
4 5 CVCC
4 5 CVCC
Figure 22. A simple resistor in series avoids any Figure 23. or a diode forces VCC to reach
latchup in the controller UVLOlow sooner
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NCP1203
ORDERING INFORMATION
Device Package Shipping†
NCP1203P40G PDIP−8 50 Units / Rail
(Pb−Free)
NCP1203D40R2G SOIC−8 2500 Units / Tape & Reel
(Pb−Free)
NCP1203P60G PDIP−8 50 Units / Rail
(Pb−Free)
NCP1203D60R2G SOIC−8 2500 Units / Tape & Reel
(Pb−Free)
NCP1203P100G PDIP−8 50 Units / Rail
(Pb−Free)
NCP1203D100R2G SOIC−8 2500 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1203
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE N
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
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NCP1203
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT* S 5.80 6.20 0.228 0.244
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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