1207A-ON Semiconductor
1207A-ON Semiconductor
1207A-ON Semiconductor
kr
NCP1207A
PWM Current−Mode
Controller for Free Running
Quasi−Resonant Operation
The NCP1207A combines a true current mode modulator and a
demagnetization detector to ensure full borderline/critical Conduction
Mode in any load/line conditions and minimum drain voltage http://onsemi.com
switching (Quasi−Resonant operation). Due to its inherent skip cycle
capability, the controller enters burst mode as soon as the power MARKING
demand falls below a predetermined level. As this happens at low peak DIAGRAMS
current, no audible noise can be heard. An internal 8.0 s timer
prevents the free−run frequency to exceed 100 kHz (therefore below 8
the 150 kHz CISPR−22 EMI starting limit), while the skip adjustment SO−8 1207A
D1, D2 SUFFIX ALYW
capability lets the user select the frequency at which the burst foldback 8 CASE 751
takes place. 1
1
The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
8
supply the NCP1207A. This feature is particularly useful in
PDIP−8
applications where the output voltage varies during operation (e.g. N SUFFIX
1207AP
battery chargers). Due to its high−voltage technology, the IC is CASE 626
AWL
directly connected to the high−voltage DC rail. As a result, the 8 YYWW
short−circuit trip point is not dependent upon any VCC auxiliary level. 1 1
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast 1207A/P = Device Code
Overvoltage Protection (OVP). Once an OVP has been detected, the A = Assembly Location
IC permanently latches off. WL, L = Wafer Lot
Finally, the continuous feedback signal monitoring implemented YY, Y = Year
with an overcurrent fault protection circuitry (OCP) makes the final WW, W = Work Week
design rugged and reliable.
Features PIN CONNECTIONS
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation
Dmg 1 8 HV
• Current−Mode with Adjustable Skip−Cycle Capability
2 7
• No Auxiliary Winding VCC Operation
FB NC
NCP1207A
Vout
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Description
1 Demag Core reset detection and OVP The auxiliary FLYBACK signal ensures discontinuous operation and
offers a fixed overvoltage detection level of 7.2 V.
2 FB Sets the peak current setpoint By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.
3 CS Current sense input and skip This pin senses the primary current and routes it to the internal
cycle level selection comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.
4 Gnd The IC ground −
5 Drv Driving pulses The driver’s output to an external MOSFET.
6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 10 F.
7 NC − This unconnected pin ensures adequate creepage distance.
8 HV High−voltage pin Connected to the high−voltage rail, this pin injects a constant current into
the VCC bulk capacitor.
http://onsemi.com
2
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
+
VUVLO
−
4.5 s +
Delay
Resd
HV Demag − Demag
OVP +
7.0 8.0 s Rint
PON + /1.44 + 10 V
mA Blanking
5.0 V 50 mV
+ − S Q Driver: src = 20
+ S* VCC sink = 10
− +
R* R Q
VCC
12 V, 10 V, Drv
5.3 V (fault) 4.2 V
To Internal Fault
Soft−Start = 1 ms
Supply Mngt. + /3 FB
GND −
1.0 V 200 A
when Drv
Overload? is OFF
380 ns
Timeout L.E.B. CS
5.0 s Reset
Timeout Demag
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2. Internal Circuit Architecture
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Voltage
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ Rating Symbol
VCC, Drv
Value
16
Units
V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) Pin 5 (Drv) and Pin 1 (Demag) − −0.3 to 10 V
Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V ESD diodes are − 5.0 mA
activated
http://onsemi.com
3
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted)
Rating Pin Symbol Min Typ Max Unit
DYNAMIC SELF−SUPPLY
VCC Increasing Level at which the Current Source Turns−off 6 VCCOFF 10.8 12 12.9 V
VCC Decreasing Level at which the Current Source Turns−on 6 VCCON 9.1 10 10.6 V
VCC Decreasing Level at which the Latchoff Phase Ends 6 VCClatch − 5.3 − V
VCC Level at which Output Pulses are Disabled 6 UVLO − VCCON − V
−200mV
Internal IC Consumption, No Output Load on Pin 5, 6 ICC1 − 1.0 1.3 mA
FSW = 60 kHz (Note 1)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, 6 ICC2 − 1.6 2.0 mA
FSW = 60 kHz (Note 1)
Internal IC Consumption in Latchoff Phase 6 ICC3 − 330 − A
INTERNAL STARTUP CURRENT SOURCE (TJ 0°C)
High−voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA
High−voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA
DRIVE OUTPUT
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output Signal 5 Tr − 40 − ns
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output Signal 5 Tf − 20 − ns
Source Resistance 5 ROH 12 20 36
Sink Resistance 5 ROL 5.0 10 19
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB − 0.02 − A
Maximum Internal Current Setpoint 3 ILimit 0.92 1.0 1.12 V
Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 100 160 ns
Leading Edge Blanking Duration 3 TLEB − 380 − ns
Internal Current Offset Injected on the CS Pin during OFF Time 3 Iskip − 200 − A
OVERVOLTAGE SECTION (VCC = 11 V)
Sampling Delay after ON Time 1 Tsample − 4.5 − s
OVP Internal Reference Level 1 Vref 6.4 7.2 8.0 V
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k)
Internal Pull−up Resistor 2 Rup − 20 − k
Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − −
Internal Soft−start − Tss − 1.0 − ms
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (Vpin 1 Decreasing) 1 Vth 35 50 90 mV
Hysteresis (Vpin 1 Decreasing) 1 VH − 20 − mV
Input Clamp Voltage
High State (Ipin 1 = 3.0 mA) 1 VCH 8.0 10 12 V
Low State (Ipin 1 = −2.0 mA) 1 VCL −0.9 −0.7 −0.5 V
Demag Propagation Delay 1 Tdem − 210 − ns
Internal Input Capacitance at Vpin 1 = 1.0 V 1 Cpar − 10 − pF
Minimum TOFF (Internal Blanking Delay after TON) 1 Tblank − 8.0 − s
Timeout After Last Demag Transition 1 Tout − 5.0 − s
Pin 1 Internal Impedance 1 Rint − 28 − k
1. Max value at TJ = 0°C.
http://onsemi.com
4
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
1.6 2.3
1.4 2.1
1.2 1.9
ICC1 (mA)
ICC2 (mA)
1.0 1.7
0.8 1.5
0.6 1.3
0.4 1.1
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 3. Internal IC Consumption (No Output Figure 4. Internal IC Consumption (1.0 nF
Load) versus Temperature Output Load) versus Temperature
13.2 11.2
12.8 10.8
12.4
10.4
VCCOFF (V)
VCCON (V)
12.0
10
11.6
9.6
11.2
10.8 9.2
10.4 8.8
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. VCC Increasing Level at which the Figure 6. VCC Decreasing Level at which the
Current Source Turns−Off versus Temperature Current Source Turns−On versus Temperature
12 40
11 35
10
30
9
ROH & ROL ()
8 25
IC1 (mA)
7 20
6
15
5
10
4
3 5
2 0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 7. Internal Startup Current Source at Figure 8. Source and Sink Resistance versus
VCC = 10 V versus Temperature Temperature
http://onsemi.com
5
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
120 1.20
100 1.15
80 1.10
VTH (mV)
Ilimit (V)
60 1.05
40 1.00
20 0.95
0 0.90
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. Input Voltage (Vpin1 Decreasing) Figure 10. Maximum Internal Current Setpoint
versus Temperature versus Temperature
8.0
7.8
7.6
7.4
7.2
Vref (V)
7.0
6.8
6.6
6.4
6.2
6.0
−25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 11. OVP internal Reference Level
versus Temperature
http://onsemi.com
6
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
APPLICATION INFORMATION
Introduction occurs at low peak current. This point guarantees a
The NCP1207A implements a standard current mode noise−free operation with cheap transformer. This
architecture where the switch−off time is dictated by the option also offers the ability to fix the maximum
peak current setpoint whereas the core reset detection switching frequency when entering light load
triggers the turn−on event. This component represents the conditions.
ideal candidate where low part−count is the key parameter, • Overcurrent Protection (OCP): by continuously
particularly in low−cost AC/DC adapters, consumer monitoring the FB line activity, NCP1207A enters burst
electronics, auxiliary supplies, etc. Thanks to its mode as soon as the power supply undergoes an
high−performance High−Voltage technology, the overload. The device enters a safe low power operation
NCP1207A incorporates all the necessary components / which prevents from any lethal thermal runaway. As
features needed to build a rugged and reliable Switch−Mode soon as the default disappears, the power supply
Power Supply (SMPS): resumes operation. Unlike other controllers, overload
• Transformer core reset detection: borderline / critical detection is performed independently of any auxiliary
operation is ensured whatever the operating conditions winding level. In presence of a bad coupling between
are. As a result, there are virtually no primary switch both power and auxiliary windings, the short circuit
turn−on losses and no secondary diode recovery losses. detection can be severely affected. The DSS naturally
The converter also stays a first−order system and shields you against these troubles.
accordingly eases the feedback loop design. Dynamic Self−Supply
• Quasi−resonant operation: by delaying the turn−on The DSS principle is based on the charge/discharge of the
event, it is possible to re−start the MOSFET in the VCC bulk capacitor from a low level up to a higher level. We
minimum of the drain−source wave, ensuring reduced can easily describe the current source operation with some
EMI / video noise perturbations. In nominal power simple logical equations:
conditions, the NCP1207A operates in Borderline POWER−ON: IF VCC < VCCOFF THEN Current Source
Conduction Mode (BCM) also called Critical is ON, no output pulses
Conduction Mode.
IF VCC decreasing > VCCON THEN Current Source is
• Dynamic Self−Supply (DSS): due to its Very High
OFF, output is pulsing
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1207A allows for a direct pin IF VCC increasing < VCCOFF THEN Current Source is
connection to the high−voltage DC rail. A dynamic ON, output is pulsing
current source charges up a capacitor and thus provides Typical values are: VCCOFF = 12 V, VCCON = 10 V
a fully independent VCC level to the NCP1207A. As a To better understand the operational principle, Figure 12’s
result, there is no need for an auxiliary winding whose sketch offers the necessary light.
management is always a problem in variable output
voltage designs (e.g. battery chargers).
• Overvoltage Protection (OVP): by sampling the plateau VRIPPLE = 2 V
VCCOFF = 12 V
voltage on the demagnetization winding, the
VCC
http://onsemi.com
7
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
The DSS behavior actually depends on the internal IC When using Figure 13 option, it is important to check
consumption and the MOSFET’s gate charge Qg. If we the absence of any negative ringing that could occur
select a MOSFET like the MTP2N60E, Qg equals 22 nC on pin 8. The resistor in series should help to damp
(max). With a maximum switching frequency selected at any parasitic LC network that would ring when
75 kHz, the average power necessary to drive the MOSFET suddenly applying the power to the IC. Also, since
(excluding the driver efficiency and neglecting various the power disappears during 10 ms (half−wave
voltage drops) is: rectification), CVCC should be calculated to supply
Fsw ⋅ Qg ⋅ VCC with: the IC during these holes in the supply
3. Permanently force the VCC level above VCCH with
Fsw = maximum switching frequency
an auxiliary winding. It will automatically
Qg = MOSFET’s gate charge disconnect the internal startup source and the IC will
VCC = VGS level applied to the gate be fully self−supplied from this winding. Again, the
To obtain the output current, simply divide this result by total power drawn from the mains will significantly
VCC: Idriver = FSW ⋅ Qg = 1.6 mA. The total standby power decrease. Make sure the auxiliary voltage never
consumption at no−load will therefore heavily rely on the exceeds the 16 V limit.
internal IC consumption plus the above driving current
Skipping Cycle Mode
(altered by the driver’s efficiency). Suppose that the IC is
The NCP1207A automatically skips switching cycles
supplied from a 350 VDC line. The current flowing through
when the output power demand drops below a given level.
pin 8 is a direct image of the NCP1207A consumption
This is accomplished by monitoring the FB pin. In normal
(neglecting the switching losses of the HV current source).
operation, Pin 2 imposes a peak current accordingly to the
If ICC2 equals 2.3 mA @ TJ = 60°C, then the power
load value. If the load demand decreases, the internal loop
dissipated (lost) by the IC is simply: 350 V x 2.3 mA =
asks for less peak current. When this setpoint reaches a
805 mW. For design and reliability reasons, it would be
determined level, the IC prevents the current from
interested to reduce this source of wasted power that
decreasing further down and starts to blank the output
increase the die temperature. This can be achieved by using
pulses: the IC enters the so−called skip cycle mode, also
different methods:
named controlled burst operation. The power transfer now
1. Use a MOSFET with lower gate charge Qg.
depends upon the width of the pulse bunches (Figure 14) and
2. Connect pin 8 through a diode (1N4007 typically) to
follows the following formula:
one of the mains input. The average value on pin 8
1 Lp Ip 2 Fsw D
V
becomes mainsPEAK 2. Our power contribution burst with:
2
example drops to: 223 V x 2.3 mA = 512 mW. If a Lp = primary inductance
resistor is installed between the mains and the diode, Fsw = switching frequency within the burst
you further force the dissipation to migrate from the
Ip = peak current at which skip cycle occurs
package to the resistor. The resistor value should
account for low−line startups. Dburst = burst width / burst recurrence
HV 1N4007
MAX PEAK NORMAL CURRENT
CURRENT SENSE SIGNAL (mV)
300
5 CURRENT MODE OPERATION
1 2 Cbulk
MAINS 1 8 6 200 SKIP CYCLE
2 7 CURRENT LIMIT
3 6
100
4 5
0
Figure 13. A simple diode naturally reduces the WIDTH
average voltage on Pin 8
RECURRENCE
http://onsemi.com
8
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
DRIVER current sense comparator permanently resets the latch and the
next clock cycle (given by the demagnetization detection) is
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 A
ignored: we are skipping cycles as shown by Figure 16. As
soon as the feedback voltage goes up again, there can be two
Rskip situations: the recurrent period is small and a new
− 3
RESET + demagnetization detection (next wave) signal triggers the
Rsense NCP1207A. To the opposite, in low output power conditions,
2 no more ringing waves are present on the drain and the toggling
of the current sense comparator together with the internal 5 s
timeout initiates a new cycle start. In normal operating
+ conditions, e.g. when the drain oscillations are generous, the
demagnetization comparator can detect the 50 mV crossing
and gives the “green light”, alone, to re−active the power
switch. However, when skip cycle takes place (e.g. at low
Figure 15. A patented method allows for skip level
selection via a series resistor inserted in series output power demands), the re−start event slides along the
with the current drain ringing waveforms (actually the valley locations) which
decays more or less quickly, depending on the
The skip level selection is done through a simple resistor Lprimary−Cparasitic network damping factor. The situation can
inserted between the current sense input and the sense element. thus quickly occur where the ringing becomes too weak to be
Every time the NCP1207A output driver goes low, a 200 A detected by the demagnetization comparator: it then
source forces a current to flow through the sense pin permanently stays locked in a given position and can no longer
(Figure 15): when the driver is high, the current source is off deliver the “green light” to the controller. To help in this
and the current sense information is normally processed. As situation, the NCP1207A implements a 5 s timeout generator:
soon as the driver goes low, the current source delivers 200 A each time the 50 mV crossing occurs, the timeout is reset. So,
and develops a ground referenced voltage across Rskip. If this as long as the ringing becomes too low, the timeout generator
voltage is below the feedback voltage, the current sense starts to count and after 5 s, it delivers its “green light”. If the
comparator stays in the high state and the internal latch can be skip signal is already present then the controller re−starts;
triggered by the next clock cycle. Now, if because of a low load otherwise the logic waits for it to set the drive output high.
mode the feedback voltage is below Rskip level, then the Figure 16 depicts these two different situations:
Drain
Signal
Timeout
Signal
Demag Re−start
Current Sense and Timeout Re−start
Drain
Signal
Timeout 5 s 5 s
Signal
Figure 16. When the primary natural ringing becomes too low, the internal timeout together with the sense
comparator initiates a new cycle when FB passes the skip level.
http://onsemi.com
9
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
Demagnetization Detection
The core reset detection is done by monitoring the voltage 400
activity on the auxiliary winding. This voltage features a
200
7.0
100
DEMAG SIGNAL (V)
5.0 POSSIBLE
RE−STARTS
0
3.0
Figure 19. The NCP1207A Operates in
1.0 Borderline / Critical Operation
50 mV
0V
−1.0 Overvoltage Protection
The overvoltage protection works by sampling the plateau
Figure 17. Core reset detection is done through a
voltage 4.5 s after the turn−off sequence. This delay
dedicated auxiliary winding monitoring guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
TO INTERNAL be the case, the designer should install a small RC damper
COMPARATOR Resd Rdem across the transformer primary inductance connections.
1 Figure 20 shows where the sampling occurs on the auxiliary
2 1 5 4
winding.
Rint ESD2 ESD1 Aux
SAMPLING HERE
4 3 8.0
Resd + Rint = 28 k
DEMAG SIGNAL (V)
6.0
Figure 18. Internal Pad Implementation
http://onsemi.com
10
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
2
10 k 2 7
1
ON/OFF Q1
3 2
3 6
Rdrop
4 5
7.0 mA 7.1 k 0.286
2
10 nF
99.5 mW
7.1 k
Please refer to the application note AND8069 available
Figure 23. A simple bipolar transistor totally
from www.onsemi.com/pub/ncp1200.
disables the IC
http://onsemi.com
11
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
• If the power consumption budget is really too high for the NCP1207A hosts a dedicated overload detection circuitry.
DSS alone, connect a diode between the auxiliary Once activated, this circuitry imposes to deliver pulses in a
winding and the VCC pin which will disable the DSS burst manner with a low duty−cycle. The system recovers
operation (VCC 10 V). when the fault condition disappears.
The SOIC package offers a 178°C/W thermal resistor. During the startup phase, the peak current is pushed to the
Again, adding some copper area around the PCB footprint maximum until the output voltage reaches its target and the
will help decrease this number: 12 mm 12 mm to drop feedback loop takes over. This period of time depends on
RJA down to 100°C/W with 35 m copper thickness (1 oz) normal output load conditions and the maximum peak
or 6.5 mm 6.5 mm with 70 m copper thickness (2 oz). current allowed by the system. The time−out used by this IC
As one can see, we do not recommend using the SO−8 works with the VCC decoupling capacitor: as soon as the
package and the DSS if the part operates at high switching VCC decreases from the VCCOFF level (typically 12 V) the
frequencies. In that case, an auxiliary winding is the best device internally watches for an overload current situation.
solution. If this condition is still present when the VCCON level is
reached, the controller stops the driving pulses, prevents the
Overload Operation self−supply current source to restart and puts all the circuitry
In applications where the output current is purposely not in standby, consuming as little as 330 A typical (ICC3
controlled (e.g. wall adapters delivering raw DC level), it is parameter). As a result, the VCC level slowly discharges
interesting to implement a true short−circuit protection. A toward 0. When this level crosses 5.3 V typical, the
short−circuit actually forces the output voltage to be at a low controller enters a new startup phase by turning the current
level, preventing a bias current to circulate in the source on: VCC rises toward 12 V and again delivers output
Optocoupler LED. As a result, the FB pin level is pulled up pulses at the VCCOFF crossing point. If the fault condition
to 4.2 V, as internally imposed by the IC. The peak current has been removed before VCCON approaches, then the IC
setpoint goes to the maximum and the supply delivers a continues its normal operation. Otherwise, a new fault cycle
rather high power with all the associated effects. Please note takes place. Figure 24 shows the evolution of the signals in
that this can also happen in case of feedback loss, e.g. a presence of a fault.
broken Optocoupler. To account for this situation,
VCC
REGULATION
OCCURS HERE
12 V
LATCHOFF
10 V PHASE
5.3 V
TIME
If the fault is relaxed during the Vcc
DRV
natural fall down sequence, the IC
automatically resumes.
DRIVER If the fault still persists when Vcc
PULSES reached VCCON, then the controller
cuts everything off until recovery.
TIME
INTERNAL
FAULT FLAG
FAULT IS
RELAXED
TIME
STARTUP PHASE FAULT OCCURS HERE
Figure 24.
Soft−Start level (e.g. 1.0 V). The soft−start is also activated during the
The NCP1207A features an internal 1 ms soft−start to overcurrent burst (OCP) sequence. Every restart attempt is
soften the constraints occurring in the power supply during followed by a soft−start activation. Generally speaking, the
startup. It is activated during the power on sequence. As soft−start will be activated when VCC ramps up either from
soon as VCC reaches VCCOFF , the peak current is gradually zero (fresh power−on sequence) or 5.3 V, the latchoff
increased from nearly zero up to the maximum clamping voltage occurring during OCP.
http://onsemi.com
12
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
http://onsemi.com
13
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
NCP1207A
200 A X RSKIP
VGATE (5 V/div)
This picture explains how the 200 A internal offset The short−circuit protection forces the IC to enter burst in
current creates the skip cycle level. presence of a secondary overload.
http://onsemi.com
14
Datasheet pdf - http://www.DataSheet4U.net/
w w w . D a t a S h e e t . c o . k r
NCP1207A
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8 5 NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
−B− FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
1 4
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
F MILLIMETERS INCHES
DIM MIN MAX MIN MAX
NOTE 2 −A− A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
L C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
C H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
J K 2.92 3.43 0.115 0.135
−T− L 7.62 BSC 0.300 BSC
SEATING N M −−− 10 −−− 10
PLANE N 0.76 1.01 0.030 0.040
M
D K
H G
0.13 (0.005) M T A M B M
http://onsemi.com
15
D a t a s h e
www.DataSheet.co.kr
NCP1207A
PACKAGE DIMENSIONS
(SO−8)
D1, D2 SUFFIX
CASE 751−07
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
−X− Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
8 5 SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
1 EXCESS OF THE D DIMENSION AT MAXIMUM
4 MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 A 4.80 5.00 0.189 0.197
SEATING B 3.80 4.00 0.150 0.157
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
The product described herein (NCP1207A), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,385,061, 6,429,709,
6,587,357, 6,633,193. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
http://onsemi.com NCP1207A/D
16
Datasheet pdf - http://www.DataSheet4U.net/