NCP1203

PWM Current−Mode
Controller for Universal
Off−Line Supplies Featuring
Standby and Short Circuit
Protection http://onsemi.com
Housed in SO-8 or DIP8 package, the NCP1203 represents a major
leap toward ultra- compact Switch- Mode Power Supplies and MARKING
represents an excellent candidate to replace the UC384X devices. DIAGRAMS
Thanks to its proprietary SMARTMOS Very High Voltage
8
Technology, the circuit allows the implementation of complete
SO-8 XXXXXX
off-line AC/DC adapters, battery charger and a high-power SMPS
8 D1, D2 SUFFIX ALYW
with few external components. CASE 751
With an internal structure operating at a fixed 40 kHz, 60 kHz or 1
1
100 kHz switching frequency, the controller features a high-voltage
start-up FET which ensures a clean and loss-less start-up sequence.
8
Its current-mode control naturally provides good audio-susceptibility
and inherent pulse-by-pulse control. PDIP-8 XXXXXXXXX
When the current set point falls below a given value, e.g. the output N SUFFIX AWL
power demand diminishes, the IC automatically enters the so- called 8 YYWW
CASE 626
skip cycle mode and provides improved efficiency at light loads 1
1
while offering excellent performance in standby conditions. Because
this occurs at a user adjustable low peak current, no acoustic noise
takes place. xx = Specific Device Code
The NCP1203 also includes an efficient protective circuitry which, A = Assembly Location
in presence of an output over load condition, disables the output WL, L = Wafer Lot
YY, Y = Year
pulses while the device enters a safe burst mode, trying to restart.
WW, W = Work Week
Once the default has gone, the device auto- recovers. Finally, a
temperature shutdown with hysteresis helps building safe and robust
power supplies.
PIN CONNECTIONS
Features
• High-Voltage Start-Up Current Source Adj 1 8 HV
• Auto-Recovery Internal Output Short-Circuit Protection
• Extremely Low No-Load Standby Power
FB 2 7 NC

• Current-Mode with Adjustable Skip-Cycle Capability CS 3 6 VCC

• Internal Leading Edge Blanking Gnd 4 5 Drv
• 250 mA Peak Current Capability
• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz (Top View)

• Direct Optocoupler Connection

• Undervoltage Lockout at 7.8 V Typical ORDERING INFORMATION
• SPICE Models Available for TRANsient and AC Analysis Device Package Shipping
• Pin to Pin Compatible with NCP1200
NCP1203P60 PDIP8 50 Units/Tube
Applications
• AC/DC Adapters for Notebooks, etc. NCP1203D60R2 SO-8 2500/Tape & Reel

• Offline Battery Chargers NCP1203P40 PDIP8 50 Units/Tube

• Auxiliary Power Supplies (USB, Appliances, TVs, etc.) NCP1203D40R2 SO-8 2500/Tape & Reel
NCP1203P100 PDIP8 50 Units/Tube
NCP1203D100R2 SO-8 2500/Tape & Reel

 Semiconductor Components Industries, LLC, 2003 1 Publication Order Number:

February, 2003- Rev. 3 NCP1203/D

This datasheet has been downloaded from http://www.digchip.com at this page

 NCP1203

* VOUT
Aux. +
+

NCP1203
Adj HV
1 8
FB
2 7
EMI CS VCC
3 6
FILTER Gnd Drv
4 5

UNIVERSAL
INPUT +

*Please refer to the application information section

Figure 1. Typical Application Example

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Function Pin Description
1 Adj Adjust the skipping peak current This pin lets you adjust the level at which the cycle skipping process takes
place. Shorting this pin to ground, permanently disables the skip cycle
feature.
2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. Skip cycle occurs when
FB falls below Vpin1.
3 CS Current sense input This pin senses the primary current and routes it to the internal comparator
via an L.E.B.

4 Gnd The IC ground -

5 Drv Driving pulses The driver’s output to an external MOSFET.
6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 22 F.
7 NC - This unconnected pin ensures adequate creepage distance.
8 HV Ensure a clean and lossless Connected to the high-voltage rail, this pin injects a constant current into
start-up sequence the VCC capacitor during the start-up sequence.

http://onsemi.com
2
 NCP1203

Adj HV
1 8

HV CURRENT
SOURCE

80 k SKIP CYCLE
FB 1.2 V COMPARATOR NC
+
2 − UVLO HIGH AND LOW 7
INTERNAL VCC INTERNAL REGULATOR

24 k

CURRENT
Q FLIP-FLOP
SENSE VCC
DCmax = 80%
250 ns 40-60-100 kHz SET Q OVERLOAD
3 6
L.E.B. CLOCK MANAGEMENT
RESET

20 k 57 k +
−
GROUND Drv
VREF
4 + 25 k 1V ±250 mA 5
-

Figure 2. Internal Circuit Architecture

MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC, Drv 16 V
Power Supply Voltage on all other pins except Pin 5 (Drv), Pin 6 (VCC) and Pin 8 (HV) - -0.3 to 10 V
Maximum Current into all pins except Pin 6 (VCC) and Pin 8 (HV) when - 5.0 mA
10 V ESD diodes are activated

Thermal Resistance Junction-to-Air, PDIP8 Version RθJA 100 °C/W

Thermal Resistance Junction-to-Air, SOIC Version RθJA 178 °C/W

Maximum Junction Temperature TJMAX 150 °C

Temperature Shutdown - 170 °C
Hysteresis in Shutdown - 30 °C
Storage Temperature Range - -60 to +150 °C
ESD Capability, HBM Model, All pins except Pin 6 (VCC) and Pin 8 (HV) - 2.0 KV
ESD Capability, Machine Model - 200 V
Maximum Voltage on Pin 6 (VCC) and Pin 8 (HV) Decoupled to Ground with 10 F - 450 V

http://onsemi.com
3
 NCP1203

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted.)
Characteristic Symbol Pin Min Typ Max Unit

Supply Section (All frequency versions, otherwise noted)

Turn-on Threshold Level, VCC Going Up VCC(on) 6 12.2 12.8 14 V
Minimum Operating Voltage after Turn-on VCC(min) 6 7.2 7.8 8.4 V
VCC Decreasing Level at which the Latch-off Phase Ends VCClatch 6 - 4.9 - V
Internal IC Consumption, No Output Load on Pin 5 ICC1 6 - 750 880 A
(Note 1)

Internal IC Consumption, 1.0 nF Output Load on Pin 5, ICC2 6 - 1.2 1.4 mA

FSW = 40 kHz (Note 2)

Internal IC Consumption, 1.0 nF Output Load on Pin 5, ICC2 6 - 1.4 1.6 mA

FSW = 60 kHz (Note 2)

Internal IC Consumption, 1.0 nF Output Load on Pin 5, ICC2 6 - 2.0 2.2 mA

FSW = 100 kHz (Note 2)

Internal IC Consumption, Latch-off Phase, VCC = 6.0 V ICC3 6 - 250 - A

Internal Start-Up Current Source (Pin 8 biased at 50 V)

High-V oltage Current Source, VCC = 10 V IC1 8 3.5 6.0 9.0 mA
High-V oltage Current Source, VCC = 0 IC2 8 - 11 - mA

Drive Output
Output Voltage Rise-Time @ CL = 1.0 nF, 10-90% of Tr 5 - 67 - ns
Output Signal

Output Voltage Fall-Time @ CL = 1.0 nF, 10-90% of Tf 5 - 28 - ns

Output Signal

Source Resistance ROH 5 27 40 61 

Sink Resistance ROL 5 5.0 10 20 

Current Comparator (Pin 5 loaded unless otherwise noted)

Input Bias Current @ 1.0 V Input Level on Pin 3 IIB 3 - 0.02 - A
Maximum Internal Current Setpoint (Note 3) ILimit 3 0.85 0.92 1.0 V
Default Internal Current Setpoint for Skip Cycle Operation ILskip 3 - 360 - mV
Propagation Delay from Current Detection to Gate OFF TDEL 3 - 90 160 ns
State

Leading Edge Blanking Duration (Note 3) TLEB 3 - 230 - ns

Internal Oscillator (VCC = 11 V, Pin 5 loaded by 1 nF)

Oscillation Frequency, 40 kHz Version fOSC - 37 42 47 kHz
Oscillation Frequency, 60 kHz Version fOSC - 57 65 73 kHz
Oscillation Frequency, 100 kHz Version fOSC - 90 103 115 kHz
Maximum Duty-Cycle Dmax - 74 80 87 %

Feedback Section (VCC = 11 V, Pin 5 unloaded)

Internal Pull-up Resistor Rup 2 - 20 - k
Pin 3 to Current Setpoint Division Ratio Iratio - - 3.3 - -

Skip Cycle Generation

Default Skip Mode Level Vskip 1 1.0 1.2 1.4 V
Pin 1 Internal Output Impedance Zout 1 - 22 - k
1. Max value at TJ = 0°C.
2. Maximum value @ TJ = 25°C, please see characterization curves.
3. Pin 5 loaded by 1 nF.

http://onsemi.com
4
 NCP1203

14.0 8.4
13.8
8.2
VCC(on) THRESHOLD (V)

13.6

VCC(min) LEVEL (V)

13.4 8.0

13.2
7.8
13.0

12.8 7.6
12.6
7.4
12.4
12.2 7.2
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 3. VCC(on) Threshold versus Figure 4. VCC(min) Level versus Temperature

Temperature

1000 2.0

ICC, 1 nF LOAD CONSUMPTION (mA)

ICC, CURRENT CONSUMPTION (A)

100 kHz
950
900 1.8
850
800 60 kHz 1.6
100 kHz
750
60 kHz
700 1.4
650 40 kHz
600 1.2
550 40 kHz
500 1.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 5. IC Current Consumption (No Load) Figure 6. ICC Consumption (Loaded by 1 nF)
versus Temperature versus Temperature

8.0 400

7.5
HV CURRENT SOURCE (mA)

350
7.0
ICC @ VCC = 6 V (A)

40 & 60 kHz
6.5 300
6.0
250
5.5
100 kHz
5.0
200
4.5
4.0 150
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 7. HV Current Source at VCC = 10 V Figure 8. IC Consumption at VCC = 6 V

versus Temperature versus Temperature

http://onsemi.com
5
 NCP1203

60 20
DRIVE SOURCE RESISTANCE ()
55 18

DRIVE SINK RESISTANCE ()

50 16
45 14

40 12

35 10
30 8
25 6
20 4
15 2
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 9. Drive Source Resistance versus Figure 10. Drive Sink Resistance versus
Temperature Temperature

0.99 120
MAXIMUM CURRENT SETPOINT (V)

100 kHz
0.97 f, FREQUENCY (kHz) 100

0.95
80
0.93 60 kHz
60
0.91 40 kHz
40
0.89

20
0.87

0.85 0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Maximum Current Setpoint versus Figure 12. Frequency versus Temperature
Temperature

http://onsemi.com
6
 NCP1203

APPLICATION INFORMATION

Introduction skipping unwanted switching cycles at a user-adjustable

The NCP1203 implements a standard current mode power level. By ensuring that skip cycles take place at low
architecture where the switch-off time is dictated by the peak current, the device ensures quiet, noise free operation.
peak current setpoint. This component represents the ideal Finally, an auto-recovery output short-circuit protection
candidate where low part-count is the key parameter, (OCP) prevents from any lethal thermal runaway in
particularly in low-cost AC/DC adapters, auxiliary supplies overload conditions.
etc. Thanks to its high-performance SMARTMOS
High-Voltage technology, the NCP1203 incorporates all the Start-Up Sequence
necessary components normally needed in UC384X based When the power supply is first powered from the mains
supplies: timing components, feedback devices, low-pass outlet, the internal current source (typically 6.0 mA) is
filter and start-up device. This later point emphasizes the biased and charges up the VCC capacitor. When the voltage
fact that ON Semiconductor’s NCP1203 does not need an on this VCC capacitor reaches the VCC(on) level (typically
external start-up resistance but supplies the start-up current 12.8 V), the current source turns off and no longer wastes
directly from the high-voltage rail. On the other hand, more any power. At this time, the VCC capacitor only supplies the
and more applications are requiring low no-load standby controller and the auxiliary supply is supposed to take over
power, e.g. for AC/DC adapters, VCRs etc. UC384X series before VCC collapses below VCC(min). Figure 13 shows the
have a lot of difficulty to reduce the switching losses at low internal arrangement of this structure:
power levels. NCP1203 elegantly solves this problem by

8 HV

12.8 V/4.9 V +
− 6 mA or 0

CVCC Aux

Figure 13. The Current Source Brings VCC Above 12.8 V and then Turns Off

Once the power supply has started, the VCC shall be

constrained below 16 V, which is the maximum rating on 13.5
pin 6. Figure 14 portrays a typical start-up sequence with a
12.8 V REGULATION
VCC regulated at 12.5 V: 12.5

11.5

10.5

9.5

3.00 M 8.00 M 13.0 M 18.0 M 23.0 M

t, TIME (sec)
Figure 14. A Typical Start-Up Sequence for
the NCP1203

http://onsemi.com
7
 NCP1203

Current-Mode Operation transformer … You can thus select cheap magnetic

As the UC384X series, the NCP1203 features a components free of noise problems.
well-known current mode control architecture which
provides superior input audio-susceptibility compared to External MOSFET Connection
traditional voltage-mode controllers. Primary current By leaving the external MOSFET external to the IC, you
pulse-by-pulse checking together with a fast over current can select avalanche proof devices which, in certain cases
comparator offers greater security in the event of a difficult (e.g. low output powers), let you work without an active
fault condition, e.g. a saturating transformer. clamping network. Also, by controlling the MOSFET gate
signal flow, you have an option to slow down the device
Adjustable Skip Cycle Level commutation, therefore reducing the amount of
By offering the ability to tailor the level at which the skip ElectroMagnetic Interference (EMI).
cycle takes place, the designer can make sure that the skip
SPICE Model
operation only occurs at low peak current. This point
A dedicated model to run transient cycle-by-cycle
guarantees a noise-free operation with cheap transformers.
simulations is available but also an averaged version to help
Skip cycle offers a proven mean to reduce the standby power
you closing the loop. Ready-to-use templates can be
in no or light loads situations.
downloaded in OrCAD’s Pspice and INTUSOFT’s from ON
Wide Switching-Frequency Offer Semiconductor web site, NCP1203 related section.
Four different options are available: 40 kHz - 65 kHz –
Overload Operation
100 kHz. Depending on the application, the designer can
In applications where the output current is purposely not
pick up the right device to help reducing magnetics or
controlled (e.g. wall adapters delivering raw DC level), it is
improve the EMI signature before reaching the 150 kHz
interesting to implement a true short-circuit protection. A
starting point.
short-circuit actually forces the output voltage to be at a low
Over Current Protection (OCP) level, preventing a bias current to circulate in the
When the auxiliary winding collapses below UVLOlow, optocoupler LED. As a result, the auxiliary voltage also
the controller stops switching and reduces its consumption. decreases because it also operates in Flyback and thus
It stays in this mode until Vcc reaches 4.9 V typical, where duplicates the output voltage, providing the leakage
the start-up source is reactivated and a new start-up inductance between windings is kept low. To account for this
sequence is attempted. The power supply is thus operated in situation and properly protect the power supply, NCP1203
burst mode and avoids any lethal thermal runaway. When hosts a dedicated overload detection circuitry. Once
the default goes way, the power supply automatically activated, this circuitry imposes to deliver pulses in a burst
resumes operation. manner with a low duty-cycle. The system auto-recovers
when the fault condition disappears.
Wide Duty-Cycle Operation During the start-up phase, the peak current is pushed to
Wide mains operation requires a large duty-cycle the maximum until the output voltage reaches its target and
excursion. The NCP1203 can go up to 80% typically. the feedback loop takes over. The auxiliary voltage takes
place after a few switching cycles and self-supplies the IC.
Low Standby-Power
In presence of a short circuit on the output, the auxiliary
If SMPS naturally exhibit a good efficiency at nominal
voltage will go down until it crosses the undervoltage
load, they begin to be less efficient when the output power
lockout level of typically 7.8 V. When this happens,
demand diminishes. By skipping un-needed switching
NCP1203 immediately stops the switching pulses and
cycles, the NCP1203 drastically reduces the power wasted
unbias all unnecessary logical blocks. The overall
during light load conditions. In no-load conditions, the
consumption drops, while keeping the gate grounded, and
NCP1203 allows the total standby power to easily reach next
the VCC slowly falls down. As soon as VCC reaches typically
International Energy Agency (IEA) recommendations.
4.8 V, the start-up source turns-on again and a new start-up
No Acoustic Noise while Operating sequence occurs, bringing VCC toward 12.8 V as an attempt
Instead of skipping cycles at high peak currents, the to restart. If the default has gone, then the power supply
NCP1203 waits until the peak current demand falls below a normally restarts. If not, a new protective burst is initiated,
user-adjustable 1/3rd of the maximum limit. As a result, shielding the SMPS from any runaway. Figure 15, on the
cycle skipping can take place without having a singing following page, portrays the typical operating signals in
short circuit.

http://onsemi.com
8
 NCP1203

12.8 V
7.8 V
VCC

4.9 V

DRIVING PULSES

Figure 15. Typical Waveforms in Short Circuit Conditions

Calculating the VCC Capacitor 1 · Lp · Ip2 · Fsw
3.8 W

The VCC capacitor can be calculated knowing the IC 2
consumption as soon as VCC reaches 12.8 V. Suppose that a If this IC enters skip cycle mode with a bunch length of
NCP1203P60 is used and drives a MOSFET with a 30 nC 10 ms over a recurrent period of 100 ms, then the total power
total gate charge (Qg). The total average current is thus made transfer is: 3.8 . 0.1
380 mW.
of ICC1 (700 A) plus the driver current, Fsw x Qg or To better understand how this skip cycle mode takes place,
1.8 mA. The total current is therefore 2.5 mA. The ∆V a look at the operation mode versus the FB level
available to fully start-up the circuit (e.g. never reach the immediately gives the necessary insight:
7.8 V UVLO during power on) is 12.8–7.8 = 5 V. We have
a capacitor who then needs to supply the NCP1203 with FB
2.5 mA during a given time until the auxiliary supply takes
4.2 V, FB Pin Open
over. Suppose that this time was measured at around 15 ms.
3.2 V, Upper
CVCC is calculated using the equation C

t · i or NORMAL CURRENT Dynamic Range

V MODE OPERATION
C  7.5 F. Select a 22 F/16 V and this will fit.

Skipping Cycle Mode 1V

The NCP1203 automatically skips switching cycles when SKIP CYCLE OPERATION
IP(min) = 333 mV/RSENSE
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal Figure 16.
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop When FB is above the skip cycle threshold (1.0 V by
asks for less peak current. When this setpoint reaches a default), the peak current cannot exceed 1.0 V/Rsense.
determined level (Vpin 1), the IC prevents the current from When the IC enters the skip cycle mode, the peak current
decreasing further down and starts to blank the output cannot go below Vpin1/3.3/Rsense. The user still has the
pulses: the IC enters the so-called skip cycle mode, also flexibility to alter this 1.0 V by either shunting pin 1 to
named controlled burst operation. The power transfer now ground through a resistor or raising it through a resistor up
depends upon the width of the pulse bunches (Figure 17). to the desired level. Grounding pin 1 permanently
Suppose we have the following component values: invalidates the skip cycle operation. However, given the
Lp, primary inductance = 350 H extremely low standby power the controller can reach, the
Fsw , switching frequency = 61 kHz PWM in no-load conditions can quickly enter the minimum
Ip skip = 600 mA (or 333 mV/Rsense) ton and still transfer too much power. An instability can take
The theoretical power transfer is therefore: place. We recommend in that case to leave a little bit of skip
level to always allow 0% duty-cycle.

http://onsemi.com
9
 NCP1203

Power P1

Power P2

Power P3

Figure 17. Output Pulses at Various Power Levels (X = 5.0
s/div) P1
P2
P3

MAX PEAK
300 M CURRENT

200 M SKIP CYCLE

CURRENT LIMIT

100 M

315.40 882.70 1.450 M 2.017 M 2.585 M

Figure 18. The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise-Free Operation

We recommend a pin1 operation between 400 mV and disappeared. This option can easily be accomplished
1.3 V that will fix the skip peak current level between through a single NPN bipolar transistor wired between FB
120 mV/Rsense and 390 mV/Rsense. and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
Non-Latching Shutdown pin 1. As soon as FB is relaxed, the IC resumes its operation.
In some cases, it might be desirable to shut off the part Figure 19 depicts the application example:
temporarily and authorize its restart once the default has

http://onsemi.com
10
 NCP1203

1 8
2 7
3 6
ON/OFF Q1
4 5

Figure 19. Another Way of Shutting Down the IC without a Definitive Latch-Off State

Full Latching Shutdown When the VCC level exceeds the zener breakdown voltage,
Other applications require a full latching shutdown, e.g. the NPN biases the PNP and fires the equivalent SCR,
when an abnormal situation is detected (over temp or permanently bringing down the FB pin. The switching
overvoltage). This feature can easily be implemented pulses are disabled until the user unplugs the power supply.
through two external transistors wired as a discrete SCR.

Rhold
OVP 12 k

NCP1203
10 k
1 8
2 7
3 6
4 5 CVCC LAux
0.1 F 10 k

Figure 20. Two Bipolars Ensure a Total Latch-Off of the SMPS in Presence of an OVP

Rhold ensures that the SCR stays on when fired. The bias pin is often the seat of such spurious signals, the
current flowing through Rhold should be small enough to let high-voltage pin can also be the source of problems in
the VCC ramp up (12.8 V) and down (4.9 V) when the SCR certain circumstances. During the turn-off sequence, e.g.
is fired. The NPN base can also receive a signal from a when the user un-plugs the power supply, the controller is
temperature sensor. Typical bipolars can be MMBT2222 still fed by its VCC capacitor and keeps activating the
and MMBT2907 for the discrete latch. The MMBT3946 MOSFET ON and OFF with a peak current limited by
features two bipolars NPN+PNP in the same package and Rsense. Unfortunately, if the quality coefficient Q of the
could also be used. resonating network formed by Lp and Cbulk is low (e.g. the
MOSFET Rdson + Rsense are small), conditions are met to
Protecting the Controller Against Negative Spikes make the circuit resonate and thus negatively bias the
As with any controller built upon a CMOS technology, it controller. Since we are talking about ms pulses, the amount
is the designer’s duty to avoid the presence of negative of injected charge (Q = I x t) immediately latches the
spikes on sensitive pins. Negative signals have the bad habit controller which brutally discharges its VCC capacitor. If this
to forward bias the controller substrate and induce erratic VCC capacitor is of sufficient value, its stored energy
behaviors. Sometimes, the injection can be so strong that damages the controller. Figure 21 depicts a typical negative
internal parasitic SCRs are triggered, engendering shot occurring on the HV pin where the brutal VCC discharge
irremediable damages to the IC if they are a low impedance testifies for latch-up.
path is offered between VCC and GND. If the current sense

http://onsemi.com
11
 NCP1203

Figure 21. A negative spike takes place on the Bulk capacitor at the switch-off sequence

Simple and inexpensive cures exist to prevent from Another option (Figure 23) consists in wiring a diode from
internal parasitic SCR activation. One of them consists in VCC to the bulk capacitor to force VCC to reach UVLOlow
inserting a resistor in series with the high-voltage pin to sooner and thus stops the switching activity before the bulk
keep the negative current to the lowest when the bulk capacitor gets deeply discharged. For security reasons, two
becomes negative (Figure 22). Please note that the negative diodes can be connected in series.
spike is clamped to –2 x Vf due to the diode bridge. Also, the
power dissipation of this resistor is extremely small since it
only heats up during the start-up sequence.

Rbulk
> 4.7 k

1 8 1 8 D3
+ +
Cbulk 2 7 Cbulk 2 7 1N4007

3 6 3 6
+ +
4 5 CVCC 4 5 CVCC

Figure 22. A simple resistor in series avoids any Figure 23. or a diode forces VCC to reach
latch-up in the controller UVLOlow sooner

http://onsemi.com
12
 NCP1203

PACKAGE DIMENSIONS

PDIP-8
N SUFFIX
CASE 626-05
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8 5 2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
-B- Y14.5M, 1982.

1 4 MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
F C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
NOTE 2 -A- F 1.02 1.78 0.040 0.070
L G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
C L 7.62 BSC 0.300 BSC
M −−− 10
−−− 10

J N 0.76 1.01 0.030 0.040
-T-
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M

http://onsemi.com
13
 NCP1203

PACKAGE DIMENSIONS

SO-8
D1, D2 SUFFIX
CASE 751-07
ISSUE AA

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
-X- Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
8 5 SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
1 EXCESS OF THE D DIMENSION AT MAXIMUM
4 MATERIAL CONDITION.
-Y- K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
-Z- D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0
8
0
8

N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

SMARTMOS is a trademark of Motorola, Inc.

The product described herein (NCP1203), may be covered by one or more of the following U.S. patents: 6,271,737; 6,385,060. There may
be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment: JAPAN: ON Semiconductor, Japan Customer Focus Center
Literature Distribution Center for ON Semiconductor 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
P.O. Box 5163, Denver, Colorado 80217 USA Phone: 81-3-5773-3850
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
ON Semiconductor Website: http://onsemi.com
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected] For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800-282-9855 Toll Free USA/Canada

http://onsemi.com NCP1203/D
14