BUK98180-100A

N-channel TrenchMOS logic level FET

16 March 2016 Product data sheet

1. General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.

2. Features and benefits

• Low conduction losses due to low on-state resistance
• Q101 compliant
• Suitable for logic level gate drive sources

3. Applications
• 12 V, 24 V and 42 V loads
• Automotive and general purpose power switching
• Motors, lamps and solenoids

4. Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 100 V

ID drain current VGS = 5 V; Tsp = 25 °C; Fig. 2; Fig. 3 - - 4.6 A

Ptot total power dissipation Tsp = 25 °C; Fig. 1 - - 8 W

Static characteristics
RDSon drain-source on-state VGS = 10 V; ID = 5 A; Tj = 25 °C - 147 173 mΩ
resistance
VGS = 4.5 V; ID = 5 A; Tj = 25 °C - - 201 mΩ

VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12; - 153 180 mΩ

Fig. 13
Avalanche ruggedness
EDS(AL)S non-repetitive drain- ID = 4 A; Vsup ≤ 100 V; RGS = 50 Ω; - - 16 mJ
source avalanche VGS = 5 V; Tj(init) = 25 °C; unclamped
energy
Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

5. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 G gate 4 D

2 D drain
G
3 S source
1 2 3
4 D drain mbb076 S
SC-73 (SOT223)

6. Ordering information
Table 3. Ordering information
Type number Package
Name Description Version
BUK98180-100A SC-73 plastic surface-mounted package with increased SOT223
heatsink; 4 leads
BUK98180-100A/CU SC-73 plastic surface-mounted package with increased SOT223
heatsink; 4 leads

7. Marking
Table 4. Marking codes
Type number Marking code
BUK98180-100A 918010
BUK98180-100A/CU 918010

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 100 V

VDGR drain-gate voltage RGS = 20 kΩ - 100 V

VGS gate-source voltage -10 10 V

Ptot total power dissipation Tsp = 25 °C; Fig. 1 - 8 W

ID drain current Tsp = 25 °C; VGS = 5 V; Fig. 2; Fig. 3 - 4.6 A

Tsp = 100 °C; VGS = 5 V; Fig. 2 - 3 A

IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; Fig. 3 - 18 A

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

Symbol Parameter Conditions Min Max Unit

Tstg storage temperature -55 150 °C

Tj junction temperature -55 150 °C

VGSM peak gate-source voltage pulsed; tp ≤ 50 µs -15 15 V

Source-drain diode
IS source current Tsp = 25 °C - 4.6 A

ISM peak source current pulsed; tp ≤ 10 µs; Tsp = 25 °C - 18 A

Avalanche ruggedness
EDS(AL)S non-repetitive drain-source ID = 4 A; Vsup ≤ 100 V; RGS = 50 Ω; - 16 mJ
avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped

03aa17 03aa25
120 120

Pder Ider
(%) (%)

80 80

40 40

0 0
0 50 100 150 200 0 50 100 150 200
Tsp (°C) Tsp (°C)

Fig. 1. Normalized total power dissipation as a Fig. 2. Normalized continuous drain current as a
function of solder point temperature function of solder point temperature

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

03nc34
102

ID
(A)
RDSon = VDS/ID
10 tp = 10 µs

100 µs

1 1 ms

tp D.C. 10 ms
P δ=
T
100 ms
10- 1

tp t
T
10- 2
10- 1 1 10 102 103
VDS (V)

Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

9. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-sp) thermal resistance Fig. 4 - - 15 K/W
from junction to solder
point
Rth(j-a) thermal resistance - 120 - K/W
from junction to
ambient

03nc35
102

Zth(j-sp)
(K/W)

10
δ = 0.5

0.2
0.1
1
0.05

0.02 tp
P δ=
T
10- 1

Single Shot t
tp
T
10- 2
10- 6 10- 5 10- 4 10- 3 10- 2 10- 1 1 10 12
tp (s)

Fig. 4. Transient thermal impedance from junction to solder point as a function of pulse duration

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

10. Characteristics
Table 7. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 100 - - V
breakdown voltage
ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 89 - - V

VGS(th) gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; 1 1.5 2 V

voltage Fig. 11
ID = 1 mA; VDS = VGS; Tj = -55 °C; - - 2.3 V
Fig. 11
ID = 1 mA; VDS = VGS; Tj = 150 °C; 0.6 - - V
Fig. 11
IDSS drain leakage current VDS = 100 V; VGS = 0 V; Tj = 150 °C - - 500 µA

VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA

IGSS gate leakage current VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA

VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA

RDSon drain-source on-state VGS = 10 V; ID = 5 A; Tj = 25 °C - 147 173 mΩ

resistance
VGS = 4.5 V; ID = 5 A; Tj = 25 °C - - 201 mΩ

VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12; - 153 180 mΩ

Fig. 13
VGS = 5 V; ID = 5 A; Tj = 150 °C; - - 389 mΩ
Fig. 12; Fig. 13
Dynamic characteristics
Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 464 619 pF

Coss output capacitance Tj = 25 °C; Fig. 14 - 60 72 pF

Crss reverse transfer - 36 50 pF

capacitance
td(on) turn-on delay time VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; - 7 - ns

tr rise time RG(ext) = 10 Ω; Tj = 25 °C - 89 - ns

td(off) turn-off delay time - 18 - ns

tf fall time - 25 - ns

Source-drain diode
VSD source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.85 1.2 V

trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; - 49 - ns

Qr recovered charge VGS = -10 V; VDS = 30 V; Tj = 25 °C - 130 - nC

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

03nc31 03nc30
25 180
VGS (V) = 10 RDSon
ID
(mΩ)
(A) 5
175
20 4

170

15
165

160
10

3 155
5
150

2.2
0 145
0 2 4 6 8 10 4 6 8 10
VDS (V) VGS (V)

Fig. 5. Output characteristics: drain current as a Fig. 6. Drain-source on-state resistance as a function
function of drain-source voltage; typical values of gate-source voltage; typical values

03aa36 03nc28
10-1 18
gfs
ID (S)
(A) 16
-2
10
14

12
10-3
10
min typ max
8
10-4
6

4
10-5
2

10-6 0
0 1 2 3 0 5 10 15
VGS (V) ID (A)

Tj = 25 °C; VDS = 5 V Fig. 8. Forward transconductance as a function of

Fig. 7. Sub-threshold drain current as a function of drain current; typical values
gate-source voltage

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

03nc29 03nc27
18 5
ID
(A) VGS
16 (V)

14 4

VDD = 14 V VDD = 80 V
12
3
10

8
2
6

4
1
Tj = 150 °C Tj = 25 °C
2

0 0
0 1 2 3 4 0 2 4 6 8 10
VGS (V) QG (nC)

Fig. 9. Transfer characteristics: drain current as a Fig. 10. Gate-source voltage as a function of turn-on
function of gate-source voltage; typical values gate charge; typical values

03aa33 03nc32
2.5 250
VGS(th) RDSon
VGS (V) = 3
(V) (mΩ) 3.2
2 max

200
3.4
1.5 typ 3.6
3.8
4

1 min 5
150

0.5

0 100
-60 0 60 120 180 0 2 4 6 8 10 12
Tj (° C) ID (A)

Fig. 11. Gate-source threshold voltage as a function of Fig. 12. Drain-source on-state resistance as a function
junction temperature of drain current; typical values

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

03ne90 03nc33
2.4 1200
a C (pF)
2.0 1000 Ciss

1.6 800
Coss

1.2 600 Crss

0.8 400

0.4 200

0 0
- 60 20 100 180 10- 2 10- 1 1 10 102
Tj (°C) VDS (V)

Fig. 13. Normalized drain-source on-state resistance Fig. 14. Input, output and reverse transfer capacitances
factor as a function of junction temperature as a function of drain-source voltage; typical
values

03nc26
15
IS
(A)

10

Tj = 150 °C Tj = 25 °C

0
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD (V)

Fig. 15. Reverse diode current as a function of reverse diode voltage; typical value

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

11. Package outline

Plastic surface-mounted package with increased heatsink; 4 leads SOT223

D B E A X

y
HE v M A

b1

A1

1 2 3 Lp

e1 bp w M B detail X

0 2 4 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y

1.8 0.10 0.80 3.1 0.32 6.7 3.7 7.3 1.1 0.95
mm 4.6 2.3 0.2 0.1 0.1
1.5 0.01 0.60 2.9 0.22 6.3 3.3 6.7 0.7 0.85

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

04-11-10
SOT223 SC-73
06-03-16

Fig. 16. Package outline SC-73 (SOT223)

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Product data sheet 16 March 2016 9 / 12

Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

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punitive, special or consequential damages (including - without limitation -
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or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.

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whatsoever, Nexperia’s aggregate and cumulative liability towards
Document Product Definition customer for the products described herein shall be limited in accordance
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Objective Development This document contains data from Right to make changes — Nexperia reserves the right to
[short] data the objective specification for product make changes to information published in this document, including without
sheet development. limitation specifications and product descriptions, at any time and without
Preliminary Qualification This document contains data from the notice. This document supersedes and replaces all information supplied prior
[short] data preliminary specification. to the publication hereof.
sheet
Suitability for use in automotive applications — This Nexperia
Product Production This document contains the product product has been qualified for use in automotive
[short] data specification. applications. Unless otherwise agreed in writing, the product is not designed,
sheet authorized or warranted to be suitable for use in life support, life-critical or
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[1] Please consult the most recently issued document before initiating or malfunction of a Nexperia product can reasonably be expected
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[3] The product status of device(s) described in this document may have inclusion and/or use of Nexperia products in such equipment or
changed since this document was published and may differ in case of applications and therefore such inclusion and/or use is at the customer's own
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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data sheet shall define the specification of the product as agreed between
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customer have explicitly agreed otherwise in writing. In no event however, the Absolute Maximum Ratings System of IEC 60134) will cause permanent
shall an agreement be valid in which the Nexperia product damage to the device. Limiting values are stress ratings only and (proper)
is deemed to offer functions and qualities beyond those described in the operation of the device at these or any other conditions above those
Product data sheet. given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

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12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.

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Nexperia BUK98180-100A
N-channel TrenchMOS logic level FET

13. Contents
1 General description ............................................... 1
2 Features and benefits ............................................1
3 Applications ........................................................... 1
4 Quick reference data ............................................. 1
5 Pinning information ............................................... 2
6 Ordering information ............................................. 2
7 Marking ................................................................... 2
8 Limiting values .......................................................2
9 Thermal characteristics .........................................4
10 Characteristics ....................................................... 5
11 Package outline ..................................................... 9
12 Legal information .................................................10
12.1 Data sheet status ............................................... 10
12.2 Definitions ...........................................................10
12.3 Disclaimers .........................................................10
12.4 Trademarks ........................................................ 11

© Nexperia B.V. 2017. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 March 2016

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