EC1002-2: Applied Digital Logic Design

Department of Electronics and Communication

Engineering
 Unit II
Combinational Logic
and Sequential Logic
Circuits
 UNIT – II

Combinational Logic and Sequential Logic Circuits: Introduction to

Combinational Logic Circuits, Half/Full Adders/Subtractors, Parallel
Adders/Subtractors, Binary Comparators, Decoders, Encoders,
Multiplexers. Basic Bistable Element, SR Flip-Flop, D Flip Flop, JK Flip
Flop, T Flip Flop, Master Slave JK Flip Flop, Characteristic Equations,
Conversion of Flip Flops.
10Hrs

3
Binary addition
Binary subtraction

1
Binary subtraction using 2’s complement method

2’s complement is a complement arithmetic operation

used to find the complement of a given number.

The 2’s complement of a binary number is determined

by taking 1’s complement of the given number and then
adding a 1 to the least significant bit of the 1’s
complement.

1’s complement is an arithmetic operation that performs

the inversion of bits of a binary number.
The 1’s complement of a binary number is determined
by changing all the bits to 0 and 0 bits to 1 of the
number.
For example, consider the binary number (100110111)2.
We have to find the 2’s complement of this number.

Firstly, we find the 1’s complement of this number below.

1’s Complement = (011001000)2

Now, as follows, add 1 to the LSB of 1’s complement to

determine the 2’s complement of the number.
Binary number subtraction using 2’s complement
The following steps are involved in subtraction using the
2’s complement arithmetic.
•Find the 2’s complement of the subtrahend.
•Add the 2’s complement of the subtrahend to the
minuend.
•If there is a carry produced, the result is positive.
Obtain the final result by omitting the carry.
•If there is no carry produced, the result is negative. The
final result is obtained by taking 2’s complement of the
intermediate result and putting a minus sign.
Subtract (1110101)2 – (1000101)2 using 2’s complement
arithmetic.
Minuend = (1110101)2
Subtrahend = (1000101)2
1’s complement of subtrahend = (0111010)2
Therefore, 2’s complement of subtrahend = (0111010)2 +
(1)2 = (0111011)2
Adding 2’s complement of the subtrahend to minuend to
obtain to perform their subtraction.
(1110101)2 + (0111011)2 = (1 0110000)2
Since there is a carry, hence the result is positive. The final
result is obtained by discarding the carry marked in red.
Subtract (1011) 2 from (1110) 2 using 2’s complement method
In this example, Subtrahend (1011) 2 is the smaller than Minuend
number (1110) 2.
Step 1– 1’s complement of subtrahend (1011) 2
Step 2– 2’s complement of number (step 1)
Step 3– Add (1110) 2 and (0101) 2
Perform (1011)2 - (1110)2 from using 2’s complement method
Subtrahend (1110) 2 is larger than Minuend number (1011)2 in this
example.
Step 1– 2’s complement of number (1110)2

Step 2– Add minuend (1011) 2 and 2’s complement of subtrahend

(0010) 2
Step 3– No carry generated, Take 2’s complement of the number
obtained in Step 2
 Half Adder
Half Adder adds to one-bit numbers and produces
two outputs sum and Carry
 Full Adder
A full adder is a combinational logic circuit that performs the
addition of three single-bit numbers.
It is a digital circuit that has three inputs A, B, and C in , where Cin is
the previous carry and two output sum (S), carry (Cout).
Here sum is the least significant bit (LSB) and carry is the most
significant bit (MSB).
A full adder circuit is used in computer ALU (Arithmetic and Logic
Unit ) to perform arithmetic operations.
S
=

=
Full adder using half adder
Sum = A ⊕ B ⊕ C
Carry = AB + (A ⊕ B)C
= AB + (A’B + AB’)C
= AB + A’BC + AB’C
= B (A + A’C) + AB’C
= B [(A + A’)(A + C)] + AB’C
= AB + BC + AB’C
= BC + A(B + B’C)
= BC + A[(B + B’)(B + C)]
= BC + AB + AC
= AB + BC + AC
4-bit ripple carry adder

1 1 0 0 0

1 1 0 1
1 1 0 0
1 1 0 0 1
 4-bit ripple carry adder/Parallel adder

C3 = Cout
Working of Ripple Carry Adder /Parallel adder
• Firstly the Full Adder A adds A0 and B0 along with the carry Cin to
generate the sum S0 (the first bit of the output sum) and the carry
C0 which is connected to the next adder in chain.
• Next, the Full Adder B uses this carry bit C0 to add with the input
bits A1 and B1 to generate the sum S1(the second bit of the
output sum) and the carry C1 which is again further connected to
the next adder in chain and so on.
• The process continues till the last Full Adder D uses the carry bit
C2 to add with its input A3 and B3 to generate the last bit of the
output S3 along with last carry bit C3.
A3 A2 A1 A0  0101
B3 B2 B1 B0  1010
Cin0
------------------------------
S3S2S1S01111
C30
 Half Subtractor
It produces the difference between the two binary bits at the input and
produces two outputs difference and borrow ( to indicate if a 1 has been
borrowed)

In the subtraction (A), A is called a Minuend bit and B is called

a Subtrahend bit.

= A XOR B
 Full Subtractor
• A full subtractor is a combinational circuit that
performs subtraction of two bits, one is minuend
and other is subtrahend, taking into account borrow
of the previous adjacent lower minuend bit. This
circuit has three inputs and two outputs.
• The three inputs A, B and Bin, denote the
minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout
represent the difference and output borrow,
respectively.
 D Bout

Bout =
D
=

=
Parallel Subtractor
Working of Parallel Subtractor
• The parallel binary subtractor is formed by combination of all full
adders with subtrahend complement input.
• This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their subtraction.
• Firstly the 1’s complement of B is obtained by the NOT gate and 1
can be added through the carry to find out the 2’s complement of
B. This is further added to A to carry out the arithmetic subtraction.
• The process continues till the last full adder uses the carry bit to
add with its input A and 2’s complement of B to generate the last
bit of the output S3 along last carry bit C4.
For Subtraction
For a>b, a=b
• If a carry is generated (C4=1) , then ignore the carry
and result will be the difference between a and b.
For a<b
• If no carry (C4=0), then the difference is 2’s
compliment of the result with negative sign
 4-bit Parallel Adder/Subtractor
• In Digital Circuits, a Binary adder/subtractor is capable
of both the addition and subtraction of binary numbers
in one circuit itself.
• The operation is performed depending on the binary
value the control signal holds. It is one of the
components of the ALU (Arithmetic Logic Unit).
• Let’s consider two 4-bit binary numbers A and B as
inputs to the Digital Circuit for the operation with
digits

The circuit consists of 4 full adders since we are performing

operations on 4-bit numbers. There is a control line M that
holds a binary value of either 0 or 1 which determines that
the operation is carried out is addition or subtraction.
Charishma
• When the mode input (M) is at a low logic, i.e. '0',
the circuit acts as an adder and when the mode input
is at a high logic, i.e. '1', the circuit acts as a
subtractor.
• The exclusive-OR gate connected in series receives
input M and one of the inputs B.
• When M is at a low logic, we have B⊕ 0 = B.
The full adders receive the value of B, the input
carry is 0, and the circuit performs A plus B.
• When M is at a high logic, we have B⊕ 1 = B' and
C0 = 1. The B inputs are complemented, and a 1 is
added through the input carry. The circuit performs
the operation A plus the 2's complement of B.
Charishma
 Examples
M=0: A = 0001,B = 0000
S = 0001, C4= 0

M=0: A = 0010,B = 0100

S = 0110, C4 = 0

M=0: A = 1011,B = 0110

S = 0001, C4 = 1
M=1: A = 0001,B = 0000
S = 0001,C4= 1

M=1: A = 0010, B = 0100

S = 1110, C4= 0

M=1: A = 1011, B = 0110

S = 0101, C4 = 1

M=1: A = 0101, B = 0011

S = 0010, C4= 1
1-bit comparator
2- bit comparator
Multiplexer(MUX)
Application of MUX
+S
4:1 Multiplexer

𝑌 = 𝐵 𝐴 𝐷0 + 𝐵 𝐴 𝐷 1+ 𝐵 𝐴 𝐷2 + 𝐵𝐴 𝐷 3
8:1 Multiplexer
8:1 Multiplexer
Implement the following function using 4:1 MUX
a b c f
0 0 0 1 1
0 0 1 1
0 1 0 1 C’
0 1 1 0
1 0 0 0 0
1 0 1 0
1 1 0 0 c
1 1 1 1
Implement the following function using 4:1 MUX, use b and c as select lines

a b c f
a b c f
0 0 0 0 a
0 0 0 0
1 0 0 1
0 0 1 1
0 0 1 1 1
0 1 0 0
1 0 1 1
0 1 1 0
0 1 0 0 0
1 0 0 1
1 1 0 0
1 0 1 1
0 1 1 0 a
1 1 0 0
1 1 1 1
1 1 1 1
 Encoder
An Encoder is a combinational circuit that performs the reverse
operation of a Decoder.
It has a maximum of 2n input lines and ‘n’ output lines, hence it
encodes the information from 2n inputs into an n-bit code.
It will produce a binary code equivalent to the input, which is
active High.
Therefore, the encoder encodes 2n input lines with ‘n’ bits.
Example of Encoder
4x2 Encoder
8x3 Encoder (Octal to Binary encoder)

outputs
inputs
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
 Decoder
• The combinational circuit that change the binary
information into 2N output lines is known as Decoders.
• The binary information is passed in the form of N input
lines.
• The output lines define the 2N-bit code for the binary
information.
• In simple words, the Decoder performs the reverse
operation of the Encoder.
• At a time, only one input line is activated for simplicity.
The produced 2N-bit output code is equivalent to the binary
information.
2 to 4 decoder with active high outputs
3 to 8 decoder with active high outputs
Truth Table of 3:8 decoder
 Encoder
An Encoder is a combinational circuit that performs the reverse
operation of a Decoder.
It has a maximum of 2n input lines and ‘n’ output lines, hence it
encodes the information from 2n inputs into an n-bit code.
It will produce a binary code equivalent to the input, which is
active High.
Therefore, the encoder encodes 2n input lines with ‘n’ bits.
4x2 Encoder
 8x3 Encoder

outputs
inputs
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
Additional Problem Statements
BCD to Excess-3 Conversion

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25/06/2024 86
25/06/2024 87
The final set of output equations are
W= A + BD + BC
X = B’C + B’D + BC’D’
Y = C’D’ + CD
Z = D’

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Excess-3 to BCD
Excess-3 code is also a Self complementing code
Binary to gray code conversion
Binary to gray code conversion
Gray to Binary code conversion
Gray code is also called unit distance code
Binary Multiplier