18-Bit Stereo Audio Codec, Single-Ended Analog Input/Output: Features
18-Bit Stereo Audio Codec, Single-Ended Analog Input/Output: Features
18-Bit Stereo Audio Codec, Single-Ended Analog Input/Output: Features
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCM3000
PCM3001
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SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless
otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Input Logic
VIH (1) 2
Input logic level VDC
VIL (1) 0.8
IIN (2) ±1
Input logic current µA
IIN (3) –120
VIH (4) 0.64 VDD VDC
Input logic level
VIL (4) 0.28 VDD
IIN (4) Input logic current ±40 µA
Output Logic
VOH (5) IOUT = –1.6 mA 4.5
Output logic level
VOL (5) IOUT = 3.2 mA 0.5
VDC
VOH (6) IOUT = –3.2 mA 4.5
Output logic level
VOL (6) IOUT = 3.2 mA 0.5
Clock Frequency
fS Sampling frequency 4 (7) 44.1 48 kHz
256 fS 1.024 11.2896 12.288
System clock frequency 384 fS 1.536 16.9344 18.432 MHz
512 fS 2.048 22.5792 24.576
ADC CHARACTERISTICS
Resolution 18 Bits
DC Accuracy
Gain mismatch, channel-to-channel ±1 ±5
% of FSR
Gain error ±2 ±5
Gain drift ±20 ppm of FSR/°C
Bipolar zero error High-pass filter off (8) ±1.7 % of FSR
Bipolar zero drift High-pass filter off (8) ±20 ppm of FSR/°C
(1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB
(2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt-trigger input)
(3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt-trigger input, 70-kΩ internal pullup resistor)
(4) Pin 20: XTI
(5) Pins 19, 22: DOUT, CLKIO
(6) Pin 21: XTO
(7) Refer to Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies.
(8) High-pass filter disabled (PCM3000 only) to measure dc offset
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(9) fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF, 400-Hz HPF
used for performance calculation or measurement.
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PACKAGE/ORDERING INFORMATION
PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE QUANTITY
CODE MARKING NUMBER MEDIA
PCM3000E Rails 47
PCM3000E PCM3000E
PCM3000E/2K Tape and reel 2000
28-pin SSOP DB
PCM3001E Rails 47
PCM3001E PCM3001E
PCM3001E/2K Tape and reel 2000
4
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PCM3001
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5
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PCM3001
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PIN CONFIGURATION—PCM3000/3001
PCM3000 PCM3001
(TOP VIEW) (TOP VIEW)
P0007-01
PIN ASSIGNMENTS—PCM3000
NAME PIN I/O DESCRIPTION
AGND1 3 – ADC analog ground
AGND2 13 – DAC analog ground
BCKIN 17 I Bit clock input (1)
CINNL 9 – ADC antialias filter capacitor (–), Lch
CINNR 8 – ADC antialias filter capacitor (–), Rch
CINPL 10 – ADC antialias filter capacitor (+), Lch
CINPR 7 – ADC antialias filter capacitor (+), Rch
CLKIO 22 I/O Buffered oscillator output or external clock input (1)
DGND 24 – Digital ground
DIN 18 I Data input (1)
DOUT 19 O Data output
LRCIN 16 I Sample rate clock input (fS) (1)
MC 25 I Serial mode control, bit clock
MD 26 I Serial mode control, data
ML 27 I Serial mode control, strobe pulse
RSTB 28 I Reset, active-low (1) (2)
VCC1 2 – ADC analog power supply
VCC2 14 – DAC analog power supply
VDD 23 – Digital power supply
VCOM 11 – DAC output common
VINL 1 I ADC analog input, Lch
VINR 6 I ADC analog input, Rch
VOUTL 15 O DAC analog output, Lch
VOUTR 12 O DAC analog output, Rch
VREFL 4 – ADC input reference, Lch
VREFR 5 – ADC input reference, Rch
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PIN ASSIGNMENTS—PCM3001
NAME PIN I/O DESCRIPTION
AGND1 3 – ADC analog ground
AGND2 13 – DAC analog ground
BCKIN 17 I Bit clock input (1)
CINNL 9 – ADC antialias filter capacitor (–), Lch
CINNR 8 – ADC antialias filter capacitor (–), Rch
CINPL 10 – ADC antialias filter capacitor (+), Lch
CINPR 7 – ADC antialias filter capacitor (+), Rch
CLKIO 22 I/O Buffered oscillator output or external clock input (1)
DGND 24 – Digital ground
DIN 18 I Data input (1)
DOUT 19 O Data output
FMT0 27 I Audio data format control 0 (1) (2)
FMT1 26 I Audio data format control 1 (1) (2)
FMT2 25 I Audio data format control 2 (1) (2)
LRCIN 16 I Sample rate clock input (fS) (1)
RSTB 28 I Reset, active-low (1) (2)
VCC1 2 – ADC analog power supply
VCC2 14 – DAC analog power supply
VDD 23 – Digital power supply
VCOM 11 – DAC output common
VINL 1 I ADC analog input, Lch
VINR 6 I ADC analog input, Rch
VOUTL 15 O DAC analog output, Lch
VOUTR 12 O DAC analog output, Rch
VREFL 4 – ADC input reference, Lch
VREFR 5 – ADC input reference, Rch
XTI 20 I Oscillator input
XTO 21 O Oscillator output
7
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PCM3001
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SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
THD+N THD+N
vs vs
TEMPERATURE POWER SUPPLY
0.010 4 0.010 4
0.006 2 0.006 2
FS
0.004 1 0.004 1
FS
0.002 0 0.002 0
−25 0 25 50 75 100 4.25 4.50 4.75 5.00 5.25 5.50 5.75
TA − Free-Air Temperature − °C VCC − Supply Voltage − V
G001 G002
Figure 1. Figure 2.
−60 dB
Dynamic Range
0.006 48 kHz 2 94 94
48 kHz SNR
0.004 1 92 92
FS
44.1 kHz
0.002 0 90 90
256 fS 384 fS 512 fS 4.25 4.50 4.75 5.00 5.25 5.50 5.75
System Clock VCC − Supply Voltage − V
G004
G003
Figure 3. Figure 4.
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THD+N
vs
OUTPUT DATA RESOLUTION
0.010 4
0.008 −60 dB 3
0.006 2
FS
0.004 1
0.002 0
16-Bit 18-Bit
Resolution
G005
Figure 5.
THD+N THD+N
vs vs
TEMPERATURE POWER SUPPLY
0.010 4 0.010 4
THD+N − Total Harm. Dist. + Noise at −60 dB − %
0.008 3 0.008 3
−60 dB −60 dB
0.006 2 0.006 2
FS
0.004 1 0.004 1
FS
0.002 0 0.002 0
−25 0 25 50 75 100 4.25 4.50 4.75 5.00 5.25 5.50 5.75
TA − Free-Air Temperature − °C VCC − Supply Voltage − V
G006 G007
Figure 6. Figure 7.
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PCM3001
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Dynamic Range
Dynamic Range − dB
48 kHz SNR
0.006 2 96 96
−60 dB
44.1 kHz
0.002 0 92 92
256 fS 384 fS 512 fS 4.25 4.50 4.75 5.00 5.25 5.50 5.75
System Clock VCC − Supply Voltage − V
G008 G009
Figure 8. Figure 9.
THD+N
vs
INPUT DATA RESOLUTION
0.010 4 THD+N − Total Harm. Dist. + Noise at −60 dB − %
THD+N − Total Harm. Dist. + Noise at FS − %
0.008 3
−60 dB
0.006 2
FS
0.004 1
0.002 0
16-Bit 18-Bit
Resolution
G010
Figure 10.
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PCM3001
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SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
DECIMATION FILTER
−20
−50
Amplitude − dB
Amplitude − dB
−40
−100
−60
−150
−80
−200 −100
0 8 16 24 32 0.0 0.2 0.4 0.6 0.8 1.0
Normalized Frequency [× fS Hz] Normalized Frequency [× fS Hz]
G011 G012
0.0
−0.2
Amplitude − dB
−0.4
−0.6
−0.8
−1.0
0.0 0.1 0.2 0.3 0.4 0.5
Normalized Frequency [× fS Hz]
G013
Figure 13.
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0.0
−0.2
Amplitude − dB
−0.4
−0.6
−0.8
−1.0
0 1 2 3 4
Normalized Frequency [× fS/1000 Hz]
G014
Figure 14.
ANTIALIASING FILTER
470 pF 470 pF
0.0
−10
−0.2
Amplitude − dB
Amplitude − dB
−20
−0.4
−40
−0.8
−1.0 −50
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 1M 10M
f − Frequency − Hz f − Frequency − Hz
G015 G016
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DIGITAL FILTER
−20 −0.2
−40 −0.4
Level − dB
Level − dB
−60 −0.6
−80 −0.8
−100 −1.0
0 0.4536 fS 1.3605 fS 2.2675 fS 3.1745 fS 4.0815 fS 0 0.1134 fS 0.2268 fS 0.3402 fS 0.4535 fS
f − Frequency − Hz f − Frequency − Hz
G017 G018
DE-EMPHASIS FILTER
−2 0.4
−4 0.2
Level − dB
Error − dB
−6 0.0
−8 −0.2
−10 −0.4
−12 −0.6
0 5k 10k 15k 20k 25k 0 3628 7256 10884 14512
f − Frequency − Hz f − Frequency − Hz
G019 G020
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−2 0.4
−4 0.2
Level − dB
Error − dB
−6 0.0
−8 −0.2
−10 −0.4
−12 −0.6
0 5k 10k 15k 20k 25k 0 4999.8375 9999.675 14999.5125 19999.35
f − Frequency − Hz f − Frequency − Hz
G021 G022
−2 0.4
−4 0.2
Level − dB
Error − dB
−6 0.0
−8 −0.2
−10 −0.4
−12 −0.6
0 5k 10k 15k 20k 25k 0 5442 10884 16326 21768
f − Frequency − Hz f − Frequency − Hz
G023 G024
14
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INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20 Hz–24 kHz, EXPANDED SCALE) (10 Hz–10 MHz)
1.0 10
5
0
−5
0.5
−10
−15
Level − dB
Level − dB
−20
0.0 −25
−30
−35
−40
−0.5
−45
−50
−55
−1.0 −60
20 100 1k 10k 24k 10 100 1k 10k 100k 1M 10M
f − Frequency − Hz f − Frequency − Hz
G025 G026
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SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Block Diagram
CINPL
CINNL
(+)
Analog Decimation
Delta-Sigma
VINL Front-End and LRCIN
(−) Modulator
Circuit High-Pass Filter
BCKIN
VREFL
Serial Data
Reference ADC
Interface
VREFR
DIN
(−)
Analog Decimation
Delta-Sigma
VINR Front-End and DOUT
(+) Modulator
Circuit High-Pass Filter
CINNR
Loop Control
CINPR
ML(FMT0)(1)
Analog Multilevel Interpolation
VOUTL Low-Pass Delta-Sigma Filter Mode
Filter Modulator 8× Oversampling Control MC(FMT2)(1)
Interface
Reset RSTB
16
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PCM3001
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470 pF
CINPL 10 9 CINNL
2.2 µF
VINL 15 kΩ
1 −
+
− 1 kΩ
(+)
+
+ Delta-Sigma
1 kΩ Modulator
(−)
VREFL
4
4.7 µF +
VREF
S0011-04
17
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SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
BCKIN
DIN 16 1 2 3 14 15 16 1 2 3 14 15 16
MSB LSB MSB LSB
BCKIN
DOUT 1 2 3 14 15 16 1 2 3 14 15 16 1
MSB LSB MSB LSB
BCKIN
DIN 18 1 2 3 16 17 18 1 2 3 16 17 18
MSB LSB MSB LSB
BCKIN
DOUT 1 2 3 16 17 18 1 2 3 16 17 18 1
MSB LSB MSB LSB
T0016-07
18
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BCKIN
DIN 16 1 2 3 14 15 16 1 2 3 14 15 16
MSB LSB MSB LSB
BCKIN
DOUT 16 1 2 3 14 15 16 1 2 3 14 15 16
MSB LSB MSB LSB
BCKIN
DIN 18 1 2 3 16 17 18 1 2 3 16 17 18
MSB LSB MSB LSB
BCKIN
DOUT 18 1 2 3 16 17 18 1 2 3 16 17 18
MSB LSB MSB LSB
T0016-08
19
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BCKIN
DIN 1 2 3 16 17 18 1 2 3 16 17 18 1
MSB LSB MSB LSB
BCKIN
DOUT 1 2 3 16 17 18 1 2 3 16 17 18 1
MSB LSB MSB LSB
BCKIN
DIN 1 2 3 16 17 18 1 2 3 16 17 18
MSB LSB MSB LSB
BCKIN
DOUT 1 2 3 16 17 18 1 2 3 16 17 18
MSB LSB MSB LSB
T0016-09
20
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BCKIN
DIN 16 1 2 3 14 15 16 1 2 3 14 15 16 1
MSB LSB MSB LSB
BCKIN
DOUT 16 1 2 3 14 15 16 1 2 3 14 15 16 1
MSB LSB MSB LSB
T0016-10
21
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t(LRP)
LRCIN 1.4 V
t(BCL) t(LB)
t(BCH) t(BL)
BCKIN 1.4 V
DIN 1.4 V
t(BDO) t(LDO)
T0021−02
SYSTEM CLOCK
The system clock for the PCM3000/3001 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling
frequency. The system clock can be either a crystal oscillator placed between XTI (pin 20) and XTO (pin 21), or
an external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (pin 22), and
XTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating.
When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected to
ground, the external clock must be tied to CLKIO. For best performance, the external-clock-input-2 circuit in
Figure 23 is recommended.
The PCM3000/3001 also has a system-clock detection circuit which automatically senses if the system clock is
operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided into
256 fS automatically. The 256-fS clock is used to operate the digital filters and the modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 23 and
Figure 24 illustrate the typical system clock connections and external system clock timing.
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CLKIO
Clock Divider
C1
Xtal XTI
R
C2
XTO
C1 = C2 = 10 to 33 pF PCM3000/3001
R R
XTO XTO
PCM3000/3001 PCM3000/3001
External Clock Input 1 : (XTO is open) External Clock Input 2 : (XTO is open)
S0017−01
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t(CLKIH)
XTI CLKIO
3.2 V 2.0 V
XTI or CLKIO
1.4 V 0.8 V
t(CLKIL)
T0005-06
POWER-ON RESET
The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI or
CLKIO) is active and VDD > 4 V. For the PCM3001, the system clock must complete a minimum of 3 complete
cycles prior to VDD > 4 V to ensure proper reset operation. The initialization sequence requires 1024 system
cycles for completion, as shown in Figure 25. Figure 26 shows the state of the DAC and ADC outputs during and
after the reset sequence.
4.4 V
VDD 4.0 V
3.6 V
Internal Reset
3 Clocks Minimum
System Clock
(XTI or CLKIO)
T0014-04
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32/fS
(0.5 VCC2)
4096/fS
T0019-03
Figure 26. DAC Output and ADC Output for Reset and Power Down
EXTERNAL RESET
The PCM3000/3001 includes a reset input, RSTB (pin 28). As shown in Figure 27, the external reset signal must
drive RSTB low for a minimum of 40 nanoseconds while the system clock is active in order to initiate the reset
sequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion.
Figure 26 shows the state of the DAC and ADC outputs during and after the reset sequence.
t(RST) = 40 ns (min)
RSTB Pulse Duration
RSTB
t(RST)
Internal Reset
25
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32/fS
Undefined
ADC DOUT Normal Data Data Zero Data Normal Data(1)
T0020-04
(1) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appears
initially.
Figure 28. DAC Output and ADC Output For Loss of Synchronization
OPERATIONAL CONTROL
The PCM3000 can be controlled in the software mode with a three-wire serial interface on MC (pin 25),
MD (pin 26), and ML (pin 27). Table 2 indicates selectable functions, and Figure 29 and Figure 30 illustrate
control data input format and timing. The PCM3001 only allows for control of data format.
ML
MC
T0023-01
26
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t(MHH)
t(MLH)
t(MLS)
ML 1.4 V
t(MCL)
t(MLL)
t(MCH)
MC 1.4 V
t(MCY)
LSB
MD 1.4 V
t(MDS)
t(MDH)
T0024-01
REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
REGISTER 2 res res res res res A1 A0 PDWN BYPS res ATC IZD OUT DEM1 DEM0 MUT
REGISTER 3 res res res res res A1 A0 res res res LOP FMT2 FMT1 FMT0 LRP res
NOTE: res indicates a reserved bit, which should be set to 0.
27
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PROGRAM REGISTER 0
res: Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits definte the address for REGISTER 0:
A1 A0
0 0 Register 0
LDL: Bit 8 – DAC Attenuation Data Load Control for Left Channel
This bit is used to simultaneously set the analog outputs of the left and right channels. The output
level is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is stored into a register, and the output level remains at the previous attenuation
level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is
set to 1, the output levels of the left and right channels are simultaneously controlled.
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PROGRAM REGISTER 1
res: Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits definte the address for REGISTER 1.
A1 A0
0 1 Register 1
LDR: Bit 8 – DAC Attenuation Data Load Control for Right Channel
This bit is used to simultaneously set the analog outputs of the left and right channels. The output
level is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new
attenuation data is stored into a register, and the output level remains at the previous attenuation
level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is
set to 1, the output levels of the left and right channels are simultaneously controlled.
AR[7:0]: Bits 7:0 – DAC Attenuation Data for Right Channel
AR7 and AR0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by
ATT = 20 × log10 (AR[7:0]/256) (dB), except AR[7:0] = FFh
AR[7:0] ATTENUATION LEVEL
00h – ∞ dB (mute)
01h –48.16 dB
: :
FEh –0.07 dB
FFh 0 dB (default)
PROGRAM REGISTER 2
res: Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits define the address for REGISTER 2:
A1 A0
1 0 Register 2
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PROGRAM REGISTER 3
res: Bits 15:11 – Reserved
These bits are reserved and should be set to 0.
A[1:0]: Bits 10:9 – Register Address
These bits define the address for REGISTER 3.
A1 A0
1 1 Register 3
31
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THEORY OF OPERATION
ADC SECTION
The PCM3000/3001 ADC consists of a band-gap reference, a stereo single-to-differential converter, a fully
differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface
circuit. The block diagram in this data sheet illustrates the architecture of the ADC section. Figure 17 shows the
single-to-differential converter, and Figure 31 illustrates the architecture of the 5th-order delta-sigma modulator
and transfer functions.
An internal high-precision reference with two external capacitors provides all reference voltages required by the
ADC, which defines the full scale range for the converter. The internal single-to-differential voltage converter
saves the space and extra parts needed for external circuitry which is required by many delta-sigma converters.
The internal full-differential signal processing architecture provides a wide dynamic range and excellent power
supply rejection performance.
The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and
simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators
which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The
delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.
The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
The 64-fS 1-bit data stream from the modulator is converted to 1-fS, 18-bit data words by the decimation filter,
which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed
by a high-pass filter function contained within the decimation filter.
Analog
In
1st − 2nd 3rd − 4th 5th
X(z) + + +
SW-CAP SW-CAP SW-CAP SW-CAP SW-CAP
− Integrator Integrator Integrator Integrator Integrator Qn(z)
Digital
Out
+ + + +
+ + + + Y(z)
H(z) Comparator
1-Bit
DAC
DAC SECTION
The delta-sigma DAC section of the PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order
noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram
of the 5-level delta-sigma modulator is shown in Figure 32. This 5-level delta-sigma modulator has the advantage
of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for a
256-fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is
shown in Figure 33.
32
PCM3000
PCM3001
www.ti.com
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
In + + +
+ + +
8 fS Z−1 Z−1 Z−1
− −
18-Bit
+
+ +
5-Level Quantizer
4
3
Out
2
64 fS
1
0
B0008-02
0
−10
−20
−30
−40
−50
−60
Gain − dB
−70
−80
−90
−100
−110
−120
−130
−140
−150
0 5 10 15 20 25 30
f − Frequency − kHz
G027
33
PCM3000
PCM3001
www.ti.com
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
APPLICATION INFORMATION
TYPICAL CONNECTION
A typical connection diagram for the PCM3000/3001 is shown in Figure 34.
+5V
Register Control
1 28 Reset
Interface
2 27 Serial
(1) Control
3 26 or
4.7 µF Format
2.2 µF(2) + +
Line In Left-Channel 4 25 Control
Reference
4.7 µF +
5 24
Analog Analog
(1)
2.2 µF(2) + Front-End Front-End
Line In Right-Channel 6 23
7 22
10 to 33 pF
470 pF Delta-Sigma
8 21
CLK/OSC
9 Manager 20
470 pF
10 Decimation 19
Filter Digital
4.7 µF +
11 Audio 18 Digital
Interpolation Interface
Post Audio
Filter
Line Out Right-Channel Low-Pass 12 17 Data
Filter
Delta-Sigma
13 16
(1) Bias
14 15
LPF and LPF and
Buffer Buffer
Post
Line Out Left-Channel Low-Pass
Filter
S0018-01
34
PCM3000
PCM3001
www.ti.com
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
VOLTAGE INPUTS
A tantalum or aluminum electrolytic capacitor, between 2.2 µF and 10 µF, is recommended as an ac-coupling
capacitor at the inputs. Combined with the 15-kΩ characteristic input impedance, a 2.2-µF coupling capacitor
establishes a 4.8-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a
series resistor on the analog input line. This series resistor, when combined with the 15-kΩ input impedance,
creates a voltage divider and enables larger input ranges.
VREF INPUTS
A 4.7-µF to 10-µF tantalum capacitor is recommended between VREFL, VREFR, and AGND1 to ensure low source
impedance for the ADC references. These capacitors should be located as close as possible to the reference
pins to reduce dynamic errors on the ADC reference.
VCOM INPUT
A 4.7-µF to 10-µF tantalum capacitor is recommended between VCOM and AGND2 to ensure low source
impedance of the DAC output common. This capacitor should located as close as possible to the VCOM pin to
reduce dynamic errors on the DAC common.
SYSTEM CLOCK
The quality of the system clock can influence the dynamic performance of both the ADC and DAC in the
PCM3000/3001. The duty cycle, jitter, and threshold voltage at the system clock input pin should be carefully
managed. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) must
also be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of up
to three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit is
exceeded.
RSTB CONTROL
If capacitors greater than 4.7 µF are used on VREF and VCOM, an external reset control with delay time
corresponding to the VREF, VCOM response is required.
35
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
PCM3000E ACTIVE SSOP DB 28 47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3000E/2K ACTIVE SSOP DB 28 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3000E/2KG4 ACTIVE SSOP DB 28 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3000EG4 ACTIVE SSOP DB 28 47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3001E ACTIVE SSOP DB 28 47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3001E/2K ACTIVE SSOP DB 28 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3001E/2KG4 ACTIVE SSOP DB 28 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM3001EG/2K ACTIVE Pb-Free CU SNBI Level-1-260C-UNLIM
(RoHS)
PCM3001EG4 ACTIVE SSOP DB 28 47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 2
MECHANICAL DATA
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
PINS **
14 16 20 24 28 30 38
DIM
4040065 /E 12/01