4NF20L STMicroelectronics PDF
4NF20L STMicroelectronics PDF
4NF20L STMicroelectronics PDF
Features
RDS(on)
Order code VDSS ID
max.
STN4NF20L 200 V < 1.5 Ω 1A 2
Application
Switching applications
Description
This N-channel 200 V realized with Figure 1. Internal schematic diagram
STMicroelectronics unique STripFET™ process
has specifically been designed to minimize input
$
capacitance and gate charge. It is therefore
suitable as primary switch in advanced high
efficiency isolated DC-DC converters.
'
3
!-V
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1 Electrical ratings
2 Electrical characteristics
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0 200 V
breakdown voltage
Zero gate voltage VDS = Max rating 1 µA
IDSS
drain current (VGS = 0) VDS = Max rating, TC=125 °C 50 µA
Gate-body leakage
IGSS VGS = ± 20 V, VDS=0 ± 100 nA
current (VDS = 0)
VGS(th) Gate threshold voltage VGS = VDS, ID = 250 µA 1 2 3 V
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Ciss 150 pF
Output capacitance VDS = 25 V, f = 1 MHz,
Coss - 30 - pF
Reverse transfer VGS = 0
Crss 4 pF
capacitance
Instrinsic gate
Rg f=1 MHz open drain - 5.5 - Ω
resistance
Qg Total gate charge VDD = 160 V, ID = 1 A, 0.9 nC
Qgs Gate-source charge VGS = 10 V - 2.6 - nC
Qgd Gate-drain charge (see Figure 13) 6.9 nC
Source-drain current
ISD 1 A
Source-drain current -
ISDM (1) 4 A
(pulsed)
VSD (2) Forward on voltage ISD = 1 A, VGS = 0 - 1.6 V
trr Reverse recovery time ISD = 1 A, di/dt = 100 A/µs 51 ns
Qrr Reverse recovery charge VDD = 60 V - 90 nC
IRRM Reverse recovery current (see Figure 14) 3.5 A
trr Reverse recovery time ISD = 1 A, di/dt = 100 A/µs 56 ns
Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 105 nC
IRRM Reverse recovery current (see Figure 14) 3.7 A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
1
n)
R re
(o
10µs
m is a
DS
by in th
ax
ite tion
100µs
Lim era
d
Op
0.1 1ms
10ms
0.01
0.1 1 10 100 VDS(V)
1
1
3V
0 0
0 10 20 VDS(V) 0 1 2 3 4 5 6 7 8 9 VGS(V)
1.03
1.01 1.04 VGS=10V
0.99
0.97 1.02
0.95
0.93 1
-50 -25 0 25 50 75 100 TJ(°C) 0 0.2 0.4 0.6 0.8 1 ID(A)
100
2
Coss
0 0 0 Crss
0 1 2 3 4 5 6 7 8 Qg(nC) 0 10 20 30 40 50 60 VDS(V)
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature temperature
AM08192v1 AM08193v1
VGS(th) RDS(on)
(norm) (norm)
1.10 2.1
1.9
1.00 1.7
1.5
0.90 1.3
1.1
0.80 0.9
0.7
0.70 0.5
-50 -25 0 25 50 75 100 TJ(°C) -50 -25 0 25 50 75 100 TJ(°C)
3 Test circuits
Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit
resistive load
VDD
12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. μF 2.7kΩ VG
PW
47kΩ
PW 1kΩ
AM01468v1 AM01469v1
Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test
switching and diode recovery times circuit
L
A A A
D
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
S B 3.3 1000
B B μF μF
25 Ω VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform
90% 90%
IDM
10%
ID 10% VDS
0
mm.
DIM.
min. typ max.
A 1.80
A1 0.02 0.1
e 2.30
e1 4.60
V 10 o
0046067_L
5 Revision history
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