STP100NF04
STP100NF04
STP100NF04
Features
RDS(on)
Order code VDS ID Ptot
TAB max.
TAB
STB100NF04T4 40 V 4.6 mΩ 120 A 300 W
STP100NF04 40 V 4.6 mΩ 120 A 300 W
3
D2PAK TO-220 2 AEC-Q101 qualified
1
Exceptional dv/dt capability
100% avalanche tested
Low gate charge
D(2, TAB)
Description
These Power MOSFETs have been developed
using STMicroelectronics’ unique STripFET
process, which is specifically designed to
G(1) minimize input capacitance and gate charge. This
renders the devices suitable for use as primary
switch in advanced high-efficiency isolated DC-
DC converters for telecom and computer
S(3)
applications, and applications with low gate
charge driving requirements.
AM01475v1_Tab
Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Spice thermal model ..................................................................... 10
4 Test circuits ................................................................................... 11
5 Package information ..................................................................... 12
5.1 D²PAK packing information ............................................................. 12
5.2 D²PAK packing information ............................................................. 15
5.3 TO-220 package information ........................................................... 17
6 Revision history ............................................................................ 19
1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 40 V
VGS Gate- source voltage ±20 V
(1)
ID Drain current (continuous) at TC = 25°C 120 A
(1)
ID Drain current (continuous) at TC=100°C 120 A
(2)
IDM Drain current (pulsed) 480 A
PTOT Total dissipation at TC = 25°C 300 W
dv/dt(3) Peak diode recovery voltage slope 6 V/ns
(4)
EAS Single pulse avalanche energy 1.2 J
Tj Operating junction temperature range
- 55 to 175 °C
Tstg Storage temperature range
Notes:
(1)Current limited by package
(2)Pulse width limited by safe operating area.
(3)I
SD ≤120 A, di/dt ≤300A/μs, VDD =V(BR)DSS, Tj ≤ TJMAX
(4)Starting Tj = 25 °C, ID = 60 A, VDD = 30 V.
Notes:
(1)When mounted on a 1-inch² FR-4 board, 2oz Cu.
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4: On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage ID = 250 µA, VGS = 0 V 40 V
VDS = 40 V, VGS = 0 V 1 µA
IDSS Zero gate voltage drain current VDS = 40 V, VGS = 0 V
10 µA
TC = 125°C(1)
IGSS Gate body leakage current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 4 V
RDS(on) Static drain-source on- resistance VGS = 10 V, ID= 50 A 4.3 4.6 mΩ
Notes:
(1)Defined by design,not subject to production test
Table 5: Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 5100 pF
VDS = 25 V, f = 1 MHz,
Coss Output capacitance - 1300 pF
VGS = 0 V
Crss Reverse transfer capacitance - 160 pF
Qg Total gate charge VDD = 32 V, ID = 120 A , - 110 150 nC
VGS = 10 V
Qgs Gate-source charge - 35 nC
(see Figure 21: "Test
Qgd Gate-drain charge circuit for gate charge - 70 nC
behavior")
td(on) Turn-on delay time VDD = 20 V, ID = 60 A , - 35 ns
tr Rise time RG = 4.7 Ω ,VGS = 10 V - 220 ns
(see Figure 20: "Test
td(off) Turn-off delay time circuit for resistive load - 80 ns
switching times" and
tf Fall time Figure 25: "Switching - 50 ns
time waveform")
Notes:
(1)
Pulse width limited by safe operating area.
(2)Pulsed: Pulse duration = 300 μs, duty cycle 1.5%
Figure 10: Normalized gate threshold voltage vs. Figure 11: Normalized on-resistance vs.
temperature temperature
Figure 12: Source-drain diode forward characteristics Figure 13: Normalized BVDSS vs. temperature
Figure 16: Max power dissipation vs. PCB copper area Figure 17: Safe operating area
The previous curve give the safe operating area for unclamped inductive loads, single
pulse or repetitive, under the following conditions:
PD(AVE) = 0.5*(1.3*BVDSS*IAV)
EAS(AR)= PD(AVE)*TAV
Where:
IAV is the allowable current in avalanche
PD(AVE) is the average power dissipation in avalnche(single pulse)
tAV is the time in avalanche
To de rate above 25°C, at fixed IAV, the following equation must be applied:
IAV= 2*(Tjmax-TCASE)/(1.3*BVDSS*Zth)
Where:
Zth= K*Rth is the value coming from normalized thermal response at fixed pulse width
equal to TAV
4 Test circuits
Figure 20: Test circuit for resistive load Figure 21: Test circuit for gate charge
switching times behavior
Figure 22: Test circuit for inductive load Figure 23: Unclamped inductive load test
switching and diode recovery times circuit
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
0079457_A_rev22
6 Revision history
Table 12: Document revision history
Date Revision Changes
23-Mar-2005 2 New template
01-Mar-2006 3 Removed I²PAK and inserted D²PAK.
04-Sep-2006 4 New template,no content change
20-Feb-2007 5 Typo mistake on page 1
Minor text changes – Modified: Figure 17 – Updated: Section 4:
16-Mar-2013 6
Package mechanical data and Section 5: Packaging mechanical data
Updated title in cover page.
21-Nov-2016 7 Updated Section 2: "Electrical characteristics".
Minor text changes.
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