STP100NF04

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STB100NF04T4, STP100NF04

Automotive-grade N-channel 40 V, 4.3 mΩ typ., 120 A


STripFET™ II Power MOSFET in a D²PAK and TO-220
Datasheet packages
- production data

Features
RDS(on)
Order code VDS ID Ptot
TAB max.
TAB
STB100NF04T4 40 V 4.6 mΩ 120 A 300 W
STP100NF04 40 V 4.6 mΩ 120 A 300 W

3
D2PAK TO-220 2  AEC-Q101 qualified
1
 Exceptional dv/dt capability
 100% avalanche tested
 Low gate charge

Figure 1: Internal schematic diagram Applications


 Switching applications

D(2, TAB)
Description
These Power MOSFETs have been developed
using STMicroelectronics’ unique STripFET
process, which is specifically designed to
G(1) minimize input capacitance and gate charge. This
renders the devices suitable for use as primary
switch in advanced high-efficiency isolated DC-
DC converters for telecom and computer
S(3)
applications, and applications with low gate
charge driving requirements.

AM01475v1_Tab

Table 1: Device summary


Order code Marking Package Packing
STB100NF04T4 B100NF04 D²PAK Tape and reel
STP100NF04 P100NF04 TO-220 Tube

November 2016 DocID9969 Rev 7 1/20


This is information on a product in full production. www.st.com
Contents STB100NF04T4, STP100NF04

Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Spice thermal model ..................................................................... 10
4 Test circuits ................................................................................... 11
5 Package information ..................................................................... 12
5.1 D²PAK packing information ............................................................. 12
5.2 D²PAK packing information ............................................................. 15
5.3 TO-220 package information ........................................................... 17
6 Revision history ............................................................................ 19

2/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Electrical ratings

1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 40 V
VGS Gate- source voltage ±20 V
(1)
ID Drain current (continuous) at TC = 25°C 120 A
(1)
ID Drain current (continuous) at TC=100°C 120 A
(2)
IDM Drain current (pulsed) 480 A
PTOT Total dissipation at TC = 25°C 300 W
dv/dt(3) Peak diode recovery voltage slope 6 V/ns
(4)
EAS Single pulse avalanche energy 1.2 J
Tj Operating junction temperature range
- 55 to 175 °C
Tstg Storage temperature range

Notes:
(1)Current limited by package
(2)Pulse width limited by safe operating area.
(3)I
SD ≤120 A, di/dt ≤300A/μs, VDD =V(BR)DSS, Tj ≤ TJMAX
(4)Starting Tj = 25 °C, ID = 60 A, VDD = 30 V.

Table 3: Thermal data


Symbol Parameter Value Unit
D²PAK TO-220
Rthj-case Thermal resistance junction-case 0.5 °C/W
(1)
Rthj-pcb Thermal resistance junction-pcb 35 °C/W
Rthj-amb Thermal resistance junction-ambient 62.5 °C/W

Notes:
(1)When mounted on a 1-inch² FR-4 board, 2oz Cu.

DocID9969 Rev 7 3/20


Electrical characteristics STB100NF04T4, STP100NF04

2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4: On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage ID = 250 µA, VGS = 0 V 40 V
VDS = 40 V, VGS = 0 V 1 µA
IDSS Zero gate voltage drain current VDS = 40 V, VGS = 0 V
10 µA
TC = 125°C(1)
IGSS Gate body leakage current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 4 V
RDS(on) Static drain-source on- resistance VGS = 10 V, ID= 50 A 4.3 4.6 mΩ

Notes:
(1)Defined by design,not subject to production test

Table 5: Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 5100 pF
VDS = 25 V, f = 1 MHz,
Coss Output capacitance - 1300 pF
VGS = 0 V
Crss Reverse transfer capacitance - 160 pF
Qg Total gate charge VDD = 32 V, ID = 120 A , - 110 150 nC
VGS = 10 V
Qgs Gate-source charge - 35 nC
(see Figure 21: "Test
Qgd Gate-drain charge circuit for gate charge - 70 nC
behavior")
td(on) Turn-on delay time VDD = 20 V, ID = 60 A , - 35 ns
tr Rise time RG = 4.7 Ω ,VGS = 10 V - 220 ns
(see Figure 20: "Test
td(off) Turn-off delay time circuit for resistive load - 80 ns
switching times" and
tf Fall time Figure 25: "Switching - 50 ns
time waveform")

4/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Electrical characteristics
Table 6: Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD Source-drain current - 120 A
ISDM(1) Source-drain current (pulsed) - 480 A
VSD(2) Forward on voltage ISD = 120 A, VGS = 0 V - 1.3 V
tr Reverse recovery time ISD = 120 A, VDD = 20 V, - 75 - ns
di/dt = 100 A/μs V, Tj =
td(off) Reverse recovery charge - 185 - nC
150 °C
(see Figure 22: "Test
tf Reverse recovery current circuit for inductive load - 5 - A
switching and diode
recovery times")

Notes:
(1)
Pulse width limited by safe operating area.
(2)Pulsed: Pulse duration = 300 μs, duty cycle 1.5%

DocID9969 Rev 7 5/20


Electrical characteristics STB100NF04T4, STP100NF04
2.1 Electrical characteristics (curves)
Figure 2: Power dissipation vs. temperature Figure 3: Max Id current vs. temperature

Figure 4: Output characteristics Figure 5: Transfer characteristics

Figure 6: Transconductance Figure 7: Static drain-source on-resistance

6/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Electrical characteristics
Figure 8: Gate charge vs. gate-source voltage Figure 9: Capacitance variations

Figure 10: Normalized gate threshold voltage vs. Figure 11: Normalized on-resistance vs.
temperature temperature

Figure 12: Source-drain diode forward characteristics Figure 13: Normalized BVDSS vs. temperature

DocID9969 Rev 7 7/20


Electrical characteristics STB100NF04T4, STP100NF04
Figure 14: Thermal resistance Rthj-pcb vs. PCB
copper area
Figure 15: Thermal impedance

Figure 16: Max power dissipation vs. PCB copper area Figure 17: Safe operating area

8/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Electrical characteristics
Figure 18: Allowable Iav vs. time in avalanche

The previous curve give the safe operating area for unclamped inductive loads, single
pulse or repetitive, under the following conditions:
PD(AVE) = 0.5*(1.3*BVDSS*IAV)
EAS(AR)= PD(AVE)*TAV
Where:
IAV is the allowable current in avalanche
PD(AVE) is the average power dissipation in avalnche(single pulse)
tAV is the time in avalanche
To de rate above 25°C, at fixed IAV, the following equation must be applied:
IAV= 2*(Tjmax-TCASE)/(1.3*BVDSS*Zth)
Where:
Zth= K*Rth is the value coming from normalized thermal response at fixed pulse width
equal to TAV

DocID9969 Rev 7 9/20


Spice thermal model STB100NF04T4, STP100NF04

3 Spice thermal model


Figure 19: Spice model schematic

Table 7: Spice parameter


Parameter Node Value
CTHERM1 5-4 0.011
CTHERM1 4-3 0.0012
CTHERM3 3-2 0.05
CTHERM4 2-1 0.1
RTHERM1 5-4 0.09
RTHERM2 4-3 0.02
RTHERM3 3-2 0.11
RTHERM4 2-1 0.17

10/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Test circuits

4 Test circuits
Figure 20: Test circuit for resistive load Figure 21: Test circuit for gate charge
switching times behavior

Figure 22: Test circuit for inductive load Figure 23: Unclamped inductive load test
switching and diode recovery times circuit

Figure 25: Switching time waveform


Figure 24: Unclamped inductive waveform

DocID9969 Rev 7 11/20


Package information STB100NF04T4, STP100NF04

5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.1 D²PAK packing information


Figure 26: D²PAK (TO-263) type A package outline

0079457_A_rev22

12/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Package information
Table 8: D²PAK (TO-263) type A package mechanical data
mm
Dim.
Min. Typ. Max.
A 4.40 4.60
A1 0.03 0.23
b 0.70 0.93
b2 1.14 1.70
c 0.45 0.60
c2 1.23 1.36
D 8.95 9.35
D1 7.50 7.75 8.00
D2 1.10 1.30 1.50
E 10 10.40
E1 8.50 8.70 8.90
E2 6.85 7.05 7.25
e 2.54
e1 4.88 5.28
H 15 15.85
J1 2.49 2.69
L 2.29 2.79
L1 1.27 1.40
L2 1.30 1.75
R 0.4
V2 0° 8°

DocID9969 Rev 7 13/20


Package information STB100NF04T4, STP100NF04
Figure 27: D²PAK (TO-263) recommended footprint (dimensions are in mm)

14/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Package information
5.2 D²PAK packing information
Figure 28: Tape outline

DocID9969 Rev 7 15/20


Package information STB100NF04T4, STP100NF04
Figure 29: Reel outline

Table 9: D²PAK tape and reel mechanical data


Tape Reel
mm mm
Dim. Dim.
Min. Max. Min. Max.
A0 10.5 10.7 A 330
B0 15.7 15.9 B 1.5
D 1.5 1.6 C 12.8 13.2
D1 1.59 1.61 D 20.2
E 1.65 1.85 G 24.4 26.4
F 11.4 11.6 N 100
K0 4.8 5.0 T 30.4
P0 3.9 4.1
P1 11.9 12.1 Base quantity 1000
P2 1.9 2.1 Bulk quantity 1000
R 50
T 0.25 0.35
W 23.7 24.3

16/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Package information
5.3 TO-220 package information
Figure 30: TO-220 type A package outline

DocID9969 Rev 7 17/20


Package information STB100NF04T4, STP100NF04
Table 11: TO-220 type A mechanical data
mm
Dim.
Min. Typ. Max.
A 4.40 4.60
b 0.61 0.88
b1 1.14 1.55
c 0.48 0.70
D 15.25 15.75
D1 1.27
E 10.00 10.40
e 2.40 2.70
e1 4.95 5.15
F 1.23 1.32
H1 6.20 6.60
J1 2.40 2.72
L 13.00 14.00
L1 3.50 3.93
L20 16.40
L30 28.90
øP 3.75 3.85
Q 2.65 2.95

18/20 DocID9969 Rev 7


STB100NF04T4, STP100NF04 Revision history

6 Revision history
Table 12: Document revision history
Date Revision Changes
23-Mar-2005 2 New template
01-Mar-2006 3 Removed I²PAK and inserted D²PAK.
04-Sep-2006 4 New template,no content change
20-Feb-2007 5 Typo mistake on page 1
Minor text changes – Modified: Figure 17 – Updated: Section 4:
16-Mar-2013 6
Package mechanical data and Section 5: Packaging mechanical data
Updated title in cover page.
21-Nov-2016 7 Updated Section 2: "Electrical characteristics".
Minor text changes.

DocID9969 Rev 7 19/20


STB100NF04T4, STP100NF04

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2016 STMicroelectronics – All rights reserved

20/20 DocID9969 Rev 7

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