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Datasheet Search Site PDF
Datasheet Search Site PDF
PIC16C58
PIC16CR56
PIC16C56
PIC16CR54
PIC16C54
PIC16CR58
2 27 OSC1/CLKIN
T0CKI 3 16 OSC1/CLKIN N/C 3 26 OSC2/CLKOUT
MCLR/VPP 4 15 OSC2/CLKOUT
VSS 4 25 RC7
VSS 5 14 VDD
N/C 5 24 RC6
6
PIC16CR57
PIC16C57
RB7
PIC16C55
RB0 13
7 12 RB6 RA0 6 23 RC5
RB1
RB2 8 11 RB5 RA1 7 22 RC4
RB3 9 10 RB4 RA2 8 21 RC3
RA3 9 20 RC2
RB0 10 19 RC1
RB1 11 18 RC0
RB2 12 17 RB7
RB3 13 16 RB6
RB4 14 15 RB5
SSOP SSOP
PIC16CR57
PIC16C55
PIC16C57
MCLR/VPP 4 17 OSC2/CLKOUT RA0 5 24 RC6
VSS 5 16 VDD RA1 6 23 RC5
VSS 6 15 VDD RA2 7 22 RC4
RB0 7 14 RB7 RA3 8 21 RC3
RB0 9 20 RC2
RB1 8 13 RB6 RB1 10 19 RC1
RB2 9 12 RB5 RB2 11 18 RC0
RB3 10 11 RB4 RB3 12 17 RB7
RB4 13 16 RB6
VSS 14 15 RB5
Device Differences
Oscillator Process
Voltage ROM MCLR
Device Selection Oscillator Technology
Range Equivalent Filter
(Program) (Microns)
PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No
PIC16C54A 2.0-6.25 User See Note 1 0.9 — No
PIC16C54C 2.5-5.5 User See Note 1 0.7 PIC16CR54C Yes
PIC16C55 2.5-6.25 Factory See Note 1 1.7 — No
PIC16C55A 2.5-5.5 User See Note 1 0.7 — Yes
PIC16C56 2.5-6.25 Factory See Note 1 1.7 — No
PIC16C56A 2.5-5.5 User See Note 1 0.7 PIC16CR56A Yes
PIC16C57 2.5-6.25 Factory See Note 1 1.2 — No
PIC16C57C 2.5-5.5 User See Note 1 0.7 PIC16CR57C Yes
PIC16C58B 2.5-5.5 User See Note 1 0.7 PIC16CR58B Yes
PIC16CR54A 2.5-6.25 Factory See Note 1 1.2 N/A Yes
PIC16CR54C 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 N/A Yes
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please
refer to Section 2.0.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
STATUS 73 Bytes
TMR0 FSR
8
DATA BUS
W ALU
8
FROM W FROM W FROM W
4 8 8
4 8 8
“TRIS 5” “TRIS 6” “TRIS 7”
TRISA PORTA TRISB PORTB TRISC PORTC
4 8 8
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
74AS04 CLKIN
Open OSC2
10K
XTAL
10K
20 pF 20 pF
Power-Up
Detect
VDD POR (Power-On Reset)
RESET S Q
WDT
On-Chip 8-bit Asynch
RC OSC Ripple Counter
(Device Reset R Q
Timer)
CHIP RESET
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will RESET properly if, and only if, V1 VDD min
Q1
10K MCLR
40K
PIC16C5X
User Memory
Memory (Page 0) 100h
The PIC16C54, PIC16CR54 and PIC16C55 have a 9-
Space
bit Program Counter (PC) capable of addressing a 512 1FFh
200h
x 12 program memory space (Figure 6-1). The
PIC16C56 and PIC16CR56 have a 10-bit Program On-chip Program 2FFh
Counter (PC) capable of addressing a 1K x 12 program Memory (Page 1) 300h
9 2FFh
CALL, RETLW Memory (Page 1) 300h
Space
On-chip 5FFh
Space
The General Purpose Registers are used for data and 05h PORTA
control information under command of the instructions. 06h PORTB
For the PIC16C54, PIC16CR54, PIC16C56 and 07h PORTC(2)
PIC16CR56, the register file is composed of 7 Special
Function Registers and 25 General Purpose Registers 08h
(Figure 6-4).
General
For the PIC16C55, the register file is composed of 8 Purpose
Registers
Special Function Registers and 24 General Purpose
Registers.
For the PIC16C57 and PIC16CR57, the register file is
composed of 8 Special Function Registers, 24 General 1Fh
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a Note 1: Not a physical register. See
banking scheme (Figure 6-5). Section 6.7.
For the PIC16C58 and PIC16CR58, the register file is 2: PIC16C55 only, in all other devices this
composed of 7 Special Function Registers, 25 General is implemented as a a general purpose
Purpose Registers and up to 48 additional General register.
Purpose Registers that may be addressed using a
banking scheme (Figure 6-6).
01h TMR0
02h PCL
03h STATUS
04h FSR
Addresses map back to
05h PORTA addresses in Bank 0.
06h PORTB
07h PORTC
08h General
Purpose
0Fh Registers 2Fh 4Fh 6Fh
10h 30h 50h 70h
General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
01h TMR0
02h PCL
03h STATUS
04h FSR
Addresses map back to
05h PORTA addresses in Bank 0.
06h PORTB
07h
General
Purpose
Registers
0Fh 2Fh 4Fh 6Fh
10h 30h 50h 70h
General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
8 7 0
PC PCL
Instruction Word
Reset to ‘0’
Reset to '0' Instruction Word 2 PA<1:0>
7 0
STATUS
6.6 Stack
PIC16C5X devices have a 10-bit or 11-bit wide, two-
level hardware push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program coun-
ter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W Register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the pro-
gram memory.
For the RETLW instruction, the PC is loaded with the
Top of Stack (TOS) contents. All of the devices covered
in this data sheet have a two-level stack. The stack has
the same bit width as the device PC, therefore, paging
is not an issue when returning from a subroutine.
Data 0Fh
Memory(1) 10h
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC + 1 PC + 2 PC + 3
Instruction
fetched MOVWF PORTB MOVF PORTB,W NOP NOP
This example shows a write
RB<7:0> to PORTB followed by a read
from PORTB.
Port pin Port pin
written here sampled here
Data Bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0 reg
T0CKI Clocks
Programmable 0 PSout
pin Prescaler(2)
T0SE(1) (2 cycle delay) Sync
3
PS2, PS1, PS0(1) PSA(1)
T0CS(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register
(Section 6.4).
2: The prescaler is shared with the Watchdog Timer (Figure 8-6).
RIN
VSS VSS
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or Small pulse
Prescaler Output (1) misses sampling
(3)
External Clock/Prescaler (2)
Output After Sampling
Timer0 T0 T0 + 1 T0 + 2
T0SE
T0CS
PSA
0
8-bit Prescaler
M
U
1 X
Watchdog 8
Timer
8 - to - 1MUX PS<2:0>
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to
access the configuration word.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to
access the configuration word.
2: PIC16LV54A supports XT, RC and LP oscillator only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
An 8-bit counter is available as a prescaler for the The CLRWDT instruction clears the WDT and the pres-
Timer0 module (Section 8.2), or as a postscaler for the caler, if assigned to the WDT, and prevents it from tim-
Watchdog Timer (WDT), respectively. For simplicity, ing out and generating a device RESET.
this counter is being referred to as “prescaler” through- The SLEEP instruction RESETS the WDT and the pres-
out this data sheet. Note that the prescaler may be caler, if assigned to the WDT. This gives the maximum
used by either the Timer0 module or the WDT, but not SLEEP time before a WDT Wake-up Reset.
0
M
Watchdog 1 Prescaler
U
Timer
X
8 - to - 1 MUX PS2:PS0
0 1
MUX PSA
Description: The contents of the W register are Encoding: 0100 bbbf ffff
AND’ed with the eight-bit literal 'k'. Description: Bit 'b' in register 'f' is cleared.
The result is placed in the W regis- Words: 1
ter.
Cycles: 1
Words: 1
Example: BCF FLAG_REG, 7
Cycles: 1
Before Instruction
Example: ANDLW H'5F' FLAG_REG = 0xC7
Before Instruction After Instruction
W = 0xA3 FLAG_REG = 0x47
After Instruction
W = 0x03
Description: The contents of the W register are Encoding: 0010 00df ffff
OR’ed with the eight bit literal 'k'. Description: The contents of register 'f' is
The result is placed in the W regis- moved to destination 'd'. If 'd' is 0,
ter. destination is the W register. If 'd'
Words: 1 is 1, the destination is file
register 'f'. 'd' is 1 is useful to test a
Cycles: 1 file register since status flag Z is
Example: IORLW 0x35 affected.
Before Instruction Words: 1
W = 0x9A Cycles: 1
After Instruction
W = 0xBF Example: MOVF FSR, 0
Z = 0 After Instruction
W = value in FSR register
RLF Rotate Left f through Carry RRF Rotate Right f through Carry
Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d
Operands: 0 f 31 Operands: 0 f 31
d [0,1] d [0,1]
Operation: See description below Operation: See description below
Status Affected: C Status Affected: C
Encoding: 0011 01df ffff Encoding: 0011 00df ffff
Description: The contents of register 'f' are Description: The contents of register 'f' are
rotated one bit to the left through rotated one bit to the right through
the Carry Flag (STATUS<0>). If 'd' the Carry Flag (STATUS<0>). If 'd'
is 0 the result is placed in the W is 0 the result is placed in the W
register. If 'd' is 1 the result is register. If 'd' is 1 the result is
stored back in placed back in
register 'f'. register 'f'.
C register 'f' C register 'f'
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example: RLF REG1,0 Example: RRF REG1,0
Before Instruction Before Instruction
REG1 = 1110 0110 REG1 = 1110 0110
C = 0 C = 0
After Instruction After Instruction
REG1 = 1110 0110 REG1 = 1110 0110
W = 1100 1100 W = 0111 0011
C = 1 C = 0
Cycles: 1 Words: 1
24CXX/
25CXX/
HCSXXX
PIC14000
MCP2510
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX
PIC16F62X
PIC16F8XX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC18FXXX
PIC12CXXX
PIC16CXXX
MPLAB® Integrated
TABLE 11-1:
Development Environment
Software Tools
MPLINKTM Object Linker
PRO MATE® II
Universal Device Programmer **
Preliminary
PICDEMTM 2 Demonstration † †
Board
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEMTM 3 Demonstration
Board
PICDEMTM 17 Demonstration
Board
DS30453E-page 65
PIC16C5X
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
D001 VDD Supply Voltage
PIC16C5X-RC 3.0 — 6.25 V
PIC16C5X-XT 3.0 — 6.25 V
PIC16C5X-10 4.5 — 5.5 V
PIC16C5X-HS 4.5 — 5.5 V
PIC16C5X-LP 2.5 — 6.25 V
D002 VDR RAM Data Retention Voltage(1) 1.5* — V Device in SLEEP Mode
D003 VPOR VDD Start Voltage to ensure VSS — V See Section 5.1 for details on
Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 5.1 for details on
Power-on Reset Power-on Reset
D010 IDD Supply Current(2)
PIC16C5X-RC(3) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
PIC16C5X-XT — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
PIC16C5X-10 — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
PIC16C5X-HS — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
PIC16C5X-HS — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
PIC16C5X-LP — 15 32 A FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D020 IPD Power-down Current(2) — 4.0 12 A VDD = 3.0V, WDT enabled
— 0.6 9 A VDD = 3.0V, WDT disabled
* These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
D001 VDD Supply Voltage
PIC16C5X-RCI 3.0 — 6.25 V
PIC16C5X-XTI 3.0 — 6.25 V
PIC16C5X-10I 4.5 — 5.5 V
PIC16C5X-HSI 4.5 — 5.5 V
PIC16C5X-LPI 2.5 — 6.25 V
D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode
D003 VPOR VDD Start Voltage to ensure — VSS — V See Section 5.1 for details on
Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 5.1 for details on
Power-on Reset Power-on Reset
D010 IDD Supply Current(2)
PIC16C5X-RCI(3) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
PIC16C5X-XTI — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
PIC16C5X-10I — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
PIC16C5X-HSI — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
PIC16C5X-HSI — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
PIC16C5X-LPI — 15 40 A FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D020 IPD Power-down Current(2) — 4.0 14 A VDD = 3.0V, WDT enabled
— 0.6 12 A VDD = 3.0V, WDT disabled
* These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
D001 VDD Supply Voltage
PIC16C5X-RCE 3.25 — 6.0 V
PIC16C5X-XTE 3.25 — 6.0 V
PIC16C5X-10E 4.5 — 5.5 V
PIC16C5X-HSE 4.5 — 5.5 V
PIC16C5X-LPE 2.5 — 6.0 V
D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode
D003 VPOR VDD Start Voltage to ensure — VSS — V See Section 5.1 for details on
Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 5.1 for details on
Power-on Reset Power-on Reset
D010 IDD Supply Current(2)
PIC16C5X-RCE(3) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
PIC16C5X-XTE — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
PIC16C5X-10E — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
PIC16C5X-HSE — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
PIC16C5X-HSE — 9.0 20 mA FOSC = 16 MHz, VDD = 5.5V
PIC16C5X-LPE — 19 55 A FOSC = 32 kHz, VDD = 3.25V,
WDT disabled
D020 IPD Power-down Current(2) — 5.0 22 A VDD = 3.25V, WDT enabled
— 0.8 18 A VDD = 3.25V, WDT disabled
* These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
14 19 16
I/O Pin
(input)
17 15
20, 21
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34 34
I/O pin
(Note 1)
TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C TA +70°C for commercial
AC Characteristics
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
T0CKI
40 41
42
Note: Please refer to Figure 12-1 for load conditions.
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
VDD Supply Voltage
D001 PIC16LCR54A 2.0 — 6.25 V
D001 PIC16CR54A 2.5 — 6.25 V RC and XT modes
D001A 4.5 — 5.5 V HS mode
D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode
Voltage(1)
D003 VPOR VDD Start Voltage to ensure — VSS — V See Section 5.1 for details on
Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 5.1 for details on
Power-on Reset Power-on Reset
IDD Supply Current(2)
D005 PICLCR54A — 10 20 A Fosc = 32 kHz, VDD = 2.0V
— — 70 A Fosc = 32 kHz, VDD = 6.0V
D005A RC(3) and XT modes:
PIC16CR54A — 2.0 3.6 mA FOSC = 4.0 MHz, VDD = 6.0V
— 0.8 1.8 mA FOSC = 4.0 MHz, VDD = 3.0V
— 90 350 A FOSC = 200 kHz, VDD = 2.5V
HS mode:
— 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
— 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
IPD Power-down Current(2)
D006 PIC16LCR54A-Commercial — 1.0 6.0 A VDD = 2.5V, WDT disabled
— 2.0 8.0* A VDD = 4.0V, WDT disabled
— 3.0 15 A VDD = 6.0V, WDT disabled
— 5.0 25 A VDD = 6.0V, WDT enabled
D006A PIC16CR54A-Commercial — 1.0 6.0 A VDD = 2.5V, WDT disabled
— 2.0 8.0* A VDD = 4.0V, WDT disabled
— 3.0 15 A VDD = 6.0V, WDT disabled
— 5.0 25 A VDD = 6.0V, WDT enabled
D007 PIC16LCR54A-Industrial — 1.0 8.0 A VDD = 2.5V, WDT disabled
— 2.0 10* A VDD = 4.0V, WDT disabled
— 3.0 20* A VDD = 4.0V, WDT enabled
— 3.0 18 A VDD = 6.0V, WDT disabled
— 5.0 45 A VDD = 6.0V, WDT enabled
D007A PIC16CR54A-Industrial — 1.0 8.0 A VDD = 2.5V, WDT disabled
— 2.0 10* A VDD = 4.0V, WDT disabled
— 3.0 20* A VDD = 4.0V, WDT enabled
— 3.0 18 A VDD = 6.0V, WDT disabled
— 5.0 45 A VDD = 6.0V, WDT enabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic Min Typ† Max Units Conditions
No.
D001 VDD Supply Voltage
RC, XT and LP modes 3.25 — 6.0 V
HS mode 4.5 — 5.5 V
D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode
D003 VPOR VDD Start Voltage to ensure — VSS — V See Section 5.1 for details on
Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure Power- 0.05* — — V/ms See Section 5.1 for details on
on Reset Power-on Reset
D010 IDD Supply Current(2)
RC(3) and XT modes — 1.8 3.3 mA FOSC = 4.0 MHz, VDD = 5.5V
HS mode — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
HS mode — 9.0 20 mA FOSC = 16 MHz, VDD = 5.5V
D020 IPD Power-down Current(2) — 5.0 22 A VDD = 3.25V, WDT enabled
— 0.8 18 A VDD = 3.25V, WDT disabled
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode.The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in k.
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
Note: Please refer to Figure 13.1 for load conditions.
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0C TA +70°C for commercial
AC Characteristics
–40C TA +85C for industrial
–40C TA +125C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
T0CKI
40 41
42
Note: Please refer to Figure 13.1 for load conditions.
1.10
REXT 10k
1.08
CEXT = 100 pF
1.06
1.04
1.02
1.00
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0 10 20 25 30 40 50 60 70
T(C)
5.5 1.8
R = 3.3K R = 3.3K
5.0 1.6
4.5 1.4
4.0 R = 5K
1.2 R = 5K
Fosc (MHz)
3.5
1.0
Fosc (MHz)
3.0
0.8
R = 10K
R = 10K
2.5
0.6
0.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
700 2.0
R = 3.3K
T = 25C
600
1.5
500 R = 5K
IPD (A)
Fosc (kHz)
1.0
400
R = 10K 0.5
300
200
0.0
Measured on DIP Packages, T = 25C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
R = 100K
0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
100 60
50
+125°C
+85°C
10 40
+70°C –55C
0°C
+85C
Ipd (A)
30
–40°C
+125C
IPD (A)
–40C
–55°C +70C
1 20
0C
10
0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts) VDD (Volts)
IPD, with WDT enabled, has two components:
The leakage current, which increases with higher temper-
FIGURE 14-7: TYPICAL IPD vs. VDD, ature, and the operating current of the WDT logic, which
WATCHDOG ENABLED increases with lower temperature. At –40C, the latter
dominates explaining the apparently anomalous behav-
Typical: statistical mean @ 25°C
ior.
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
20
18
16
14
T = 25C
12
10
IPD (A)
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
2.00
1.80 85 C )
–40 C to +
M ax (
1.60
VTH (Volts)
1.40 2 5 C )
Typ (+
1.20
8 5 C )
1.00
40 C to +
Min (–
0.80
0.60
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 14-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (RC MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.5
4.0 C )
to +85
40C
3.5 m ax (–
VIH
C
+ 25
3.0 typ 5C
)
VIH
to +8
VIH, VIL (Volts)
C
(–40
2.5 min
VIH
2.0
to +85C)
VIL max (–40C
1.5
0.5 C)
VIL min (–40C to +85
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: These input pins have Schmitt Trigger input buffers.
3.4
3.2
3.0
2.8 C)
85
o+
2.6 C t
(–40
Ma x C)
2.4 + 25
(
VTH (Volts)
Typ
2.2
)
5 C
2.0
Ct o +8
(– 40
1.8 M in
1.6
1.4
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
10
1.0
IDD (mA)
0.1 7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10K 100K 1M 10M 100M
External Clock Frequency (Hz)
10
1.0
IDD (mA)
7.0
6.5
0.1 6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10K 100K 1M 10M 100M
External Clock Frequency (Hz)
FIGURE 14-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55C TO +125C)
10
1.0
IDD (mA)
7.0
6.5
6.0
5.5
5.0
0.1 4.5
4.0
3.5
3.0
2.5
0.01
10K 100K 1M 10M 100M
External Clock Frequency (Hz)
45
8000
Max –40C
40
7000
35
WDT period (ms)
6000
30
Max +85C
5000
gm (A/V)
Typ +25C
25
45 2500
40
Max –40C
Max –40C
2000
35
30
1500
25
gm (A/V)
gm (A/V)
Typ +25C
Typ +25C
20 1000
15
Min +85C
500
10
Min +85C
5
0
2.0 3.0 4.0 5.0 6.0 7.0
0
2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts)
VDD (Volts)
0 0
Min +85C
–5
Min +85C –10
–10
IOH (mA)
IOH (mA)
–20
Typ +25C
Typ +25C
–15
Max –40C
–30
Max –40C
–20
–40
–25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
VOH (Volts)
45 90
35 70
30 60
Typ +25C
25 50
IOL (mA)
IOL (mA)
Typ +25C
20 40
Min +85C
15 30
Min +85C
10 20
5 10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts) VOL (Volts)
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
VDD Supply Voltage
D001 PIC16LC54A 3.0 — 6.25 V XT and RC modes
2.5 — 6.25 V LP mode
D001A PIC16C54A 3.0 — 6.25 V RC, XT and LP modes
4.5 — 5.5 V HS mode
D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode
Voltage(1)
D003 VPOR VDD Start Voltage to — Vss — V See Section 5.1 for details on
ensure Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 5.1 for details on
Power-on Reset Power-on Reset
IDD Supply Current(2)
D005 PIC16LC5X — 0.5 2.5 mA FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
— 11 27 A FOSC = 32 kHz, VDD = 2.5V,
WDT disabled, LP mode, Commercial
— 11 35 A FOSC = 32 kHz, VDD = 2.5V,
WDT disabled, LP mode, Industrial
D005A PIC16C5X — 1.8 2.4 mA FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
— 2.4 8.0 mA FOSC = 10 MHz, VDD = 5.5V, HS mode
— 4.5 16 mA FOSC = 20 MHz, VDD = 5.5V, HS mode
— 14 29 A FOSC = 32 kHz, VDD = 3.0V,
WDT disabled, LP mode, Commercial
— 17 37 A FOSC = 32 kHz, VDD = 3.0V,
WDT disabled, LP mode, Industrial
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
IPD Power-down Current(2)
D006 PIC16LC5X — 2.5 12 A VDD = 2.5V, WDT enabled, Commercial
— 0.25 4.0 A VDD = 2.5V, WDT disabled, Commercial
— 2.5 14 A VDD = 2.5V, WDT enabled, Industrial
— 0.25 5.0 A VDD = 2.5V, WDT disabled, Industrial
D006A PIC16C5X — 4.0 12 A VDD = 3.0V, WDT enabled, Commercial
— 0.25 4.0 A VDD = 3.0V, WDT disabled, Commercial
— 5.0 14 A VDD = 3.0V, WDT enabled, Industrial
— 0.3 5.0 A VDD = 3.0V, WDT disabled, Industrial
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
† Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid-
ance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
4: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection on wake-up from
SLEEP mode or during initial power-up.
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
OSC1
10 11
CLKOUT
13 18 12
14 19 16
I/O Pin
(input)
17 15
20, 21
Note: Please refer to Figure 15-1 for load conditions.
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
TABLE 15-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0C TA +70C for commercial
AC Characteristics –40C TA +85C for industrial
–20C TA +85C for industrial - PIC16LV54A-02I
–40C TA +125C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
T0CKI
40 41
42
Note: Please refer to Figure 15-1 for load conditions.
1.10
REXT 10 kW
1.08
CEXT = 100 pF
1.06
1.04
1.02
1.00
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0 10 20 25 30 40 50 60 70
T(C)
R=5K
4
FOSC (MHz)
3
R=10K
R=100K
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
6 R=3.3K
5
R=5K
4
FOSC (MHz)
R=10K
R=100K
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
700
R=3.3K
600
500
R=5K
400
FOSC (kHz)
300
R=10K
200
100
R=100K
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
2.5
2.0
1.5
IPD (A)
1.0
0.5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
25.00
20.00
15.00
10.00
5.00
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD (Volts)
+ 85 C
1.8 )
–4 0C to
M ax (
1.6
VTH (Volts)
1.4 2 5 C )
Typ (+
1.2
+ 8 5 C
)
1.0 0C to
4
Min (–
0.8
0.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 16-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP
MODES) vs. VDD
3.4
3.2
3.0
2.8 )
5C
o +8
2.6 0 C t
(–4
Ma x C)
2.4 + 25
(
VTH (Volts)
Typ
2.2
C)
2.0 to + 85
(– 4 0 C
1.8 M in
1.6
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
4.5
4.0 C)
to +8 5
40C
3.5 m ax (–
VIH
C
+25
3.0 typ 5C
)
VIH
to +8
VIH, VIL (Volts)
C
(–40
2.5 min
VIH
2.0
1.5 C to +85C)
VIL max (–40
0.5 5C)
VIL min (–40C to +8
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: These input pins have Schmitt Trigger input buffers.
10000
1000
IDD (A)
6.0V
5.5V
5.0V
100 4.5V
4.0V
3.5V
3.0V
2.5V
10
0.1 1 10
Freq (MHz)
1000
IDD (A)
6.0V
5.5V
5.0V
4.5V
100 4.0V
3.5V
3.0V
2.5V
10
0.1 1 10
Freq (MHz)
1000
IDD (A)
6.0V
100 5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01 0.1 1 10
Freq (MHz)
1000
IDD (A)
6.0V
5.5V
5.0V
100 4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01 0.1 1 10
Freq (MHz)
1000
IDD (A)
6.0V
100 5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01 0.1 1
Freq (MHz)
1000
IDD (A)
6.0V
5.5V
100 5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01 0.1 1
Freq (MHz)
45
8000
Max –40C
40
7000
35
WDT period (ms)
6000
30
Max +85C 5000
gm (A/W)
Typ +25C
25
4000
Max +70C
20
Typ +25C 3000
15 Min +85C
MIn 0C 2000
10
MIn –40C 100
5
2.0 3.0 4.0 5.0 6.0 7.0 0
VDD (Volts) 2.0 3.0 4.0 5.0 6.0 7.0
VDD (Volts)
Note 1: Prescaler set to 1:1.
45 2500
40
Max –40C
Max –40C
2000
35
30
1500
25
Typ +25C
gm (A/V)
gm (A/V)
Typ +25C
20 1000
15
Min +85C
500
10
Min +85C
5
0
2.0 3.0 4.0 5.0 6.0 7.0
0 VDD (Volts)
2.0 3.0 4.0 5.0 6.0 7.0
VDD (Volts)
0 0
Min +85C
–5
Min +85C –10
–10
IOH (mA)
IOH (mA)
–20
Typ +25C
Typ +25C
–15
Max –40C
–30
Max –40C
–20
–40
–25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
VOH (Volts)
45 90
Max –40C
40 80 Max –40C
35 70
30 60
Typ +25C
25 50
IOL (mA)
IOL (mA)
Typ +25C
20 40
Min +85C
15 30
Min +85C
10 20
5 10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts) VOL (Volts)
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.7
2.5
2.0
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
VDD Supply Voltage
D001 PIC16LC5X 2.5 — 5.5 V –40C TA + 85C, 16LCR5X
2.7 — 5.5 V –40C TA 0C, 16LC5X
2.5 — 5.5 V 0C TA + 85C 16LC5X
PIC16C5X RC, XT, LP and HS mode
D001A 3.0 — 5.5 V from 0 - 10 MHz
4.5 — 5.5 V from 10 - 20 MHz
D002 VDR RAM Data Retention Volt- — 1.5* — V Device in SLEEP mode
age(1)
D003 VPOR VDD Start Voltage to ensure — VSS — V See Section 5.1 for details on
Power-on Reset Power-on Reset
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 5.1 for details on
Power-on Reset Power-on Reset
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con-
sumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
IDD Supply Current(2,3)
D010 PIC16LC5X — 0.5 2.4 mA FOSC = 4.0 MHz, VDD = 5.5V, XT and
— 11 27 A RC modes
FOSC = 32 kHz, VDD = 2.5V, LP mode,
— 14 35 A Commercial
FOSC = 32 kHz, VDD = 2.5V, LP mode,
Industrial
D010A PIC16C5X — 1.8 2.4 mA FOSC = 4 MHz, VDD = 5.5V, XT and RC
— 2.6 3.6* mA modes
— 4.5 16 mA FOSC = 10 MHz, VDD = 3.0V, HS mode
— 14 32 A FOSC = 20 MHz, VDD = 5.5V, HS mode
FOSC = 32 kHz, VDD = 3.0V, LP mode,
— 17 40 A Commercial
FOSC = 32 kHz, VDD = 3.0V, LP mode,
Industrial
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con-
sumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Param
Symbol Characteristic/Device Min Typ† Max Units Conditions
No.
IPD Power-down Current(2)
D020 PIC16LC5X — 0.25 2 A VDD = 2.5V, WDT disabled, Commercial
— 0.25 3 A VDD = 2.5V, WDT disabled, Industrial
— 1 5 A VDD = 2.5V, WDT enabled, Commercial
— 1.25 8 A VDD = 2.5V, WDT enabled, Industrial
D020A PIC16C5X — 0.25 4.0 A VDD = 3.0V, WDT disabled, Commercial
— 0.25 5.0 A VDD = 3.0V, WDT disabled, Industrial
— 1.8 7.0* A VDD = 5.5V, WDT disabled, Commercial
— 2.0 8.0* A VDD = 5.5V, WDT disabled, Industrial
— 4 12* A VDD = 3.0V, WDT enabled, Commercial
— 4 14* A VDD = 3.0V, WDT enabled, Industrial
— 9.8 27* A VDD = 5.5V, WDT enabled, Commercial
— 12 30* A VDD = 5.5V, WDT enabled, Industrial
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con-
sumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
VSS
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
OSC1
10 11
CLKOUT
13 18 12
14 19 16
I/O Pin
(input)
17 15
20, 21
Note: Refer to Figure 17-5 for load conditions.
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
TABLE 17-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C TA +70°C for commercial
AC Characteristics
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
T0CKI
40 41
42
Note: Please refer to Figure 17-5 for load conditions.
1.10
REXT 10 kW
1.08
CEXT = 100 pF
1.06
1.04
1.02
1.00
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0 10 20 25 30 40 50 60 70
T(C)
R=3.3K
R=5K
4
R=10K
2
R=100K
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C
R=3.3K
1.6
1.4
R=5K
FOSC (MHz)
1.0
R=10K
0.6
0.2
R=100K
0
6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
700
R=3.3K
600
500
R=5K
FOSC (kHz)
400
300
R=10K
200
100
R=100K
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
20
15
IPD (uA)
10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
20
15
IPD (uA)
10
5.0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 18-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)
30
25
20
IPD (uA)
15
10
5.0 (-40C)
0 (+85C)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
2.0
1.8
1.6
VTH (Volts)
1.4 2 5 C )
Typ (+
1.2
1.0
0.8
0.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 18-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
4.0 C)
to +8 5
40C
3.5 m ax (–
VIH
C
+25
3.0 typ 5C
)
VIH
to +8
VIH, VIL (Volts)
40 C
2.5 m in (–
VIH
2.0
1.5 C to +85C)
VIL max (–40
0.5 C)
VIL min (–40C to +85
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: These input pins have Schmitt Trigger input buffers.
3.4
3.2
3.0
2.8
2.6
2.4 C)
( + 25
VTH (Volts)
Typ
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 18-11: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C)
TYPICAL IDD vs FREQ(RC MODE @ 20pF/25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
IDD(A)
5.5V
4.5V
100
3.5V
2.5V
10
0.1 1 10
FREQ(MHz)
10000
1000
IDD(A)
5.5V
100
4.5V
3.5V
2.5V
10
0.1 1 10
FREQ(MHz)
FIGURE 18-13: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C)
TYPICAL IDD vs FREQ (RC MODE @ 300 pF/25C) Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
IDD(A)
100 5.5V
4.5V
3.5V
2.5V
10
0.01 0.1 1
FREQ(MHz)
50 0
45
–5
40 Min +85C
35
–10
WDT period (ms)
IOH (mA)
30
Typ +25C
Typ +125C
25 –15
Typ +85C
Max –40C
20
Typ +25C –20
15
Typ –40C
10
–25
0 0.5 1.0 1.5 2.0 2.5 3.0
5.0 VOH (Volts)
2.0 3.0 4.0 5.0 6.0 7.0
VDD (Volts)
0 45
40 Max –40C
–10 35
30
Typ +125C
IOH (mA)
–20 25
IOL (mA)
Typ +85C
Typ +25C
20
Typ +25C
Typ –40C
–30 15
Min +85C
10
–40 5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts) 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
90
80 Max –40C
70
60
Typ +25C
50
IOL (mA)
40
Min +85C
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0 4 10 20 25 40
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
3: Operation between 20 to 40 MHz requires the following:
• VDD between 4.5V. and 5.5V
• OSC1 externally driven
• OSC2 not connected
• HS mode
• Commercial temperatures
Devices qualified for 40 MHz operation have -40 designation (ex: PIC16C54C-40/P).
4: For operation between DC and 20 MHz, see Section 17.1.
OSC1
1 3 3
4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
14 19 16
I/O Pin
(input)
17 15
20, 21
.
Note: Refer to Figure 19-2 for load conditions.
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin(1)
TABLE 19-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified)
AC Characteristics Operating Temperature 0°C TA +70°C (commercial)
Operating Voltage VDD range is described in Section 19.1.
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
T0CKI
40 41
42
Note: Refer to Figure 19-2 for load conditions.
25
20
15
IPD (uA)
10
5.0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
25
20
15
IPD (uA)
10
5.0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 20-3: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)
35
30
25
20
IPD (uA)
15
10
5.0 (-40C)
0 (+85C)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
2.0
1.8
1.6
VTH (Volts)
1.4 2 5 C )
Typ (+
1.2
1.0
0.8
0.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 20-5: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT
(HS MODE) vs. VDD
3.4
3.2
3.0
2.8
2.6
2.4 C)
( + 25
VTH (Volts)
Typ
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
12
11
10
9.0
IDD (mA)
8.0
7.0
6.0
5.0
4.0
3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
45
–10
40
Typ +125C
35
IOH (mA)
WDT period (ms)
–20
30 Typ +85C
VOH (Volts)
5.0
2.0 3.0 4.0 5.0 6.0 7.0
VDD (Volts)
Note 1: Prescaler set to 1:1.
90
80 Max –40C
70
60
Typ +25C
50
IOL (mA)
40
Min +85C
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
XXXXXXXXXXXX PIC16C54C
XXXXXXXXXXXX -04/S0218
XXXXXXXXXXXX
YYWWNNN 0018CDK
XXXXXXXX PIC16C54C
XXXXXXXX /JW
YYWWNNN 0001CBA
XXXXXXXXXXX PIC16C57C
XXXXXXXXXXX /JW
XXXXXXXXXXX
YYWWNNN 0038CBA
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
n 1
E A2
c L
A1
B1
B p
eB
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
2
n 1
E
A2
L
c
A1 B1
eB B p
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
2
n 1
A A2
c L
B1
A1
B p
eB
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
p
E1
2
B n 1
h
45
c
A A2
L A1
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
B
2
n 1
h
45
c
A A2
L A1
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
p
B 2
n 1
c
A A2
L A1
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
p
B
2
n 1
A
c
A2
A1
L
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
W2 D
n 1
W1
A A2
c L
A1
eB B1
B p
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
2
n 1
A A2
c L
B1
eB A1
B p
X
XORLW ............................................................................... 60
XORWF............................................................................... 60
Z
Zero (Z) bit ...................................................................... 9, 29
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