EE309 Notes 13

VDD
Lecture 13
Current mirrors R
IREF
IOUT
In this lecture:
13.1. Current mirrors Introduction
13.2. Channel-length modulation
13.3. Small-signal analysis
13.4. Questions Q1
Q2
13.1. Introduction to the current mirror W1/L1 W2/L2
VOUT
• In lecture 12 we biased the differential amplifier with a near-ideal current +
source, drawing 2 I BIAS . VGS
-
• Near-ideal means it draws a little A.C. current; this was modeled in the
small-signal analysis as a large resistor Rout – this gave rise to some
common-mode amplification. The larger Rout, the smaller the common-
mode gain ACM.
• In this lecture we see how a current mirror acts as a near-ideal D.C. (bias) At the heart is the MOSFET Q1, whose drain and gate are shorted. It is thus
current source, which we can use to bias the diff-amp. operating in its saturation region, and
EE301 GB12 Page 1 EE301 GB12 Page 2
1 W
I D1 = µCox 1 (VGS − VT )2 (neglecting channel-length modulation). We can use the
2 L1
current mirror to do
However, the drain current is set by the external circuit: current scaling,
simply by changing
VDD − VGS the width-length
I D1 = I REF = a constant. ratios of the
R
MOSFETS. In a
Now consider transistor Q2. It has the same VGS as Q1, so assuming it too is practical IC design
in saturation, then we do this by connect
a number of identical
1 W
I OUT = I D 2 = µCox 2 (VGS − VT )2 MOSFETs together.
2 L2
The current doubler
(neglecting channel-length modulation).
(right) uses identical
These two equations allow us to come up with a simple expression for IOUT: MOSFETS: Q2 and
Q3 in parallel act like
W1 L1 a single MOSFET
I OUT = I REF A very useful relation. whose width is 2W.
W2 L2
Hence IOUT=2IREF
In the special case of identical MOSFETs, then, IOUT mirrors IREF, as long as
Q2 stays in saturation.

13.2. Effect of channel-length modulation 13.3. Small-signal analysis
Taking channel-length modulation into account means that the output current Some small-signal analysis will show how changing Vout affects Iout:
IOUT has a slight dependency on the voltage VOUT. Hence the current mirror is
not a perfectly ideal current source. This dependency can be small-signal Recall: in small-signal analysis all D.C. currents and voltages go to zero
modeled by a tiny conductance 1/rO:
so here’s the circuit diagram on page 2:
So the output resistance rO of the
IOUT • IREF, VDD → 0 (naturally),
current mirror is less than infinite, Triode region
Active region
and is given by • vDS1 is completely defined by IREF, so vDS1 is D.C.; vds1 → 0
IREF
∆VOUT I OUT • The gate-source connection on Q1 means vgs1 = vgs2 = vds1=0
rO = =
∆I OUT V A2 Slope=1/rO
where
IOUT is Q2’s drain current
VA2 is Q2’s Early voltage
VGS-VT VGS VOUT
So a slight rise in VOUT causes a
slight rise in IOUT.
• It is clear that this simplifies to the iOUT 13.4. Active loads

diagram right, giving
v • Active loads commonly replace resistors in IC circuits such as diff-amps
i out = out vout and current mirrors.
rO ro
o Fabricating a resistor in a real IC design is quite difficult and costly:
o Lots of space used on the wafer
o IC Resistors suffer from high tolerances
• So there is a tiny small-signal iout due to rO caused by channel-length
modulation in Q2 • Recall also:
o Using a resistor as RLOAD in a diff-amp involves a poor trade-off
• In other words, a small change vout in the biasing voltage Vout across the between gain and available swing voltage:
current mirror results in a small change iout in the current drawn IOUT.
AV = − g m RLOAD
• This changeability is not a good thing for a D.C. current source!
So increasing RLOAD
• We can shrink its effect by increasing rO somehow. The favourite way is a. increases AV (good), but
using source degeneration, which we will see next lecture. b. increases the D.C. voltage drop across RLOAD (bad)
• Ideally, we would like

o A small RLOAD for biasing (D.C.) and
o A large RLOAD for high small-signal gain
• An active load can deliver!

How an active load works To the biasing circuit, the large-signal resistance of the active load is simply
An active load simply consists of a MOSFET in saturation. Shorting the drain
VSD VSD
and gate guarantees this. RBIAS = = small
I D I BIAS
ID
VDD
However, the small-signal resistance is much higher:
PMOS VSG IBIAS
vsd ∆VSD V
rO = = = A bigger.
Slope=1/rO id ∆I D I BIAS
Slope= (exaggerated)
1/RBIAS
IBIAS
In the diff-amp circuit we can use this in a
VA VSG-VT VSG VSD current mirror configuration to achieve
two perfectly matched load resistors.
Because the diff-amp circuit is
symmetric, the bias (D.C.) voltage at the
drain of each MOSFET is the same:
≈ ≈ VD1 = VD 2 = VDD − VSG
Then VDS1 = VDS 2 , I D1 = I D 2 and so the bias resistances are perfectly

matched:
As the length L of the MOSFET decreases:

The small-signal equivalent circuit of the
diff-amp with active loads is given right: • channel-length modulation worsens
And the gain of the diff amp is now • VA shrinks (VA ∝ L)
AV = − g m rO so a long MOSFET will give a high rO, and thus high gain.
We can thus raise the gain of the diff-

amp by raising rO:
In summary: active loads
VA
rO = • replace very bulky resistors with small transistors
I BIAS
• provide a large AC resistance while providing a small DC resistance
needed for biasing.
• allow the output node voltage to be fixed through a combination of bias

current and the W/L transistor ratio
where VA is the Early voltage for the MOSFET. How?
• improve gain by increasing channel-length modulation and by
increasing the gm of the input transistors.
• Can easily give gains exceeding 1000.

13.5. Questions
1. How come in the current mirror, drain-gate shorting guarantees
saturation?
2. Find a value for R on page 3
3. Design the basic current mirror of page 2 to obtain an output current

whose nominal value is 100 µA. Find R if Q1 and Q2 are matched, and
IREF=100 µA VDD=5 V
L1= L2=10 µm W1= W2=100 µm
VT = 1 V µCox = 20 µA/V2.
What is the lowest possible value of VOUT?
Assuming the fabrication technology results in an Early voltage VA=10L,

where L is in microns and VA is in volts, find rO of the current source. Also
find the change in output current resulting from a 3-V change in VOUT.
(Sedra & Smith example 5.9)
END OF LECTURE
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VDD

EE301 GB12 Page 3 EE301 GB12 Page 4

EE301 GB12 Page 5 EE301 GB12 Page 6

• It is clear that this simplifies to the iOUT 13.4. Active loads

• Ideally, we would like

• An active load can deliver!

≈ ≈ VD1 = VD 2 = VDD − VSG

Then VDS1 = VDS 2 , I D1 = I D 2 and so the bias resistances are perfectly

EE301 GB12 Page 9 EE301 GB12 Page 10

As the length L of the MOSFET decreases:

We can thus raise the gain of the diff-

• allow the output node voltage to be fixed through a combination of bias

• Can easily give gains exceeding 1000.

EE301 GB12 Page 11 EE301 GB12 Page 12

2. Find a value for R on page 3

3. Design the basic current mirror of page 2 to obtain an output current

What is the lowest possible value of VOUT?

Assuming the fabrication technology results in an Early voltage VA=10L,

EE301 GB12 Page 13

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