EE309 Notes 20 PDF

20.1.
Miller compensation and pole splitting

Lecture 20
Two-stage op-amp design part II
In this lecture:
20.1 Miller compensation and pole splitting
The pole frequencies in the absence of Cf
The new pole frequencies including Cf
20.2 The effect of Cf on slew rate
Extreme scenario 1
Extreme scenario 2 The small-signal equivalent circuit of our two-stage amplifier is shown above.
20.3 Mixing NMOS and PMOS
R1 and R2 represent the total small-signal output resistances of stage 1 and 2,
respectively – drain source resistances of the MOSFETS, bias current
sources etc.
C1 and C2 represent the total parasitic capacitances on the input and output.
Using the small-signal equivalent circuit above, we can examine the effect of
Cf on the poles of the two-stage amplifier circuit.
EE301 GB20 Page 1 EE301 GB20 Page 2
The pole frequencies in the absence of Cf g m3

Note that this has a zero at s = -- usually a very high frequency, too
In the absence of the compensating capacitor Cf, there are two poles – one at Cf
the input and one at the output. Call them ωp1 and ωp2:
high to worry about. We can neglect its effect here.
1 1
ω p1 = and ω p 2 = To find the new pole positions write the denominator polynomial as
R1C1 R2C2
⎛ s ⎟⎞⎛⎜ s ⎞⎟ s s2
D ( s ) = ⎜1 + 1+ ≈ 1+ + (2)
⎜ ⎟⎜ ⎟
The new pole frequencies including Cf ⎝ ω ' p1 ⎠⎝ ω ' p 2 ⎠ ω ' p1 ω ' p1 ω ' p 2
Applying Kirchoff’s current law to the input and output node in the circuit
above with Cf present, we can find a very interesting expression for the if ω'p1<<ω'p2. Equating the terms in (2) with the denominator of (1) gives
voltage gain:
1 1
ω ' p1 = ≈
vo 2
=
( )
− g m1 sC f − g m3 R1R2 R1C1 + R2C2 + C f (R1 + R2 + g m3 R1R2 ) g m3 R2C f R1
(3)
[
vid ⎧1 + R1C1 + R2C2 + C f (R1 + R2 + g m3 R1R2 ) s ⎫ ] (1)
[ ]
⎨ ⎬ and
⎩+ R1R2 C1C2 + C f (C1 + C2 ) s
2
⎭ g m3C f
[Please try this at home!] ω ' p2 = (4)
C1C2 + C f (C1 + C2 )

Equations (3) and (4) show that increasing Cf reduces ω'p1 and increases
ω'p2. This is referred to as pole splitting 20.2. Effect of Cf on slew rate
One drawback of adding a compensating capacitor in this way is that it slows
Comments the slew rate for the op-amp.
1. Pole splitting is very useful: increasing Cf forces the second pole ω'p2 The slew rate of an amplifier is the maximum rate of change of vout in
to the right, increasing the compensated open-loop gain and improving response to vin.
the amp’s high-frequency performance.
The slower slew rate is especially noticeable when we apply widely-swinging
2. In the modified expression for ω'p1 the effect of Cf is multiplied by the input voltages that are changing rapidly (high frequency).
gain of stage 2:
The slew rate for a LM741 op-amp is typically 0.5 V/µs, but other op-amps
A2 = -gm3R2 are faster – e.g. the LM7301 has a slew rate of 1.25 V/µs and is thus capable
of handling higher frequencies.
to give the new value of ω'p1, as Miller’s theorem predicts. This means
that the required value for Cf is much smaller than the CC required for Consider two extreme scenarios:
simple pole-shifting compensation.
Extreme Scenario 1 1. vIN+ suddenly increases to vINMAX, and vIN- suddenly drops to vIN MIN
2. The bias current IBIAS1 suddenly shifts completely to the left-hand arm: the
current in Q2 goes to zero
3. The current mirror forces IBIAS1 down the right-hand arm, resulting in a
surge of current IBIAS1 into the capacitor Cf.
4. Cf takes some time to charge up; hence
5. The voltage across Cf (and hence vO1) rises at a limited rate – the slew
rate. The voltage across Cf is related to the current by
⎡ dV ⎤
I BIAS1 = C f ⎢ C ⎥
⎣ dt ⎦ MAX
The slew rate is then the maximum rate of change of vO1 (and hence vO2):
⎡ dVC ⎤ I
⎢⎣ dt ⎥⎦ = BIAS1
MAX Cf

Extreme Scenario 2 20.3. Mixing NMOS and PMOS
This is similar to extreme scenario 1, but here vIN+ suddenly = vIN MIN and vIN-
We are quite free to mix NMOS and PMOS technologies in our design of a 2-
suddenly = vIN MAX, causing IQ1=0 and IQ2=IBIAS1. The current mirror causes all
stage op-amp. For example: NMOS for the diff-amp and PMOS for the
of this IBIAS1 to be drawn from the gate of Q3 (and Cf), so vO1 falls at a limited
second stage, or visa-versa.
rate – the same slew rate as we found in Extreme Scenario 1.
There are advantages to both choices. A lot depends on the required output
voltage, but aside from that the choice is generally for PMOS input diff-amp
stage and an NMOS output stage.
Benefits of PMOS Diff-Amp and NMOS Source Follower

1. PMOS transistors tend to have a lower VT, thus a higher VOD. This
allows them to turn on at a lower VGS, giving better current steering in
the diff-amp. This will help both the gain and, more importantly, the
slew rate.
2. NMOS common-source amplifiers tend to have higher

transconductance gm, which gives better high-frequency stability.
3. A NMOS source follower output stage is generally used with an NMOS

common-source amplifier output, as it suffers less voltage drop.
END OF LECTURE

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20.1.

Miller compensation and pole splitting

EE301 GB20 Page 1 EE301 GB20 Page 2

The pole frequencies in the absence of Cf g m3

EE301 GB20 Page 3 EE301 GB20 Page 4

EE301 GB20 Page 5 EE301 GB20 Page 6

4. Cf takes some time to charge up; hence

EE301 GB20 Page 7 EE301 GB20 Page 8

Benefits of PMOS Diff-Amp and NMOS Source Follower

2. NMOS common-source amplifiers tend to have higher

3. A NMOS source follower output stage is generally used with an NMOS

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