EECS 247

Analog-Digital Interface
Integrated Circuits
© 2008
Instructor: Haideh Khorramabadi
UC Berkeley
Department of Electrical Engineering and
Computer Sciences

Lecture 1: Introduction

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 1

Instructor’s Technical Background

• Ph.D., EECS department -UC Berkeley 1985, advisor Prof. P.R. Gray
– Thesis topic: Continuous-time CMOS high-frequency filters
• Industrial background
– 11 years at ATT & Bell Laboratories, N.J., in the R&D area as a circuit designer
• Circuits for wireline communications: CODECs, ISDN, and DSL including
ADCs (nyquist rate & over-sampled), DACs, filters, VCOs
• Circuits intended for wireless applications
• Fiber-optics circuits
– 3 years at Philips Semiconductors, Sunnyvale, CA
• Managed a group in the RF IC department- developed ICs for CDMA &
analog cell phones
– 3 years @ Broadcom Corp. – Director of Analog/RF ICs in San Jose, CA.
• Projects: Gigabit-Ethernet, TV tuners, and DSL circuitry
– Currently consultant for IC design
• Teaching experience
– Has taught/co-taught EE247 @ UCB since 2003
– Instructor for short courses offered by MEAD Electronics
– Adjunct Prof. @ Rutgers Univ., N.J. : Taught a graduate level IC course

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 2

 Administrative Issues
• Course web page:
http://inst.eecs.berkeley.edu/~EE247/fa08
– Course notes will be uploaded on the course website prior to
each class
– Homeworks & due dates are posted on the course website
– Announcements regarding the course will be posted on the
home page, please visit course website often

• Lectures are web cast

http://webcast.berkeley.edu/courses
– Please try to attend the classes live to benefit from direct
interactions
– Make sure you use the provided microphones when asking
questions or commenting in the class

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 3

Office Hours & Grading

• Office hours:
– Tues./Thurs. 2:30-3:30pm @ 477 Cory Hall
(unless otherwise announced in the class)
– Extra office hours by appointment
– Feel free to discuss issues via email:
[email protected]

• Course grading:
– Homework/project 50%
– Midterm 20% (tentative date: Oct. 16)
– Final 30%

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 4

 Prerequisites & CAD Tools
• Prerequisites
– Basic course in signal processing (Laplace and z-
transform, discrete Fourier transform) i.e. EE120
– Fundamental circuit concepts i.e. EE105 and
EE140

• CAD Tools:
– Hspice or Spectre
– Matlab

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 5

Analog-Digital Interface Circuitry

Analog Output Analog Input

Analog World

Analog/Digital Digital Digital/Analog

Interface 001 Processor 1001 Interface
110 1010
010 0010

• Naturally occurring signals are analog

• To process signals in the digital domain
∴ Need Analog/Digital & Digital/Analog interface circuitry

Question: Why not perform the signal processing in the analog domain only
& thus eliminate need for A/D & D/A?

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 6

 CMOS Technology Evolution versus Time
ft [GHz]
0.065u
100 0.13u 0.045u
0.1u
0.25u
0.18u
0.35u
10 0.6u
0.8u

1u
1.5u
1 2u
3u
6u Year
75 80 85 90 95 ’00 ’05 ’10
For NMOS @ (VGS - Vth = 0.5V )
*Ref: Paul R. Gray UCB EE290 course ‘95
International Technology Roadmap for Semiconductors, http://public.itrs.net

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 7

CMOS Device Evolution

Progression from 1975 to 2005

• Minimum feature sizes ~X1/100

• Cut-off frequency ft ~X300
• Minimum size device area ~1/L2
• Number of interconnect layers ~X8

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 8

 Impact of CMOS Scaling on
Digital Signal Processing
Direct beneficiary of VLSI technology down scaling
– Digital circuits deal with “0” & “1” signal levels only
Æ Not sensitive to “analog” noise
– Si Area/function reduced drastically due to
• Shrinking of feature sizes
• Multi metal levels for interconnections (currently >8 metal
level v.s. only 1 in the 1970s)
– Enhanced functionality & flexibility
– Amenable to automated design & test
– “Arbitrary” precision
– Provides inexpensive storage capability

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 9

Analog Signal Processing Characteristics

• Sensitive to “analog” noise
• Has not fully benefited from technology down scaling:
– Supply voltages scale down accordingly
Æ Reduced voltage swings Æ more challenging analog
design
– Reduced voltage swings requires lowering of the
circuit noise to keep a constant dynamic range
Æ Higher power dissipation and chip area
• Not amenable to automated design
• Extra precision comes at a high price
• Rapid progress in DSP has imposed higher demands
on analog/digital interface circuitry
ÆPlenty of room for innovations!

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 10

 Cost/Function Comparison
DSP & Analog
• Digital circuitry: Fully benefited from CMOS device scaling
– Cost/function decreases by ~29% each year
™Cost/function X1/30 in 10 years*
• Analog circuitry: Not fully benefited from CMOS scaling
– Device scaling mandates drop in supply voltagesÆ
threaten analog feasibility
™Cost/function for analog ckt almost constant or increase

¾ Rapid shift of function implementation from processing in

analog domain to digital & hence increased need for A/D &
D/A interface circuitry

*Ref: International Technology Roadmap for Semiconductors, http://public.itrs.net

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 11

Digitally Assisted Analog Circuitry

• Analog design has indeed benefited
from the availability of inexpensive on-
chip digital capabilities
• Examples:
– Compensating/calibrating ADC & DAC
inaccuracies
– Automatic frequency tuning of filters &
VCOs
– DC offset compensation

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 12

 Analog Digital Interface Circuitry
Example: Digital Audio
Analog Input
• Goal-Lossless archival and
transmission of audio signals
Analog
• Circuit functions:
Preprocessing
– Preprocessing
• Amplification A/D
• Anti-alias filtering Conversion
– A/D Conversion
• ResolutionÆ16Bits DSP
– DSP
• Storage
D/A
• Processing (e.g. recognition)
Conversion
– D/A Conversion
– Postprocessing Analog
• Smoothing filter Postprocessing
• Variable gain amplification
Analog Output

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 13

Example: Dual Mode CDMA (IS95)& Analog Cellular Phone

RF & Baseband

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 14

 Example: Typical Dual Mode Cell Phone
Contains in integrated form the following interface circuitry:

• 4 RX filters
• 3 or 4 TX filters
Dual Standard, I/Q
• 4 RX ADCs
• 2 TX DACs
• 3 Auxiliary ADCs Audio, Tx/Rx power
control, Battery charge
• 8 Auxiliary DACs control, display, ...

Total: Filters Æ 8
ADCs Æ 7
DACs Æ 12

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 15

Areas Utilizing Analog/Digital Interface Circuitry

• Communications
– Wireline communications
• Telephone related (DSL, ISDN,
CODEC)
• Television circuitry (Cable
modems, TV tuners…)
• Ethernet (Gigabit,
10/100BaseT…)
– Wireless
• Cellular telephone (CDMA,
Analog, GSM….)
• Wireless LAN (Blue tooth,
802.11a/b/g…..)
• Radio (analog & digital),
Television
• Personal Data Assistants
• Computing & Control
– Storage media (disk drives, digital
tape)
– Imagers & displays

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 16

Areas Utilizing Analog/Digital Interface Circuitry
• Instrumentation
– Electronic test equipment
& manufacturing
environment ATEs
– Semiconductor test
equipment
– Physical sensors &
actuators
– Medical equipment
• Consumer Electronics
– Audio (CD, DAT, MP3)
– Automotive control,
appliances, toys

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 17

UCB Graduate Level Analog Courses

EECS 247 - 240 - 242
• EECS 240
– Transistor level, building blocks such as opamps, buffers, comparator….
– Device and circuit fundamentals
– CAD Tools Æ SPICE

• EECS 247
– Filters, ADCs, DACs, some system level
– Signal processing fundamentals
– Macro-models, large systems, some transistor level, constraints such as finite gain,
supply voltage, noise, dynamic range considered
– CAD Tools Æ Matlab, SPICE

• EECS 242
– RF amplification, mixing
– Oscillators
– Exotic technology devices
– Nonlinear circuits

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 18

 Material Covered in EE247
• Filters
– Continuous-time filters
• Biquads & ladder type filters
• Opamp-RC, Opamp-MOSFET-C, gm-C filters
• Automatic frequency tuning techniques
– Switched capacitor (SC) filters
• Data Converters
– D/A converter architectures
– A/D converter
• Nyquist rate ADC- Flash, Pipeline ADCs,….
• Oversampled converters
• Self-calibration techniques
• Systems utilizing analog/digital interfaces
– Wireline communication systems- ISDN, XDSL…
– Wireless communication systems- Wireless LAN, Cellular
telephone,…
– Disk drive electronics
– Fiber-optics systems

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 19

Books (on reserve @ Eng. Library)

(NOT required to be purchased),

• Filters
– A. Williams and F. Taylor, Electronic Filter Design Handbook, 3rd edition, McGraw-Hill,
1995.
– W. Heinlein & W. Holmes, “Active Filters for Integrated Circuits”, Prentice Hall Int., Inc.
Chap. 8, 1974. Good reference for signal flowgraph techniques
– A. Zverev, Handbook of Filter Synthesis, Wiley, 1967.
A classic; focus is on passive ladder filters. Tables for implementing ladder filters (replaces
a CAD tool).

• Data Converters
– R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd
edition, Kluwer, 2003.
– B. Razavi, Data Conversion System Design, IEEE Press, 1995.
– S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, 1997.

• General
– Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
– Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.

™ Note: a list of relevant IEEE publications is posted on the course website. Some
will be noted as mandatory reading and the rest optional

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 20

 Introduction to Filters
• Filtering Æ Provide frequency selectivity and/or phase shaping
– Oldest & most common type of signal processing

Signal Signal
Amplitude Amplitude

0 f 0 f

Lowpass
Filter Vout
Vin

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 21

Introduction to Filters

• Typical filter applications:

– Extraction of desired signal from many
(radio, TV, cell phone, ADSL…..)
– Separating signal and noise
– Anti-aliasing
– Phase equalization
– Amplifier bandwidth limitations

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 22

 Ideal versus Practical Filters
Example: Lowpass Filter
• Ideal filter • Practical filter
– Brick-wall characteristics – Ripple in passband
– Flat magnitude response in magnitude response
the passband – Limited rejection of out-of-
– Infinite level of rejection of band signals
out-of-band signals

H ( jω ) H ( jω )

ω
Ideal Lowpass Brick-Wall Filter More Practical Filter ω

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 23

Simplest Filter
First-Order Lowpass RC Filter (LPF1)

R1=150 kOHM C1
10pF

Steady-state frequency response:

Vout ( s ) 1
H( s ) = =
Vin( s ) s
1+
ωo
1
wi t h ωo = = 2π × 1 0 0k H z
RC
EECS 247 Lecture 1: Introduction © 2008 H.K. Page 24
 S-Plane Poles and Zeros
1
s-plane (pzmap):
H (s) = jω
s
1+
ωo

Pole: p = − ωo
p=-ωo σ
Zero: z → ∞

1 1
H (s) = =
ω 2
1+ j ω
ωo 1+
2
ωo

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 25

Filter Frequency Response

Bode Plot
H ( s = jω ) ω =0 = 1
0
Magnitude (dB)

-20
H ( s = jω ) ω =ω = 1/ 2 -40
0
-60
-100dB!

H ( s = jω ) ω →∞ = 0 -80
-100
-120
0
Asymptotes:
Phase (deg)

-30
- 20dB/dec magnitude rolloff
- 90degrees phase shift per 2 decades -60

-90
1 2 3 4 5 6 7 8 9 10
10 10 10 10 10 10 10 10 10 10
Frequency [Hz]

Question:
can we really get 100dB attenuation at 10GHz?

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 26

 First-Order Low-Pass RC Filter
Including Parasitics (LPF2)
Cp=10fF

R1=150kOHM
C1
10pF

1 1
1 + sRCP Pole : p=− ≈−
R (C + CP ) RC
H ( s) =
1 + sR (C +C P ) Zero : z=−
1
RCP

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 27

Filter Frequency Response

0
Magnitude (dB)

-20
H ( jω ) ω =0 = 1 -40

CP -60
H ( jω ) ω→∞ =
C + CP -80
0

CP
Phase (deg)

≈
C -45

= 10−3
-90
= −60dB 10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10

Frequency [Hz]

• Beware of important parasitics & include them in the model …

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 28

 Dynamic Range & Electronic Noise

• Dynamic range is defined as the ratio of maximum

possible signal handled by a circuit and the minimum
useful signal
– Maximum signal handling capability usually determined by
maximum possible voltage swings which in turn is a
function of supply voltage & circuit non-linearity
– Minimum signal handling capability is normally
determined by electronic noise
• Amplifier noise due to device thermal and flicker noise
• Resistor thermal noise
• Dynamic range in analog ckts has direct implications
for power dissipation

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 29

Analog Dynamic Range

Example: First Order Lowpass Filter
• Once the poles and zeroes of the analog filter
transfer function are defined then special attention
must be paid to the actual implementation

• Of the infinitely many ways to build a filter with a

given transfer function, each of those combinations
result in a different level of output noise!

• As an example noise and dynamic range for the 1st

order lowpass filter will be derived

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 30

 First Order Filter Noise
• Capacitors are
noiseless
• Resistors have thermal R
vIN vOUT
noise
– This noise is uniformly
distributed in the C
frequency domain from
dc to infinity
– Frequency-independent
noise is called “white
noise”

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 31

Resistor Noise
• Resistor noise
characteristics
– A mean value of zero R
– A mean-squared value vIN vOUT
ohms
vn2 = 4k BTr RΔf C

measurement bandwidth (Hz)

Volts2
absolute temperature (°K)

Boltzmann’s constant = 1.38e-23 J/°K

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 32

 Resistor Noise
• Theoretically, resistor rms
noise voltage in a 10Hz band
centered at 1kHz is the
same as resistor rms noise R
in a 10Hz band centered at vIN vOUT
1GHz

• Resistor noise spectral C

density, N0, is the rms noise
per √Hz of bandwidth:

vn2
N0 = = 4k BTr R
Δf

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 33

Resistor Noise
Good numbers to memorize:
• N0 for a 1kΩ resistor at room
temperature is 4nV/√Hz
R
• Scaling R, vIN vOUT
– A 10MΩ resistor gives 400nV/√Hz
– A 50Ω resistor gives 0.9nV/√Hz
C
• Or, remember

kBTr = 4x10-21 J (Tr = 17 oC)

• Or, remember

kBTr /q = 26mV (q = 1.6x10-19 C)

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 34

 First Order Filter Noise
• To derive noise @ the output
node:
– Short circuit the input to
ground. R
- + vOUT
– Resistor noise gives the filter vIN
a non-zero output when vIN=0 e
– In this simple example, both
the input signal and the C
resistor noise obviously have
the same transfer functions to
the output
– Since noise has random
phase, we can use any
polarity convention for a noise
source (but we have to use it
consistently)

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 35

First Order Filter Noise

• What is the thermal noise of this
RC filter?

• Let’s ask SPICE! R=8kΩ

Netlist: vIN - + vOUT
e
*Noise from RC LPF C=1nF
vin vin 0 ac 1V
r1 vin vout 8kOhm
c1 vout 0 1nF
.ac dec 100 10Hz 1GHz
.noise V(vout) vin
.end

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 36

 Output Noise Spectral Density
100
20 kHz corner
Noise Spectral Density (nV/√Hz)

10

N 0 = 4k BTr R
1 nV
= 8 ×4
Hz
nV
= 11.3
0.1 Hz

0.01
101 103 105 107 109 [Hz]

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 37

Total Noise
• Total noise is what the display on a volt-meter connected to vo
would show!
• Total noise is found by integrating the noise power spectral
density within the frequency band of interest
• Note that noise is integrated in the mean-squared domain,
because noise in a bandwidth df around frequency f1 is
uncorrelated with noise in a bandwidth df around frequency f2
– Powers of uncorrelated random variables add
– Squared transfer functions appear in the mean-squared integral
f2
vo2 = ∫ vn2 H( jω ) 2df
f1
∞
vo2 = ∫ 4kB T R H( 2π jf ) 2df
0
*Ref: “Analysis & Design of Analog Integrated Circuits”, Gray, Hurst, Lewis, Meyer- Chapter 11

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 38

 Total Noise
∞
2
vo2 = ∫ 4kBTR H( 2π j f ) d f
0
∞ 2
= ∫ 4kBTR 1 df
0
1 + 2π j fRC

→ vo2 = kBT
C

• This interesting and somewhat counter intuitive result means

that even though resistors are the components generating the
noise, total noise is determined by noiseless capacitors!

• For a given capacitance, as resistance goes up, the increase in

noise density is balanced by a decrease in noise bandwidth

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 39

kT/C Noise
• kT/C noise is a fundamental analog circuit limitation

• The rms noise voltage of the simplest possible (first order) filter is
(kBT/C)1/2

• For 1pF capacitor, (kBT/C)1/2 = 64 μV-rms (at 298°K)

• 1000pF gives 2 μV-rms

• The noise of a more complex & higher order filter is given by:
(α x kBT/C)1/2

where α depends on implementation and features such as filter order

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 40

 Low Pass Filter Total Output Noise (LPF1)

Noise Spectral Density (nV/√Hz) 100

Integrated Noise ( μVrms)

10
2μVrms
1

0.1

0.01
101 103 105 107 109 [Hz]

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 41

LPF1 Output Noise

• Note that the integrated noise essentially

stops growing above 100kHz for this 20kHz
lowpass filter

• Beware of faulty intuition which might tempt

you to believe that an 80Ω, 1000pF filter has
lower integrated noise compared to our
8000Ω, 1000pF filter…

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 42

 LPF1 Output Noise
100
Noise Spectral Density (nV/√Hz)
Integrated Noise ( μVrms) 80Ω &1000pF 8000Ω & 1000pF
10

0.1

0.01
101 103 105 107 109 [Hz]

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 43

Analog Circuit Dynamic Range

• Maximum voltage swing for analog circuits (assuming no inductors
are used!) can at most be equal to power supply voltage VDD
(normally is smaller)
1 VDD
• Assuming a sinusoid signal Æ Vmax ( rms ) =
2 2

k T
• Noise for a filter Æ Vn (rms ) = α B
C

V (rms ) VDD C
D.R. = max = [V/V]
Vn (rms ) 8α k BT

Æ Dynamic range in dB is:

⎛ C⎞
= 20log10 ⎜ VDD ⎟ + 75 [dB] with C in [pF]
⎝ α ⎠

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 44

 Analog Circuit Dynamic Range

• For integrated circuits built in modern CMOS

processes, VDD < 1.5V and C < 100pF
– D.R. < 98 dB (assuming α = 1)

• For PC board circuits built with “old-fashioned”

30V opamps and discrete capacitors of < 100nF

– D.R . < 140dB

– A 42dB advantage!

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 45

Dynamic Range versus Number of Bits

• Number of bits and dB are related:

D.R. = (1.76 + 6.02 N ) [dB] N → number of bits

– see “quantization noise”, later in the course

• Hence
98 dB Æ 16 Bits
140 dB Æ 23 Bits

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 46

 Dynamic Range versus Power Dissipation
• Each extra bit corresponds to 6dB extra dynamic range
• Increasing dynamic range by one bit Æ 6dB less noise Æ decrease
in noise power by 4x!
• This translates into 4x larger capacitors
• To keep speed constant (speed prop Gm/C): Gm must increase 4x
• Power dissipation is proportional to Gm (for fixed supply and Vdsat)

In analog circuits with performance limited by thermal noise,

1 extra bit costs 4x power dissipation
E.g. 16Bit ADC at 200mW Æ 17Bit ADC at 800mW

Do not overdesign the dynamic range of analog circuits!

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 47

Noise & Dynamic Range Summary

• Thermal noise is a fundamental property of

(electronic) circuits
• In filters, noise is closely related to
– Capacitor size
• In higher order filters, noise is a function of C, filter
order, Q, and depends on implementation
• Operational amplifiers used in active filters can
contribute significant levels of extra noise to overall
filter noise
• Reducing noise in most analog circuits is costly in
terms of power dissipation and chip area

EECS 247 Lecture 1: Introduction © 2008 H.K. Page 48