23 Tyga

EN - For pricing and availability in your local country please visit one of the below links:
DE - Informationen zu Preisen und Verfügbarkeit in Ihrem Land erhalten Sie über die unten aufgeführten Links:
FR - Pour connaître les tarifs et la disponibilité dans votre pays, cliquez sur l'un des liens suivants:
A8304SESTR-T
EN DE FR
This Datasheet is presented by Dieses Datenblatt wird vom Cette fiche technique est
the manufacturer Hersteller bereitgestellt présentée par le fabricant
A8304
Single LNB Supply and Control Voltage Regulator
Features and Benefits Description

▪ Integrated boost MOSFET, current sensing, and
The A8304 is a single channel low noise block regulator
compensation
(LNBR). The A8304 consists of a monolithic boost converter
▪ 704 kHz switching frequency for small low-cost
followed by a low-drop linear regulator. It is specifically
components
designed to provide the power and the interface signals to an
¯Ē
▪ S̄L̄ ¯Ē
¯P̄¯ pin for ultra-low power consumption mode
LNB down converter via coaxial cable in satellite TV receiver
▪ Adjustable LNB output current limit (250 to 950 mA*)
systems.
limit with shutdown timer
▫ Covers wide array of application requirements The A8304 requires few external components, with the boost
▫ Minimizes component sizing to fit each application switch and compensation circuitry integrated inside of the
▫ For startup, reconfiguration, and continuous output device. The 704 kHz switching frequency and user-controlled
▪ Boost peak current limit scales with LNB current limit output current limit minimize the size of the passive filtering
▪ Optional temporary increased current limit (+25%) components.
▪ Compatible with DiSEqC1.x control
The I2C™-compatible interface provides control capabilities for
Continued on the next page… complex system requirements, as well as diagnostic capabilities
for system fault reporting.
Package: 16-contact QFN (suffix ES) A sleep pin is available to maximize power savings and to
quickly shut down the device if needed, without using I2C™
control.
The A8304 is provided in a small 3 × 3 mm QFN package with
exposed pad for thermal dissipation. It is lead (Pb) free, with
100% matte tin leadframe plating.
3 mm × 3 mm × 0.75 mm
Functional Block Diagram

L1
VS 10 μH D1
C5 C6 C4
C2 100 μF 1 μF 100 nF
100 μF GNDLX LX BOOST VCP
VIN
CLK VFB D3
C1 VREG IC 704 kHz Charge
100 nF Boost Pump A
Power Osc BOOSTREF Regulator
C3
220 nF
0.8 V
+
GND LNB VOUT
VIN
PAD Ref Slew LNBREF Linear
DAC Rate + Regulator
Limiter
VDD ILIM OC D4
TCAP D2 C8 C10 C9 A
Tone 100 nF 220 nF 10 nF
R1 R2 R3 R4 R5 C7 Generator
100 nF
4 ISET
TONECTRL
VSEL3/2/1/0 RSET
Unlatched
SDA Status
PNG, CPOK
SCL I2C™
Interface
ADD SET A D3 and D4 are used for surge protection.
Latched TSD
Faults
SLEEP RST UVLO, OCP, VIN
Read Timer
TSD 45 ms
IRQ Fault
For recommended external components, refer to table 5
8304-DS
A8304 Single LNB Supply and Control Voltage Regulator
Features and Benefits (continued)

▪ 2-wire I2C™-compatible interface for control and status ▪ Diagnostic features: PNG
▫ Programmable LNB output voltage levels (2% accuracy) ▪ Extensive protection features: UVLO, OCP, TSD
▫ Enable/disable output
▫ Flexible 22 kHz tone generation methods
▫ SINK_DIS bit for controlling the push-pull output sink *maximum value depends on PCB thermal design
current threshold
Selection Guide
Part Number Packinga Description
A8304SESTR-Tb 7 in. reel, 1500 pieces/reel QFN surface mount

12 mm carrier tape 3 mm × 3 mm × 0.75 mm nominal height
aContact Allegro for additional packing options.
bLeadframe plating 100% matte tin.
Absolute Maximum Ratings

Characteristic Symbol Conditions Rating Unit
Load Supply Voltage, VIN pin VIN 18 V
Internally
Output Current1 ILNB A
Limited
Output Voltage; BOOST pin –0.3 to 32 V
Output Voltage; LNB pin Surge2 –1.0 to 32 V
Output Voltage; LX pin –0.3 to 30 V
Output Voltage; VCP pin –0.3 to 37 V
TCAP, ISET, VREG Pins –0.3 to 6 V
Logic Input Voltage –0.3 to 5.5 V
Logic Output Voltage –0.3 to 5.5 V
Operating Ambient Temperature TA Range S –20 to 85 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
1Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the
specified current ratings, or a junction temperature, TJ, of 150°C.
2Use Allegro recommended application circuit.
Package Thermal Characteristics*

RθJA
Package PCB
(°C/W)
ES 47 4-layer
* Additional information is available on the Allegro website.
Allegro MicroSystems, Inc. 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Pin-out Diagram
BOOST
GNDLX
VIN
LX
16
15
14
13
VCP 1 12 GND
LNB 2 11 VREG
PAD
ADD 3 10 ISET
IRQ 4 9 TCAP
5
6
7
8
SDA
SCL
TONECTRL
SLEEP
Terminal List Table
Name Number Function
ADD 3 Address select
BOOST 16 Tracking supply voltage to linear regulator
GND 12 Signal ground
GNDLX 15 Boost switch ground
IRQ 4 Interrupt request
ISET 10 Output current limit set via external resistor
LNB 2 Output voltage to LNB
LX 14 Inductor drive point
PAD Pad Exposed pad; connect to the ground plane, for thermal dissipation
SCL 5 I2C™-compatible clock input
SDA 6 I2C™-compatible data input/output
When this pin is pulled low, the A8304 enters sleep mode; LNB output,
S̄¯L̄¯Ē
¯Ē
¯P̄
¯ 8 boost, I2C™ communication, and charge pump disabled to reduce input
quiescent current to less than 15 μA
TCAP 9 Capacitor for setting the rise and fall time of the LNB output
Apply external 22 kHz tone or tone on-and-off signal to enable/disable
TONECTRL 7
internal tone
VCP 1 Gate supply voltage
VIN 13 Input supply voltage
VREG 11 Analog supply

ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VIN = 10 to 16 V, S̄¯L̄¯Ē¯Ē¯P̄¯ = 1, as noted2; unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Unit
General
VIN = 12 V, ILNB = 10 mA, see table 2 for
Output Voltage Accuracy %VLNB –2 – +2 %
DAC settings
VIN = 12 V, VLNB = 13.667 V,
– 38 76 mV
ΔILNB = 10 to 450 mA
Load Regulation ΔVLNB(Load)
VIN = 12V, VLNB = 19.000 V,
– 45 90 mV
ΔILNB = 10 to 450 mA
VIN = 10 to 16 V, VLNB = 13.667 V,
–10 0 10 mV
ILNB = 10 mA
Line Regulation ΔVLNB(Line)
VIN = 10 to 16 V, VLNB = 19.000 V,
–10 0 10 mV
ILNB = 10 mA
¯L̄¯Ē
S̄ ¯Ē¯P̄¯ = 0, VIN = 12 V – – 15 μA
Supply Current (Off) IIN(OFF)
ENB = 0, VIN = 12 V – 4 7 mA
ENB = 1, VIN = 12 V, VLNB = 19 V,
– 9 – mA
ILOAD = 0 mA, TONECTRL = 0
Supply Current (On)3 IIN(ON)
ENB = 1, VIN = 12 V, VLNB = 19 V,
– 15 – mA
ILOAD = 0 mA, TONECTRL = 1
Boost Switch On Resistance RDS(on)BOOST ISW = 450 mA – 400 – mΩ
Switching Frequency fSW 633 704 774 kHz
VBOOST – VLNB, no tone signal,
Linear Regulator Voltage Drop ∆VLR 600 800 1000 mV
ILOAD = 425 mA
TCAP capacitor (C7) charging –13 –10 –7 μA
TCAP Pin Current ITCAP
TCAP capacitor (C7) discharging 7 10 13 μA
For VLNB 13 → 19 V; C7 = 100 nF,
Output Voltage Rise Time3 tr(VLNB) – 10 – ms
ILOAD = 500 mA
For VLNB 19 → 13 V; CLOAD = 100 μF,
Output Voltage Pull-Down Time3 tf(VLNB) – 20 – ms
ILOAD = 0 mA, SINK_DIS = 0
ENB = 0 – 2 4 mA
SINK_DIS = 1, ENB = 1, TONECTRL = 0 – 7 10 mA
SINK_DIS = 0, ENB = 1, TONECTRL = 0,
– 30 50 mA
Absolute(VLNB-VSEL setting) < 1.5 V
Output Reverse Current3 IRLNB
SINK_DIS = 0, ENB = 1, TONECTRL = 1,
– 60 85 mA
Absolute(VLNB-VSEL setting) < 1.5 V
SINK_DIS = 0, ENB = 1, TONECTRL = 0 or 1,
– 7 10 mA
Absolute(VLNB-VSEL setting) > 1.5 V
20 MHz BWL; reference circuit shown in
Functional Block diagram; contact Allegro for
Ripple and Noise on LNB Output4 Vrip,n(pp) – 30 – mVPP
additional information on application circuit
board design
Continued on the next page…

ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V, S̄¯L̄¯Ē¯Ē¯P̄¯ = 1, as noted2; unless noted otherwise
General (continued)
VREG Voltage VVREG VIN = 10 V 4.97 5.25 5.53 V
ISET Voltage VISET VIN = 10 V 3.4 3.5 3.6 V
VIN = 10 V, VLNB = 13.667 V – 2.28 – V
TCAP Pin Voltage VTCAP
VIN = 10 V, VLNB = 19.000 V – 3.17 – V
Protection Circuitry
Output Overcurrent Limit5 ILNB(MAX) RSET = 60.4 kΩ 450 500 550 mA
Overcurrent Disable Time tDIS – 45 – ms
Boost MOSFET Current Limit IBOOST(MAX) RSET = 60.4 kΩ – 2600 – mA
VIN Undervoltage Lockout Threshold VUVLO VIN falling 8.05 8.35 8.65 V
VIN Turn On Threshold VIN(th) VIN rising 8.40 8.70 9.00 V
Undervoltage Hysteresis VUVLOHYS – 350 – mV
Thermal Shutdown Threshold3 TJ – 165 – °C
Thermal Shutdown Hysteresis3 ∆TJ – 20 – °C
With respect to VLNB setting; VLNB low,
PNGLOSET 88 91 94 %
PNG set to 1
Power Not Good (Low)
With respect to VLNB setting; VLNB low,
PNGLORESET 92 95 98 %
PNG reset to 0
Power Not Good (Low) Hysteresis PNGLOHYS With respect to VLNB setting – 4 – %
With respect to VLNB setting; VLNB high,
PNGHISET 106 109 112 %
PNG set to 1
Power Not Good (High)
With respect to VLNB setting; VLNB high,
PNGHIRESET 102 105 108 %
PNG reset to 0
Power Not Good (High) Hysteresis PNGHIHYS With respect to VLNB setting – 4 – %
Tone
Amplitude VTONE(PP) 550 700 900 mVPP
Frequency fTONE 20 22 24 kHz
Duty Cycle DCTONE ILNB = 425 mA, CLNB = 750 nF 40 50 60 %
Rise Time tR(TONE) 5 10 15 μs
Fall Time tF(TONE) 5 10 15 μs
Tone Control (TONECTRL Pin)
VH 2.0 – – V
Logic Input
VL – – 0.8 V
Input Leakage V(lkg) –1 – 1 μA
Sleep Mode Control ( S̄¯L̄¯Ē¯Ē¯P̄¯ Pin)
VSLP(H) 2.0 – – V
Logic Input
VSLP(L) – – 0.8 V
Input Leakage ISLP(lkg) – 50 – μA
Continued on the next page…

ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V, S̄¯L̄¯Ē¯Ē¯P̄¯ = 1, as noted2; unless noted otherwise
I2C™-Compatible Interface
Logic Input (SDA,SCL) Low Level VSCL(L) – – 0.8 V
Logic Input (SDA,SCL) High Level VSCL(H) 2.0 – – V
Logic Input Hysteresis VI2CIHYS – 150 – mV
Logic Input Current II2CI VI2CI = 0 to 5 V –1 <±1.0 1 μA
Logic Output Voltage SDA and IRQ VSDA , VIRQ ILOAD = 3 mA – – 0.4 V
Logic Output Leakage SDA and IRQ ILEAK VLNB = 0 to 5 V – – 10 μA
SCL Clock Frequency fCLK – – 400 kHz
I2C™ Address Setting
ADD Voltage for Address 0001,000 VADD1 0 – 0.7 V
ADD Voltage for Address 0001,001 VADD2 1.3 – 1.7 V
1Operation at 16 V may be limited by power loss in the linear regulator.
2Indicates specifications guaranteed from 0 ≤ T ≤ 125˚C
J MIN .
3Ensured by worst case process simulations and system characterization. Not production tested.
4LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout
recommendations. Not production tested.
5Current from the LNB output may be limited by the choice of Boost components.

Functional Description
Boost Converter/Linear Regulator RSET values of 100 kΩ and 60.4 kΩ respectively, per equation 1.
The LNB current limit has a set range of 250 to 950 mA, with
The A8304 solution contains a tracking current-mode boost
converter and linear regulator. The boost converter tracks the the maximum value dependent on thermal design parameters of a
requested LNB voltage to within 800 mV, to minimize power given application. If the LNB current limit is exceeded for more
dissipation. Under conditions where the input voltage, VBOOST , than the Overcurrent Disable Time (tDIS) then the A8304 will be
is greater than the output voltage, VLNB, the linear regulator must shut down and the OCP bit set, as shown in figure 1. The typical
drop the differential voltage. When operating in these conditions, LNB output current limit can be set according to the following
care must be taken to ensure that the safe operating temperature equation:
range of the A8304 is not exceeded.
ILNB(MAX) = 29,925 / RSET , (1)
The boost converter operates at 704 kHz typical. All the loop
where ILNB(MAX) is in mA and RSET is in kΩ. If the voltage at
compensation, current sensing, and slope compensation functions
the ISET pin is 0 V (that is, shorted to GND), ILNB(MAX) will
are provided internally.
be clamped to a moderately high value (approximately 1.5 A).
The A8304 has internal pulse-by-pulse current limiting on the Care should be taken to ensure that ISET is not inadvertently
boost converter and DC current limiting on the LNB output to grounded. If no resistor is connected to the ISET pin (that is, if
protect the IC against short circuits. When the LNB output is ISET is open-circuit), ILNB(MAX) will be set to approximately
shorted, the LNB output current is limited, and if the overcur- 0 A and the A8304 will not support any load (OCP will occur
rent condition lasts for more than 45 ms, the LNB output will
prematurely).
be disabled. If this occurs, the A8304 output must be re enabled
for normal operation. The system should provide sufficient time The BOOST pulse-by-pulse current limit, IBOOST(MAX), is auto-
between successive restarts to limit internal power dissipation; matically scaled along with the LNB output current limit. The
1 s to 2 s is recommended. typical BOOST current limit is set according to the following
At extremely light loads, the boost converter operates in a pulse- equation:
skipping mode. Pulse skipping occurs when the BOOST voltage IBOOST(MAX) = 3 × ILNB(MAX) + 1100 mA , (2)
rises to approximately 450 mV above the BOOST target output
voltage. Pulse skipping stops when the BOOST voltage drops where both IBOOST(MAX) and ILNB(MAX) are in mA.
200 mV below the pulse skipping level.
Automatically scaling the BOOST current limit allows the
Two or more satellite set top boxes LNBR outputs may be con- designer to choose the lowest possible saturation current of the
nected together (for example in the case when a splitter is used). boost inductor, reducing its physical size and PCB area, thus
In this case the A8304 that has the highest programmed voltage minimizing cost.
will supply the LNB and all other A8304s will effectively be off.
If the output of the A8304 IC supplying the LNB drops below Protection
the programmed value of the next highest voltage A8304, that
unit will automatically recover from providing no-output voltage, The A8304 has a wide range of protection features and fault diag-
monotonically start up and supply the voltage at its programmed nostics which are detailed in the Status Register section.
level. This unit will supply the LNB power.
Slew Rate Control During either start-up, or when the output
Charge Pump Generates a supply voltage above the internal voltage at the LNB pin is transitioning, the output voltage rise
tracking regulator output to drive the linear regulator control. and fall times can be set by the value of the capacitor connected
LNB and BOOST Current Limits The LNB output current limit, from the TCAP pin to GND (C7 in the functional block diagram).
ILNB(MAX) can be set by connecting a resistor (RSET) from the Note that during start-up, the BOOST pin is pre-charged to the
ISET pin to GND as shown in the functional block diagram. input voltage minus a voltage drop. As a result, the slew rate
For example 300 mA and 500 mA settings would correspond to control for the BOOST pin occurs from this voltage.

The value of C7 can be calculated using the following formula: ensures that the tone signal meets all specifications, even with no
load on the LNB output.
C7 = ( ITCAP × 6) / SR , (3)
ODT (Overcurrent Disable Time)
where SR is the required slew rate of the LNB output voltage, in
V/s, and ITCAP is the TCAP pin current specified in the Electrical If the LNB output current exceeds the set output current, for more
Characteristics table. The recommended value for C7, 100 nF, than tDIS , then the LNB output will be disabled and the OCP bit
should provide satisfactory operation for most applications. will be set. See figure 1.
Short Circuit Handling
The minimum value of C7 is 10 nF. There is no theoretical maxi-
mum value of C7, however too large a value will probably cause A8304 has optional 25% bump-up on current limit for tDIS /4
the voltage transition specification to be exceeded. Tone genera- period. This feature is enabled / disabled by setting or reset-
tion is unaffected by the value of C7. ting Control Register bit 0. When this bit is enabled, the output
current limit will be 25% more than set current limit for tDIS /4
Pull-Down Rate Control In applications that have to operate at period. After tDIS /4 period, output current limit comes down to
very light loads and that require large load capacitances (in the the set limit and the OCP_25P bit is reset to zero, The user must
order of tens to hundreds of microfarads), the output linear stage set this bit again to enable 25% bump-up on the next current limit
provides approximately 30 mA of pull-down capability, with event. If the OCP_25P bit is zero when LNB output is shorted to
TONECTRL = 0. This ensures that the LNB output voltage is ground, the LNB output current will be clamped to ILNB(MAX) .
ramped from 18 to 13 V in a reasonable amount of time. When If the short circuit condition lasts for more than 45 ms, the
the tone is on (TONECTRL = 1), the output linear stage must A8304 will be disabled and the OCP bit will be set. Refer to
increase its pull-down capability to approximately 60 mA. This figures 9 and 10.
18.6 to 19.6 V
13.3 to 15.6 V
VLNB
0V
ILNB (MAX) ILNB (MAX)

500 mA
ILNB
0 mA
ENB
PNG
DIS
OCP
Short Circuit
Startup Reconfiguration or Overload
t < tDIS t < tDIS t > tDIS
Figure 1. Startup, Reconfiguration, and Short Circuit operation using RSET = 60.4 kΩ, and a capacitive load
(OCP_25P bit = 0).

In-Rush Current Component Selection

At start-up or during an LNB reconfiguration event, a transient Boost Inductor
surge current above the normal DC operating level can The A8304 is designed to operate with a boost inductor value
be provided by the A8304. This current increase can be as high of 10 μH ±50%. The error amplifier loop compensation, current
as the set output current, for as long as required, up to a maxi- sense gain, and PWM slope compensation were chosen for this
mum of 45 ms. value of inductor. The boost inductor must be able to support the
peak currents required to maintain the maximum LNB output
Tone Generation
current without saturating. Figure 3 can be used to determine the
The A8304 offers two options for tone generation (figure 2). The
peak current in the inductor given the LNB load current. The
TONECTRL pin with the TMODE control bit provides the neces-
“typical” curve uses VIN = 12 V, VLNB = 19 V, L = 10 μH, and
sary control. The TMODE bit controls whether the tone source is
f = 704 kHz, while the “maximum” curve assumes VIN = 9 V,
internal or external.
VLNB = 20 V, L = 8 μH, and f = 633 kHz.
When the internal source is used (TMODE bit set to 0), the tone
Boost Electrolytic Capacitor
is gated with the TONECTRL pin. The internal tone frequency is
The A8304 is designed to operate with a low-ESR electrolytic
22 kHz. Note: This tone can be generated under no-load condi-
boost capacitor of 100 μF ±25% . The ESR of the boost capacitor-
tions and does not require an external DiSEqC™ filter.
must be less than 140 mΩ or the boost converter will be unstable.
When the TMODE bit is set to 1, an external 22-kHz tone signal General purpose electrolytic capacitors that do not specify an
can be applied to the TONECTRL pin. This tone frequency ESR should be avoided. Allegro recommends an electrolytic
appears at the LNB output, VLNB reaches the VLNBref level after capacitor that is rated to support at least 35 V and has an rms cur-
TONECTRL has been low for longer than 42 μs. rent rating to support the maximum LNB load.
TMODE (Low)
TONECTRL
(VLNBRef)
VLNB
Option 1. TMODE = 0, internal tone gated with TONECTRL.
TMODE (High)
TONECTRL
42 μs
(VLNBRef)
VLNB
Option 2. TMODE = 1, external tone applied on TONECTRL pin.

VLNB reaches preset level if external tone low for > 42 μs.
Figure 2. Tone generation options

Figure 4 can be used to determine the necessary rms current sheet. This configuration and these components have success-
rating of the boost capacitor given the LNB load current. The fully passed surge tests up to ±1000 V/500 A, with a 1.2/50 μs
“typical” curve uses VIN = 12 V, VLNB = 19 V, L = 10 μH, and − 8/20 μs combination wave. Every application will have its
f = 704 kHz while the “maximum” curve assumes VIN = 9 V, own surge requirements and the surge solution can be changed.
VLNB = 20 V, L = 8 μH, and f = 633 kHz. However, Allegro strongly recommends incorporating a form of
surge protection to prevent any pin of the A8304 from exceeding
Boost Filtering and LNB Noise its Absolute Maximum voltage ratings shown in this datasheet.
The LNB output noise depends on the amount of high-frequency
noise at the BOOST pin. To minimize the high-frequency noise
at the BOOST pin, a high quality ceramic capacitor should be
placed as close as possible to the BOOST pin. Allegro recom-
mends a 1 μF, 10% or 20%, X5R or X7R, 1206 size capacitor, 1200
with at least a 25 V rating. 1100
1000
IBOOST_CAP_RMS (mA )
For very noise-sensitive applications, a secondary inductor can 900
be added between the 100 μF and the 1 μF boost capacitors, as 800 Maximum
shown in figure 5. This inductor should be approximately 1 μH 700
and have a DC current rating of at least 1 ADC. Adding the 1 μH 600
inductor has been shown to reduce the LNB output noise by as 500
much as 50%. Allegro strongly recommends having provisions 400 Typical
for this 1 μH inductor in the PCB layout, but only populating it if 300
the LNB output is found to have too much noise after measuring 200
at the set-top box F-connector, at full-load. 100
100 200 300 400 500 600 700 800 900 1000
Surge Components Output Current (mA)
The circuit shown on page 1 of this datasheet includes D3 and
D4 for surge protection. Component recommendations for D3
and D4 are given in the bill-of-materials at the end of this data- Figure 4. Boost capacitor rms current versus ILNB
3500
Secondary Inductor
3250
3000 10 μH 1 μH
2750 1206
IBOOST_PEAK (mA)
2500 100 μF 1.0 μF/ 25 V (min)

2250 <140 mΩ
Maximum
2000
100 nF
1750
1500
14 15 1 16
1250
Typical
1000 LX GNDLX VCP BOOST
750
13
500 VIN
250 A8304
100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
Figure 3. Boost inductor peak current versus ILNB Figure 5. Application of the secondary boost inductor

I2C™-Compatible Interface signal “good transmission” to the slave. The receiver (either the
master or the slave) should set the AK bit high (AK = 1 or NAK)
The I2C™ interface is used to access the internal Control and for the ninth SCL pulse if eight bits of data are not received suc-
Status registers of the A8304. This is a serial interface that uses cessfully.
two lines, serial clock (SCL) and serial data (SDA), connected to
AK Bit During a Write Sequence When the master sends control
a positive supply voltage via a current source or a pull-up resis-
data (writes) to the A8304 there are three instances where AK
tor. Data is exchanged between a microcontroller (master) and
bits are toggled by the A8304. First, the A8304 uses the AK bit
the A8304 (slave). The master always generates the SCL signal.
to indicate reception of a valid seven-bit chip address plus a read/
Either the master or the slave can generate the SDA signal. The
write bit (R/W = 0 for write). Second, the A8304 uses the AK bit
SDA and SCL lines from the A8304 are open-drain signals so
to indicate reception of a valid eight-bit Control register address.
multiple devices may be connected to the I2C™ bus. When the
Third, the A8304 uses the AK bit to indicate reception of eight
bus is free, both the SDA and the SCL lines are high.
bits of control data. This protocol is shown in figure 6(A).
SDA and SCL Signals. SDA can only be changed while SCL is
AK Bit During a Read Sequence When the master reads status
low. SDA must be stable while SCL is high. However, an excep-
data from the A8304 there are four instances where AK bits are
tion is made when the I2C™ Start or Stop condition is encoun-
sent–three sent by the A8304 and one sent by the master. First,
tered. See the I2C™ Communication section for further details.
the A8304 uses the AK bit to indicate reception of a valid seven-
Acknowledge (AK) Bit The Acknowledge (AK) bit indicates a bit chip address plus a read/write bit (R/W = 0 for write). Sec-
“good transmission” and can be used two ways. First, if the slave ond, the A8304 uses the AK bit to indicate reception of a valid
has successfully received eight bits of either an address or control eight-bit Status register address. Third, the A8304 uses the AK
data, it will pull the SDA line low (AK = 0) for the ninth SCL bit to indicate reception of a valid seven-bit chip address plus a
pulse to signal “good transmission” to the master. Second, if the read/write bit (R/W = 1 for read). Finally, the master uses the AK
master has successfully received eight bits of status data from the bit to indicate receiving eight bits of status data from the A8304.
A8304, it will pull the SDA line low for the ninth SCL pulse to This protocol is shown in figure 6(B).
acknowledge acknowledge acknowledge

from LNBR (slave) from LNBR (slave) from LNBR (slave)
Start Chip Address W Control Register Address Control Data Stop
SDA A6 A5 A4 A3 A2 A1 A0 0 AK RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
(A) Write to Control Register
acknowledge acknowledge acknowledge acknowledge

from LNBR (slave) from LNBR (slave) from LNBR (slave) from master
Start Chip Address W Status Register Address Stop Start Chip Address R Status Data Stop
SDA A6 A5 A4 A3 A2 A1 A0 0 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK A6 A5 A4 A3 A2 A1 A0 1 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
(B) Read from Status Register
Figure 6. I2C™ Interface Read and Write Sequences. (A) for the I2C™ Write cycle and (B) for the I2C™ Read cycle.

I2C™ Communications the A8304 Status register requires a chip address with R/W = 0, a
Status register address, an I2C™ Stop condition, an I2C™ Start
I2C™ Start and Stop Conditions The I2C™ Start condition is condition, a “repeated” chip address with R/W=1, and finally the
defined by a negative edge on the SDA line while SCL is high. status data from the A8304. Reading from the A8304 Status regis-
Conversely, the Stop condition is defined by a positive edge on ter is shown in figure 6(B).
the SDA line while SCL is high. The Start and Stop conditions
• This 9-bit Chip Address cycle is identical to the Chip Ad-
are shown in figure 6. It is possible for the Start or Stop condition
dress cycle previously described for the Write Control Regis-
to occur at any time during a data transfer. If either a Start or Stop
ter sequence. It consists of A6 to A0, plus one read/write bit
condition is encountered during a data transfer, the A8304 will
(R/W = 0) from the master, followed by an Acknowledge bit
respond by resetting the data transfer sequence.
from the slave and finally an I2C™ Stop condition.
I2C™ Write Cycle Description Writing to the A8304 Control
register requires transmission of a total of 27 bits–three 8-bit • The Status Register Address cycle consists of a total of nine
bytes of data plus an Acknowledge bit after each byte. Writing to bits–eight bits of Status register address (RS7 to RS0) from the
the A8304 Control register is shown in figure 6(A). Writing to the master, followed by an Acknowledge bit from the slave. The
A8304 Control register requires a chip address with R/W = 0, a Status register address must be transmitted MSB (RS7) first.
Control register address, and the control data, as follows: The A8304 only has one Status register, so the Status register
• The Chip Address cycle consists of a total of nine bits– address is fixed at 0000 0000.
seven bits of chip address (A6 to A0) plus one read/write bit
(R/W = 0) to indicate a write from the master followed by an • The “Repeated” Chip Address cycle begins with an I2C™
Acknowledge bit (AK = 0 for reception of a valid chip address) Start condition followed by a 9-bit cycle identical to the Chip
from the slave. The chip address must be transmitted MSB Address cycle previously described for the Write Control
(A6) first. The first five bits of the A8304 chip address (A6 to Register sequence. It consists of A6 to A0, plus one read/write
A2) are fixed as 00010. The remaining two bits (A1 and A0) bit (R/W = 1) from the master, followed by an Acknowledge bit
are used to select one of four possible A8304 chip addresses. from the slave.
The DC voltage on the ADD pin programs the chip address.
See the Electrical Characteristics table for the ADD pin volt- • The Status Data cycle consists of a total of nine bits–eight bits
ages and the corresponding chip addresses. of status data (RD7 to RD0) from the slave, followed by an
• The Control Register Address cycle consists of a total of nine Acknowledge bit from the master. The status data is transmit-
bits–eight bits of control register address (RC7 to RC0) from ted MSB (RD7) first. The Status register bits are identified in
the master followed by an Acknowledge bit from the slave. The the Status Register section of this datasheet.
Control register address must be transmitted MSB (RC7) first.
The A8304 only has one Control register so the Control register Interrupt Request (IRQ) pin
address is 0000 0000.
• The Control Data cycle consists of a total of nine bits–eight The A8304 provides an interrupt request pin (IRQ), which is an
bits of control data (D7 to D0) from the master followed by open-drain, active low output. This output may be connected
an Acknowledge bit from the slave. The control data must be to a common IRQ line with a suitable external pull-up resistor
transmitted MSB first (D7). The Control register bits are identi- and can be used with other I2C™ compatible devices to request
fied in the Control Register section of this datasheet. attention from the master controller.
I2C™ Read Cycle Description Reading from the A8304 Status The IRQ output becomes active (logic low) when the A8304 rec-
register requires transmission of a total of 36 bits–four 8-bit ognizes a fault condition. The fault conditions that will force IRQ
bytes of data plus an Acknowledge bit after each byte. Reading active include undervoltage lockout (UVLO), overcurrent

protection (OCP), and thermal shutdown (TSD). The UVLO, status register of each to determine which device is requesting
OCP, and TSD faults are latched in the Status register and will attention. As shown in figure 7, the A8304 latches all conditions
not be unlatched until the A8304 Status register is successfully in the Status register and sets the IRQ to logic low when a fault
transmitted to the master controller (an AK bit must be received occurs. The IRQ bit is reset to logic high and the Status register is
from the master). See the description in the Status Register sec- unlatched when the master acknowledges the status data from the
tion and figure 7 for further details. A8304 (an AK bit must be received from the master).
When the master device receives an interrupt, it should address The disable (DIS) and Power Not Good (PNG) conditions do not
all slaves connected to the interrupt line in sequence and read the cause an interrupt and are not latched in the Status register.
acknowledge acknowledge acknowledge acknowledge

from LNBR (slave) from LNBR (slave) from LNBR (slave) from master
Start Chip Address W Status Register Address Stop Start Chip Address R Status Data Stop
SDA A6 A5 A4 A3 A2 A1 A0 0 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK A6 A5 A4 A3 A2 A1 A0 1 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
IRQ
STATUS
FAULT event, IRQ set low, Status register latched
register
unlatched
IRQ reset
Figure 7. Fault, IRQ, and Status Register Timing. When a FAULT occurs, the IRQ bit is set to low and the Status
register is latched. The IRQ bit is reset to high when the A8304 acknowledges it is being read. The Status register is
unlatched when the master acknowledges the status data from the A8304.
UVLO I2C™ UVLO (typ),

Thresholds rising: 6 V, falling: 4.2 V
VIN
VLNB
I2C™ Read Cycle
I2C™ I2C™
Inactive Inactive
IRQ (active low)
ENABLE Bit
(via I2C™)
t
Figure 8. IRQ and Fault Clearing in Response to Under Voltage at VIN (UVLO),the I2C™ port is active when VIN is
above I2C™ UVLO (6 V when VIN is rising). IRQ transitions low when VIN goes above I2C™ UVLO (6 V, VIN rising),
and the I2C™ Read cycle resets IRQ to logic high even if VIN is below UVLO. Even though IRQ is cleared below
UVLO, one more Read cycle is required after VIN goes above UVLO, to re-enable the A8304. While VIN is falling, IRQ
transitions low when VIN goes below UVLO, and the I2C™ Read cycle resets IRQ to logic high.

45 ms 45 ms
ILNB(MAX)
ILNB
VLNB LNB shorted to GND
I2C™ Read Cycle
IRQ (acƟve low)
Enable
(ENB bit, via I2C™)
Figure 9. IRQ and Fault Clearing in Response to Overcurrent (OCP). If the LNB output is grounded for more than
45 ms, the LNB output will be shut off, an overcurrent fault (OCP) will be latched in the Status Register, and the IRQ
pin will transition low. After an OCP fault, the LNB output does not respond to the Enable (ENB) bit until an I2C™
Read cycle is executed to report and clear the OCP fault. After a successful I2C™ Read, the IRQ pin transitions high
and the A8304 can be re-enabled, provided the LNB output is no longer grounded. (OCP_25P bit set to 0)
TSD
Threshold 165°C
TJ 145°C
Loss of cooling
or STB overload
LNB O/P
I2C™ Read Cycle
IRQ
(active low)
TSD Bit
(via I2C™)
ENABLE Bit
(via I2C™)
t
Figure 10. IRQ and Fault Clearing in Response to Thermal Shutdown (TSD). If the LNB junction temperature
rises above 165°C (typ), the LNB output will be shut off, a thermal shutdown fault (TSD) will be latched in the
Status Register, and the IRQ pin will transition low. After a TSD fault, the LNB output does not respond to the
Enable (ENB) bit until an I2C™ Read cycle is executed to report and clear the TSD fault. After a successful I2C™
Read, the IRQ pin transitions high and the A8304 can be re-enabled, provided the junction temperature is below
145°C (typ).

VLNB
1.25 × ILNB(MAX)
ILNB(MAX)
ILNB
tDIS /4 tDIS /4
tDIS tDIS tDIS

I2C™ Read
I2C™ Write
OCP_25P
Bit
OCP_25P
bit cleared
LNB LNB LNB LNB LNB
Shorted Shorted Shorted Shorted Shorted
to GND to GND to GND to GND to GND
removed removed
Figure 11. Initial 25% current limit bump up with OCP_25P bit enabled, disabled, and changed during current limit condition
with OCP period > tDIS .

VLNB
1.25 × ILNBx(MAX)
ILNBx ILNBx(MAX)
tDIS /4 <tDIS /4 tDIS /4
<tDIS <tDIS <tDIS

I2C™ Read
I2C™ Write
OCPx_25P
Bit
LNB LNB LNB LNB LNB LNB LNB LNB

Shorted Shorted Shorted Shorted Shorted Shorted Shorted Shorted
to GND to GND to GND to GND to GND to GND to GND to GND
removed removed removed removed
Figure 12. Initial 25% current limit bump up with OCP_25P bit enabled, disabled, and changed during current limit condition
with OCP period < tDIS .

I2C™-Compatible Interface Timing Diagram
tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF
SDA
SCL
tLOW tHIGH
I2C™-Compatible Timing Requirements

Characteristics Symbol Min. Typ. Max. Units
Bus Free Time Between Stop/Start tBUF 1.3 – – μs
Hold Time Start Condition tHD:STA 0.6 – – μs
Setup Time for Start Condition tSU:STA 0.6 – – μs
SCL Low Time tLOW 1.3 – – μs
SCL High Time tHIGH 0.6 – – μs
Data Setup Time tSU:DAT 100 – – ns
Data Hold Time* tHD:DAT 0 – 900 ns
Setup Time for Stop Condition tSU:STO 0.6 – – μs
Output Fall Time (VfI2COut(H) to VfI2COut(L)) tfI2COut – – 250 ns
*For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA
signal in order to bridge the undefined region of the SCL signal falling edge.

Control Register (I2C™-Compatible Write Registers)

All main functions of the A8304 are controlled through the I2C™ The LNB output will be programmed according the status of the
compatible interface via the 8-bit Control register. Table 1 shows VSEL3, VSEL2, VSEL1, and VSEL0 bits in the I2C™ Control
the functionality and bit definitions of the Control register. At register 0 as outlined in table 2.
power-up, the Control register is initialized to all 0s.
Table 1. Control Register 0 Definition, Address: 0000 0000

Bit Name Function Description
0 VSEL0
The available voltages provide levels for all the common
1 VSEL1 LNB output voltage control
standards plus the ability to add line compensation.
2 VSEL2 VSEL0 is the LSB and VSEL3 is the MSB to the internal
See table 2 for available output voltage selections
DAC.
3 VSEL3
0: Disable LNB Output
4 ENB Turns the LNB output on or off.
1: Enable LNB Output
0: Internal tone, gated with TONECTRL pin
5 TMODE Controls tone mode.
1: External 22 kHz logic pulse, on TONECTRL pin
25% bump up over the current limit for tDIS / 4 period;
6 OCP_25P
bit resets automatically after tDIS / 4 period
0: Enable internal sinks
7 SINK_DIS Controls use of internal sinks.
1: Disable internal sinks
Table 2. Output Voltage Selection

VSEL3 VSEL2 VSEL1 VSEL0 LNB (V)
0 0 1 0 13.333
0 0 1 1 13.667
0 1 0 1 14.333
0 1 1 1 15.667
1 0 1 1 18.667
1 1 0 0 19.000
1 1 0 1 19.333
1 1 1 0 19.667

Status Registers (I2C™-Compatible Read Register) bit (ENB) via the I2C™ interface. The DIS bit is latched and is
only reset when there are no faults and the A8304 output is turned
The main fault conditions: undervoltage lockout (UVLO), over- back on using the Enable (ENB) bit via the I2C™ interface.
current (OCP), and thermal shutdown (TSD) are all indicated by
setting the relevant bits in the Status register. In all fault cases, The Power Not Good (PNG) and Charge Pump OK (CPOK) bits
after the bit is set, it remains latched until the I2C™ master are set based on the conditions sensed at the LNB output and
has successfully read the A8304, assuming the fault has been VCP pins, respectively. These bits are not latched and, unlike
resolved. the other fault bits, may become reset without an I2C™ read
sequence. The PNG and CPOK bits are continuously updated.
The undervoltage lockout (UVLO) bit indicates either the input
voltage at the VIN pin is too low or the A8304 internal supply There are three methods to detect when the Status register
voltage (VREG) is too low. changes: responding to the interrupt request (IRQ) pin going low,
continuously polling the Status register via the I2C™ interface, or
The Disable bit (DIS) indicates the status of the LNB output. detecting a fault condition external to the A8304 and performing
The DIS is set when either a fault occurs (UVLO, OCP, TSD, or a diagnostic poll of the A8304. In any case, the master should
CPOK) or when the LNB output is turned off using the Enable read and re-read the Status register until the status changes.
Table 3. Status Register Description and IRQ Operation

Bit Name Function Latched? Reset Condition Effect on IRQ Pin
0 DIS LNB output disabled Yes LNB enabled and no faults None
1 CPOK Charge pump OK No VCP > VBOOST + 5V None
2 OCP Overcurrent Yes I2C™ read and fault removed IRQ set low
3 – Not used – – –
4 PNG Power Not Good No LNB voltage within range None
5 – Not used – – –
6 TSD Thermal shutdown Yes I2C™ read and fault removed IRQ set low
7 UVLO VIN or VREG undervoltage Yes I2C™ read and fault removed IRQ set low
Table 4. Status Register Bit Descriptions

Bit Name Description
0 DIS The DIS bit is set to 1 when the A8304 is disabled, (ENB = 0) or there is a fault: UVLO, OCP, CPOK, or TSD.
If this bit is set low, the internal charge pump is not operating correctly (VCP). If the charge pump voltage is
1 CPOK
too low, the LNB output is disabled and the DIS bit is set.
This bit will be set to a 1 if the LNB output current exceeds the overcurrent threshold (ILNB(MAX)) for more than
2 OCP
the overcurrent disable time (tDIS). If the OCP bit is set to 1, then the DIS bit is also set to 1.
3 – Not used.
Set to 1 when the A8304 is enabled and the LNB output voltage is either too low or too high (nominally ±9%
4 PNG from the LNB DAC setting). Set to 0 when the A8304 is enabled and the LNB voltage is within the acceptable
range (nominally ±5% from the LNB DAC setting).
5 – Not used.
The TSD bit is set to 1 if the A8304 has detected an overtemperature condition. If the TSD bit is set to 1, then
6 TSD
the DIS bit is also set to 1.
The UVLO bit is set to 1 if either the voltage at the VIN pin or the voltage at the VREG pin is too low. If the
7 UVLO
UVLO bit is set to 1, then the DIS bit is also set to 1.

Table 5. Component Selection Table

Component Characteristics Manufacturer Device
C1, C4, C7, C8 100 nF, 50 V, X5R or X7R, 0603
Panasonic: EEU-FM1H101B
C2, C5 100 μF, 35 VMIN , ESR < 140 mΩ, IRIPPLE > 550 mA ChemiCon: EKZE500ELL101MHB5D
Nichicon: UHC1V101MPT
C3 220 nF, 10 VMIN, X5R or X7R, 0402 or 0603
TDK: C3216X7R1E105K
Murata: GRM31MR71E105KA01
C6 1.0 μF, 25 VMIN, X5R or X7R, 1206
Taiyo Yuden: TMK316BJ105KL-T
Kemet: C1206C105K3RACTU
C9 10 nF, 50 V, X5R or X7R, 0402 or 0603
C10 220 nF, 50 V, X5R or X7R, 0805
Diodes, Inc: B140HW-7
D1, D2 Schottky diode, 40 V, 1 A, SOD-123
Central Semi: CMMSH1-40
Sanken: SFPB-74
Vishay: B340A-E3/5AT
D3 Schottky diode, 40 V, 3 A, SMA
Diodes, Inc.: B340A-13-F
Central Semi: CMSH3-40MA
ST: LNBTVS6-221S,
D4 TVS, 20 VRM, 32 VCL at 500 A (8/20 μs), 3000 W
Littelfuse: 3.0SMCJ20A
L1 10 μH, ±20%, 3.4 ASAT , 45 mΩ Taiyo Yuden- NR8040T100M
R1 to R5 Determined by VDD, bus capacitance, etc.

Package ES 16-Pin QFN
0.30
3.00 ±0.15
0.90 16 0.50
16
1
A 1
2
3.00 ±0.15 1.70 3.10
1.70
17X D C
SEATING 3.10
0.08 C PLANE
+0.05 C PCB Layout Reference View
0.25 –0.07
0.75 ±0.05
0.50
For reference only, not for tooling use (reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.40±0.10
B A Terminal #1 mark area
1.70 B Exposed thermal pad (reference only, terminal #1
2
identifier appearance at supplier discretion)
1
C Reference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
16
necessary to meet application process requirements and PCB layout
1.70 tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals

I2C™ is a trademark of Philips Semiconductors.

DiSEqC™ is a trademark of Eutelsat S.A.
Copyright ©2012-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.

EN - For pricing and availability in your local country please visit one of the below links:
DE - Informationen zu Preisen und Verfügbarkeit in Ihrem Land erhalten Sie über die unten aufgeführten Links:
FR - Pour connaître les tarifs et la disponibilité dans votre pays, cliquez sur l'un des liens suivants:
A8304SESTR-T
EN DE FR
This Datasheet is presented by Dieses Datenblatt wird vom Cette fiche technique est
the manufacturer Hersteller bereitgestellt présentée par le fabricant
Powered by TCPDF (www.tcpdf.org)

23 Tyga

Uploaded by

Copyright:

Available Formats

23 Tyga

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

23 Tyga

Uploaded by

Copyright:

Available Formats

EN - For pricing and availability in your local country please visit one of the below links:

Single LNB Supply and Control Voltage Regulator

Features and Benefits Description

Functional Block Diagram

For recommended external components, refer to table 5

Features and Benefits (continued)

A8304SESTR-Tb 7 in. reel, 1500 pieces/reel QFN surface mount

Absolute Maximum Ratings

Package Thermal Characteristics*

Allegro MicroSystems, Inc. 2

Device Pin-out Diagram

Allegro MicroSystems, Inc. 3

ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VIN = 10 to 16 V, S̄¯L̄¯Ē¯Ē¯P̄¯ = 1, as noted2; unless noted otherwise

Continued on the next page…

Allegro MicroSystems, Inc. 4

Continued on the next page…

Allegro MicroSystems, Inc. 5

Allegro MicroSystems, Inc. 6

Allegro MicroSystems, Inc. 7

ILNB (MAX) ILNB (MAX)

Allegro MicroSystems, Inc. 8

In-Rush Current Component Selection

Option 1. TMODE = 0, internal tone gated with TONECTRL.

Option 2. TMODE = 1, external tone applied on TONECTRL pin.

Figure 2. Tone generation options

Allegro MicroSystems, Inc. 9

2500 100 μF 1.0 μF/ 25 V (min)

Allegro MicroSystems, Inc. 10

acknowledge acknowledge acknowledge

SDA A6 A5 A4 A3 A2 A1 A0 0 AK RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

(A) Write to Control Register

acknowledge acknowledge acknowledge acknowledge

(B) Read from Status Register

Allegro MicroSystems, Inc. 11

Allegro MicroSystems, Inc. 12

acknowledge acknowledge acknowledge acknowledge

UVLO I2C™ UVLO (typ),

I2C™ Read Cycle

Allegro MicroSystems, Inc. 13

VLNB LNB shorted to GND

I2C™ Read Cycle

IRQ (acƟve low)

I2C™ Read Cycle

Allegro MicroSystems, Inc. 14

tDIS tDIS tDIS

Allegro MicroSystems, Inc. 15

tDIS /4 <tDIS /4 tDIS /4

<tDIS <tDIS <tDIS

LNB LNB LNB LNB LNB LNB LNB LNB

Allegro MicroSystems, Inc. 16

I2C™-Compatible Interface Timing Diagram

tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF

I2C™-Compatible Timing Requirements

Allegro MicroSystems, Inc. 17

Control Register (I2C™-Compatible Write Registers)

Table 1. Control Register 0 Definition, Address: 0000 0000

Table 2. Output Voltage Selection

Allegro MicroSystems, Inc. 18

Table 3. Status Register Description and IRQ Operation