A8305 Datasheet

A8305
Single LNB Supply and Control Voltage Regulator
FEATURES AND BENEFITS DESCRIPTION

▪ Integrated boost MOSFET, current sensing, and compensation Intended for analog and digital satellite receivers, this single
▪ Stable with low-profile ceramic boost capacitors low noise block converter regulator (LNBR) is a monolithic
▪ New 15.67 V output setting to accommodate designs in the linear and switching voltage regulator, specifically designed to
Japan market provide the power and the interface signals to an LNB down
▪ Adjustable LNB output current limit from 250 to 950 mA* converter via coaxial cable. The A8305 requires few external
▫ Covers wide array of application requirements components, with the boost switch and compensation circuitry
▫ Minimizes component sizing to fit each application integrated inside of the device. A high switching frequency is
▫ For startup, reconfiguration, and continuous output chosen to minimize the size of the passive filtering components,
▪ Boost peak current limit scales with LNB current limit further assisting in cost reduction. The high levels of component
setting integration ensure extremely low noise and ripple figures.
▪ 8 programmable LNB output voltage (DAC) levels
▪ LNB overcurrent limiter with shutdown timer The A8305 has been designed for high efficiency, utilizing
▪ Static LNB current limit reliably starts a wide the Allegro™ advanced BCD process. The integrated boost
range of loads switch has been optimized to minimize both switching and
▪ Tracking boost converter minimizes power dissipation static losses. To further enhance efficiency, the voltage drop
▪ LNB transition times configurable by external capacitor across the tracking regulator has been minimized.
▪ Push-pull LNB output stage maintains 13→18 V and For DiSEqC™ communications, a tone control pin is provided
18→13 V transition times, even with highly capacitive loads to gate the internally-generated 22 kHz tone on-and-off.
Continued on the next page… A comprehensive set of fault registers are provided, which
comply with all the common standards, including: overcurrent,
thermal shutdown, undervoltage, and power not good.
PACKAGE: 16-contact QFN (suffix ES)
Furthermore, design methodology and structure ensure the
highest level of robustness against transients and component
failures. The device uses a 2-wire bidirectional serial interface,
compatible with the I2C™ standard, that operates up to 400 kHz.
The A8305 is supplied in a lead (Pb) free package.
3 mm × 3 mm × 0.75 mm
Functional Block Diagram

L1
15 µH D1
VS
C2 C5
2X 4.7 µF C4
3X 10 µF
or 100 nF or
1X 10 µF 4X 4.7 µF
C1
100 nF VIN LX GNDLX BOOST VCP
VREG
Charge D3
Pump A
C3
220 nF
See table 6 for bill of materials Regulator Boost
Converter
fsw
VDD
LNB
Wave VOUT
R1 R2 R3 R4 DAC Voltage Linear
Control Shape Stage
LNB
TCAP D4
D2 C8 C10 C9 A
TONECTRL 100 nF 220 nF 10 nF
TONECTRL fsw
Fault Monitor
SDA
I 2 C™- Clock TCAP
OCP
Compatible C7
PNG Divider 22 kHz 100 nF
SCL Interface TSD Oscillator
UVLO
ADD
IRQ A D3 and D4 are used for surge protection.
ISET
RSET
PAD GND
8305-DS, Rev. 8 September 15, 2021

MCO-0000474
A8305 Single LNB Supply and Control Voltage Regulator
FEATURES AND BENEFITS (continued)

▪ Built-in 22 kHz tone oscillator facilitates DiSEqC™ tone ▪ Extensive protection features: UVLO, OCP, TSD, CPOK
encoding, even at no-load ▪ 2-wire I2C-compatible interface
▪ Tone generation does not require additional external
components
▪ Diagnostic features: PNG *maximum value depends on PCB thermal design
SELECTION GUIDE
Part Number Packing [1] Description
7 in. reel, 1500 pieces/reel ES package, MLP/QFN surface mount
A8305SESTR-T [2]
12 mm carrier tape 3 mm × 3 mm × 0.75 mm nominal height
[1] Contact Allegro for additional packing options.

[2] Leadframe plating 100% matte tin.
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Conditions Rating Unit
Load Supply Voltage, VIN pin VIN 30 V
Internally
Output Current [3] IOUT A
Limited
Output Voltage, BOOST pin –0.3 to 43 V
Output Voltage, LNB pin Surge [4] –1.0 to 43 V
Output Voltage, LX pin –0.3 to 30 V
Output Voltage, VCP pin –0.3 to 48 V
Logic Input Voltage –0.3 to 5.5 V
Logic Output Voltage –0.3 to 5.5 V
Operating Ambient Temperature TA Range S –20 to 85 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
[1] Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the
specified current ratings, or a junction temperature, TJ, of 150°C.
[2] Use Allegro recommended application circuit.
PACKAGE THERMAL CHARACTERISTICS [5]

Package RθJA (°C/W) PCB
ES 47 4-layer
[5] Additional information is available on the Allegro website.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Pinout Diagram
BOOST
GNDLX
VIN
LX
16
15
14
13
VCP 1 12 GND
LNB 2 11 VREG
PAD
NC 3 10 ISET
IRQ 4 9 TCAP
5
6
7
8
SDA
SCL
TONECTRL
ADD
Terminal List Table

Name Number Function
ADD 7 Address select
BOOST 16 Tracking supply voltage to linear regulator
GND 12 Signal ground
GNDLX 15 Boost switch ground
IRQ 4 Interrupt request
ISET 10 Output current limit set via external resistor
LNB 2 Output voltage to satellite dish
LX 14 Inductor drive point
NC 3 No connection
PAD Pad Exposed pad; connect to the ground plane, for thermal dissipation
SCL 5 I2C™-compatible clock input
SDA 6 I2C™-compatible data input/output
TCAP 9 Capacitor for setting the rise and fall time of the LNB output
TONECTRL 8 Gates the 22 kHz tone on-and-off
VCP 1 Gate supply voltage
VIN 13 Supply input voltage
VREG 11 Analog supply
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ELECTRICAL CHARACTERISTICS [1] at TA = 25°C, VIN = 10 to 16 V, as noted [2], unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
GENERAL
VIN = 12 V, IOUT = 50 mA, see table 3 for
Output Voltage Accuracy VOUT –2 – 2 %
DAC settings
VIN = 12 V, VOUT = 13.667 V,
– 38 76 mV
ΔIOUT = 50 to 450 mA
Load Regulation ΔVOUT(Load)
VIN = 12 V, VOUT = 19.000 V,
– 45 90 mV
ΔIOUT = 50 to 450 mA
VIN = 10 to 16 V, VOUT = 13.667 V,
–10 0 10 mV
IOUT = 50 mA
Line Regulation ΔVOUT(Line)
VIN = 10 to 16 V, VOUT = 19.000 V,
–10 0 10 mV
IOUT = 50 mA
IIN(OFF) ENB = 0, VIN = 12 V – 4 – mA
ENB = 1, VIN = 12 V, VOUT = 19 V,
– 11 – mA
Supply Current ILOAD = 0 mA, TONECTRL = 0
IIN(ON)
ENB = 1, VIN = 12 V, VOUT = 19 V,
– 17 – mA
ILOAD = 0 mA, TONECTRL = 1
RDS(on)
Boost Switch On Resistance ISW = 450 mA – 300 – mΩ
BOOST
Switching Frequency fSW 320 352 384 kHz
VBOOST – VLNB, no tone signal,
Linear Regulator Voltage Drop ∆VREG 600 800 1000 mV
ILOAD = 425 mA
TCAP capacitor (C12) charging –13 –10 –7 µA
TCAP Pin Current ITCAP
TCAP capacitor (C12) discharging 7 10 13 µA
For VLNB 13.667 to 19.667 V; C12 = 100 nF,
Output Voltage Rise Time [3] tr(VLNB) – 10 – ms
ILOAD = 500 mA
For VLNB 19.667 to 13.667 V; CLOAD = 100 µF,
Output Voltage Pull-Down Time [3] tf(VLNB) – 25 – ms
ILOAD = 0 mA
ENB = 0, VLNB = 21 V, Boost capacitor fully
– 2 4 mA
charged
ENB = 1, VSEL2,1,0 = 001 (13.667 V),
– 9 15 mA
VLNB = 21 V, TONECTRL = 0 or 1
LNB Sink Current [3] IRLNB
ENB = 1, VSEL2,1,0 = 101 (19.000 V),
– 9 15 mA
VLNB = 21 V, TONECTRL = 0 or 1
ENB = 1, VSEL2,1,0 = 110 (19.667 V),
– 30 40 mA
18.5 V < VLNB <21 V, TONECTRL = 0
LNB Off Current ILNB(Off) VIN = 16 V – – 10 µA
Continued on the next page…
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ELECTRICAL CHARACTERISTICS [1] (continued) at TA = 25°C, VIN = 10 to 16 V, as noted [2], unless noted otherwise
GENERAL (continued)
20 MHz BWL; reference circuit shown in
Application Information section; contact
Ripple and Noise on LNB Output [4] Vrip,n(pp) – 15 – mVPP
Allegro for additional information on
application circuit board design
VREG Voltage VVREG VIN = 10 V 4.97 5.25 5.53 V
ISET Voltage VISET VIN = 10 V 3.4 3.5 3.6 V
VIN = 10 V, VOUT = 13.667 V – 2.28 – V
TCAP Voltage VTCAP
VIN = 10 V, VOUT = 19.000 V – 3.17 – V
PROTECTION CIRCUITRY
RSET = 100 kΩ 250 300 350 mA

Output Overcurrent Limit [5] IOUT(MAX)
RSET = 60.4 kΩ 450 500 550 mA
Overcurrent Disable Time tDIS – 45 – ms

VIN Undervoltage Lockout Threshold VUVLO VIN falling 8.05 8.35 8.65 V
VIN Turn On Threshold VIN(th) VIN rising 8.40 8.70 9.00 V
Undervoltage Hysteresis VUVLOHYS – 350 – mV
RSET = 100 kΩ – 1680 – mA
Boost MOSFET Current Limit IBOOST(MAX)
RSET = 60.4 kΩ – 2600 – mA
Thermal Shutdown Threshold [3] TJ – 165 – °C
Thermal Shutdown Hysteresis [3] ∆TJ – 20 – °C
With respect to VLNB setting; VLNB low,
PNGLOSET 88 91 94 %
PNG set to 1
Power Not Good (Low)
With respect to VLNB setting; VLNB low,
PNGLORESET 92 95 98 %
PNG reset to 0
Power Not Good (Low) Hysteresis PNGLOHYS With respect to VLNB setting – 4 – %
With respect to VLNB setting; VLNB high,
PNGHISET 106 109 112 %
PNG set to 1
Power Not Good (High)
With respect to VLNB setting; VLNB high,
PNGHIRESET 102 105 108 %
PNG reset to 0
Power Not Good (High) Hysteresis PNGHIHYS With respect to VLNB setting – 4 – %
TONE
Amplitude VTONE(PP) ILNB = 0 to 425 mA, CLNB = 750 nF 400 650 900 mVPP
Frequency fTONE ILNB = 0 to 425 mA, CLNB = 750 nF 20 22 24 kHz
Duty Cycle DCTONE ILNB = 0 to 425 mA, CLNB = 750 nF 40 50 60 %

Rise Time tR(TONE) ILNB = 0 to 425 mA, CLNB = 750 nF 5 10 15 μs
Fall Time tF(TONE) ILNB = 0 to 425 mA, CLNB = 750 nF 5 10 15 μs
Continued on the next page…
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ELECTRICAL CHARACTERISTICS [1] (continued) at TA = 25°C, VIN = 10 to 16 V, as noted [2], unless noted otherwise
TONE CONTROL (TONECTRL)
VH 2.0 – – V
Logic Input
VL – – 0.8 V
Input Leakage –1 – 1 μA
I2C™-COMPATIBLE INTERFACE
Logic Input (SDA,SCL) Low Level VSCL(L) – – 0.8 V
Logic Input (SDA,SCL) High Level VSCL(H) 2.0 – – V
Logic Input Hysteresis VI2CIHYS – 150 – mV
Logic Input Current II2CI VI2CI = 0 to 5 V –1 <±1.0 1 µA
Logic Output Voltage SDA and IRQ VOUT(L) ILOAD = 3 mA – – 0.4 V
Logic Output Leakage SDA and IRQ VLKG VOUT = 0 to 5 V – – 10 µA
SCL Clock Frequency fCLK – – 400 kHz
I2C™ ADDRESS SETTING
ADD Voltage for Address 0001,000 Address1 0 – 0.7 V
ADD Voltage for Address 0001,001 Address2 1.3 – 1.7 V
[1] Operation at 16 V may be limited by power loss in the linear regulator.

[2] Indicates specifications guaranteed from 0 ≤ TJ ≤ 125˚CMIN.
[3] Guaranteed by worst case process simulations and system characterization. Not production tested.
[4] LNB output ripple and noise are dependent on component selection and PCB layout. Not production tested.
[5] Current from the LNB output may be limited by the choice of Boost components.
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FUNCTIONAL DESCRIPTION
Protection is reduced below the value of the other outputs, the A8305 output
will auto-recover to their programmed levels.
The A8305 has a wide range of protection features and fault diag-
nostics which are detailed in the Status Register section. Charge Pump. Generates a supply voltage above the internal
tracking regulator output to drive the linear regulator control.
Boost Converter/Linear Regulator
LNB and BOOST Current Limits. The LNB output current limit,
The A8305 solution contains a tracking current-mode boost IOUT(MAX) can be set by connecting a resistor (RSET) from the
converter and linear regulator. The boost converter tracks the ISET pin to GND as shown in the functional block diagram. The
requested LNB voltage to within 800 mV, to minimize power LNB current limit can be set from 300 to 500 mA, correspond-
dissipation. Under conditions where the input voltage, VBOOST , ing to an RSET value of 100 to 60.4 kΩ, respectively. If the LNB
is greater than the output voltage, VLNB, the linear regulator must current limit is exceeded for more than the Overcurrent Disable
drop the differential voltage. When operating in these conditions, Time (tDIS) then the A8305 will be shut down and the OCP bit
care must be taken to ensure that the safe operating temperature set, as shown in figure 1. The LNB output current limit can be set
range of the A8305 is not exceeded. as high as 650 mA (RSET = 46 kΩ) but care should be taken not
to exceed the thermal limit of the package or thermal shutdown
The boost converter operates at 352 kHz typical: 16 times the
(TSD) will occur. The typical LNB output current limit can be set
internal 22 kHz tone frequency. All the loop compensation,
according to the following equation:
current sensing, and slope compensation functions are provided
internally. IOUT(MAX) = 29,925 / RSET ,
The A8305 has internal pulse-by-pulse current limiting on the where IOUT(MAX) is in mA and RSET is in kΩ. If the voltage at
boost converter and DC current limiting on the LNB output to the ISET pin is 0 V (that is, shorted to GND), IOUT(MAX) will
protect the IC against short circuits. When the LNB output is be clamped to a moderately high value (approximately 1.5 A).
shorted, the LNB output current is limited, and if the overcur- Care should be taken to ensure that ISET is not inadvertently
rent condition lasts for more than 45 ms, the LNB output will grounded. If no resistor is connected to the ISET pin (that is, if
be disabled. If this occurs, the A8305 output must be reenabled ISET is open-circuit), IOUT(MAX) will be set to approximately
for normal operation. The system should provide sufficient time 0 A and the A8305 will not support any load (OCP will occur
between successive restarts to limit internal power dissipation; prematurely).
1 s to 2 s is recommended
The BOOST pulse-by-pulse current limit, IBOOST(MAX), is auto-
At extremely light load or no load, if the BOOST voltage tries matically scaled along with the LNB output current limit. The
to exceed the BOOST target voltage, the boost converter oper- typical BOOST current limit is set according to the following
ates with minimum on time. BOOST settling voltage depends on equation:
supply voltage, boost inductance, minimum on time, switching IBOOST(MAX) = 4.7 × IOUT(MAX) + 270 mA ,
frequency, output power and power loss in boost inductor, capaci-
tor and A8305. If the BOOST voltage settles below pulse skip-
where both IBOOST(MAX) and IOUT(MAX) are in mA.
ping threshold (23.7 V), the boost converter continues to operate
with minimum on time. If BOOST voltage tries to exceed 23.7 V, Automatically scaling the BOOST current limit allows the
pulse skipping occurs, and pulse skipping stops when the BOOST designer to choose the lowest possible saturation current of the
voltage drops to 23.4 V. boost inductor, reducing its physical size and PCB area, thus
minimizing cost.
In the case that two or more set top box LNB outputs are con-
nected together by the customer (e.g., with a splitter), it is pos- Slew Rate Control. During either start-up, or when the output
sible that one output could be programmed at a higher voltage voltage at the LNB pin is transitioning, the output voltage rise
than the other. This would cause a voltage on one output that is and fall times can be set by the value of the capacitor connected
higher than its programmed voltage (e.g., 19 V on the output of a from the TCAP pin to GND. Note that during start-up, the
13 V programmed voltage). The output with the highest voltage BOOST pin is pre-charged to the input voltage minus a diode
will effectively turn off the other outputs. As soon as this voltage voltage drop. As a result, the slew rate control for the BOOST
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pin occurs from this voltage. ity to approximately 100 mA. This ensures that the tone signal
meets all specifications, even with no load on the on the LNB
The value of C7 can be calculated using the following formula:
output.
C7 = (ITCAP × 6) / SR ,
where SR is the required slew rate of the LNB output voltage, in ODT (Overcurrent Disable Time)
V/s, and ITCAP is the TCAP pin current specified in the Electrical If the LNB output current exceeds the set output current, for more
Characteristics table. The recommended value for C7 , 100 nF, than 45 ms, then the LNB output will be disabled and the OCP bit
should provide satisfactory operation for most applications. will be set. See figure 1.
The minimum value of C7 is 10 nF. There is no theoretical maxi- Short Circuit Handling
mum value of C7 however too large a value will probably cause
If the LNB output is shorted to ground, the LNB output current
the voltage transition specification to be exceeded. Tone genera-
will be clamped to IOUT(MAX) . If the short circuit condition lasts
tion is unaffected by the value of C7 .
for more than 45 ms, the A8305 will be disabled and the OCP bit
Pull-Down Rate Control. In applications that have to operate at will be set.
very light loads and that require large load capacitances (in the
Auto-Restart
order of tens to hundreds of microfarads), the output linear stage
provides approximately 45 mA of pull-down capability. This After a short circuit condition occurs, the host controller should
ensures that the LNB output voltage is ramped from 18 to 13 V in periodically reenable the A8305 to check if the short circuit
a reasonable amount of time. When the tone is on (TONECTRL has been removed. Consecutive startup attempts should allow
= 1), the output linear stage must increase its pull-down capabil- 1 s to 2 s of delay between restarts.
18.6 to 20.0 V
13.3 to 15.6 V
LNB Output
Voltage
0V
IOUT (MAX) IOUT (MAX)

500 mA
IOUT
0 mA
ENB
PNG
DIS
OCP
Short Circuit
Startup Reconfiguration or Overload
t < tDIS t < tDIS t > tDIS
Figure 1. Startup, Reconfiguration, and Short Circuit operation using RSET = 60.4 kΩ, and
a capacitive load
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In-Rush Current VIN = 12 V, VOUT = 19 V, L = 15 µH, and f = 352 kHz, while the
At start-up or during an LNB reconfiguration event, a tran- “maximum” curve assumes VIN = 9 V, VOUT = 20 V, L = 12 µH,
sient surge current above the normal DC operating level can be and f = 282 kHz.
provided by the A8305. This current increase can be as high as BOOST CAPACITORS
the set output current, for as long as required, up to a maximum The A8305 is designed to operate with three or four, high-quality
of 45 ms. ceramic capacitors on the boost node. Allegro recommends
Tone Generation capacitors that are rated at least 35 V, ±10%, X7R, 1210 size.
A 22 kHz tone is generated internally, and can be controlled on Physically smaller capacitors, like 0603 and 0805, with lower
temperature ratings, like X5R and Z5U, should be avoided. Fig-
and off via the TONECTRL pin as shown in figure 2. Note this
ure 4 can be used to determine the necessary rms current rating
tone can be generated under no-load conditions, and does not
of the boost capacitor given the LNB load current. The “typical”
require the use of an external DiSEqC filter.
curve uses VIN = 12 V, VOUT = 19 V, L = 15 µH, and f = 352 kHz
Component Selection while the “maximum” curve assumes VIN = 9 V, VOUT = 20 V,
L = 12 µH, and f = 282 kHz.
BOOST INDUCTOR
The A8305 is designed to operate with a boost inductor value The nominal boost capacitance should total 18.8 to 30 µF.
of 15 µH +30%/–40% with a DCR less than 75 mΩ. The error Allegro recommends either four 4.7 µF or three 10 µF capacitors,
amplifier loop compensation, current sense gain, and PWM with the characteristics shown in table 1. If tolerance, tempera-
slope compensation were chosen for this value of inductor. The ture, and DC bias effects are considered, the capacitance must
boost inductor must be able to support the peak currents required total at least 13 µF. The DC bias effect is very significant on
to maintain the maximum LNB output current without saturat- ceramic capacitors with lower voltage ratings, smaller packages,
ing. Figure 3 can be used to determine the peak current in the or wider temperature characteristics. For example, a 10 µF, 25 V,
inductor given the LNB load current. The “typical” curve uses 1206, X5R capacitor can lose 85% of its value at 20 VDC bias. If
the total boost capacitance becomes less than 12 µF, the converter
TONECTRL
will have reduced gain and phase margins. If the total boost
capacitance becomes less than 7.5 µF, then the converter will
Tone very likely be unstable.
LNB (V)
(LNB Ref) Two possible ceramic based capacitor solutions have been pre-
sented. Other capacitor combinations are certainly possible, such
Figure 2. Internal tone, gated by TONECTRL pin as a very low ESR electrolytic capacitor in parallel with several
3250 1100
3000 1000
2750
900
2500
IBOOST (mA peak)
IBOOST (mA rms)
2250 800
Maximum
2000 700
Maximum
1750 600
1500
500
1250
400
1000 Typical
Typical
750 300
500 200
100 150 200 250 300 350 400 450 500 550 600 650 100 150 200 250 300 350 400 450 500 550 600 650
ILNB (mA) ILNB (mA)
Figure 3. Boost inductor peak current versus ILNB for the A8305 Figure 4. Boost capacitor rms current versus ILNB for the A8305
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microfarads of ceramic capacitance. However, there are two SURGE COMPONENTS

critical requirements that must be satisfied: 1) the zero formed by The circuit shown on page 1 of this datasheet includes D3 and
the electrolytic capacitor and its ESR should be at least 1 decade D4 for surge protection. Component recommendations for D3
higher than the 0 dB crossover of the boost loop (typically around and D4 are given in the bill-of-materials at the end of this data-
25 kHz), and 2) the ceramic capacitors must eliminate the high sheet. This configuration and these components have success-
frequency switching spikes/edges in the boost voltage, or the fully passed surge tests up to ±1000 V/500 A, with a 1.2/50 µs
LNB output noise will be too high. − 8/20 µs combination wave. Every application will have its
own surge requirements and the surge solution can be changed.
BOOST FILTERING AND LNB NOISE
However, Allegro strongly recommends incorporating a form of
The LNB output noise depends on the amount of high-frequency
surge protection to prevent any pin of the A8305 from exceeding
noise at the BOOST pin. To minimize the high-frequency noise at
its Absolute Maximum voltage ratings shown in this datasheet.
the BOOST pin, the ceramic capacitors should be placed as close
as possible to the BOOST pin.
Table 1. Recommended Boost Capacitor Characteristics

Temperature Total Capacitance at –10%
Quantity of Value Tolerance Rating Coefficient of and 20 VDC Bias
Capacitors (µF) (%) (V) Capacitance Size (µF)
4 4.7 ±10 50 X7R 1210 14.0
3 10 ±10 35 X7R 1210 18.6
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I2C™-Compatible Interface signal “good transmission” to the slave. The receiver (either the
master or the slave) should set the AK bit high (AK = 1 or NAK)
The I2C™ interface is used to access the internal Control and for the ninth SCL pulse if eight bits of data are not received suc-
Status registers of the A8305. This is a serial interface that uses cessfully.
two lines, serial clock (SCL) and serial data (SDA), connected to
AK Bit During a Write Sequence. When the master sends con-
a positive supply voltage via a current source or a pull-up resis-
trol data (writes) to the A8305 there are three instances where AK
tor. Data is exchanged between a microcontroller (master) and
bits are toggled by the A8305. First, the A8305 uses the AK bit
the A8305 (slave). The master always generates the SCL signal.
to indicate reception of a valid seven-bit chip address plus a read/
Either the master or the slave can generate the SDA signal. The
write bit (R/W = 0 for write). Second, the A8305 uses the AK bit
SDA and SCL lines from the A8305 are open-drain signals so
to indicate reception of a valid eight-bit Control register address.
multiple devices may be connected to the I2C™ bus. When the
Third, the A8305 uses the AK bit to indicate reception of eight
bus is free, both the SDA and the SCL lines are high.
bits of control data. This protocol is shown in figure 5(A).
SDA and SCL Signals. SDA can only be changed while SCL is
AK Bit During a Read Sequence. When the master reads status
low. SDA must be stable while SCL is high. However, an excep-
data from the A8305 there are four instances where AK bits are
tion is made when the I2C™ Start or Stop condition is encoun-
sent–three sent by the A8305 and one sent by the master. First,
tered. See the I2C™ Communication section for further details.
the A8305 uses the AK bit to indicate reception of a valid seven-
Acknowledge (AK) Bit. The Acknowledge (AK) bit indicates a bit chip address plus a read/write bit (R/W = 0 for write). Sec-
“good transmission” and can be used two ways. First, if the slave ond, the A8305 uses the AK bit to indicate reception of a valid
has successfully received eight bits of either an address or control eight-bit status register address. Third, the A8305 uses the AK
data, it will pull the SDA line low (AK = 0) for the ninth SCL bit to indicate reception of a valid seven-bit chip address plus a
pulse to signal “good transmission” to the master. Second, if the read/write bit (R/W = 1 for read). Finally, the master uses the AK
master has successfully received eight bits of status data from the bit to indicate receiving eight bits of status data from the A8305.
A8305, it will pull the SDA line low for the ninth SCL pulse to This protocol is shown in figure 5(B).
acknowledge acknowledge acknowledge

from LNBR (slave) from LNBR (slave) from LNBR (slave)
Start Chip Address W Control Register Address Control Data Stop
SDA A6 A5 A4 A3 A2 A1 A0 0 AK RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
(A) Write to Control Register
acknowledge acknowledge acknowledge acknowledge

from LNBR (slave) from LNBR (slave) from LNBR (slave) from master
Start Chip Address W Status Register Address Stop Start Chip Address R Status Data Stop
SDA A6 A5 A4 A3 A2 A1 A0 0 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK A6 A5 A4 A3 A2 A1 A0 1 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
(B) Read from Status Register
Figure 5. I2C™ Interface Read and Write Sequences. (A) for the I2C™ Write cycle and (B) for the I2C™ Read cycle
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I2C™ Communications I2C™ Read Cycle Description. Reading from the A8305 Status
register requires transmission of a total of 36 bits–four 8-bit
I2C™ Start and Stop Conditions. The I2C™ Start condition is bytes of data plus an Acknowledge bit after each byte. Reading
defined by a negative edge on the SDA line while SCL is high- the A8305 Status register requires a chip address with R/W = 0, a
Conversely, the Stop condition is defined by a positive edge on Status register address, an I2C™ Stop condition, an I2C™ Start
the SDA line while SCL is high. The Start and Stop conditions condition, a “repeated” chip address with R/W=1, and finally the
are shown in figure 5. It is possible for the Start or Stop condition status data from the A8305. Reading from the A8305 Status regis-
to occur at any time during a data transfer. If either a Start or Stop ter is shown in figure 5(B).
condition is encountered during a data transfer, the A8305 will
• This 9-bit Chip Address cycle is identical to the Chip Ad-
respond by resetting the data transfer sequence.
dress cycle previously described for the Write Control regis-
I2C™ Write Cycle Description. Writing to the A8305 Control ter sequence. It consists of A6 to A0, plus one read/write bit
register requires transmission of a total of 27 bits–three 8-bit (R/W = 0) from the master, followed by an Acknowledge bit
bytes of data plus an Acknowledge bit after each byte. Writing to from the slave and finally an I2C™ Stop condition.
the A8305 Control register is shown in figure 5(A). Writing to the • The Status Register Address cycle consists of a total of nine
A8305 Control register requires a chip address with R/W = 0, a bits–eight bits of Status register address (RS7 to RS0) from the
Control register address, and the control data, as follows: master, followed by an Acknowledge bit from the slave. The
• The Chip Address cycle consists of a total of nine bits– Status register address must be transmitted MSB (RS7) first.
seven bits of chip address (A6 to A0) plus one read/write bit The A8305 only has one Status register, so the Status register
(R/W = 0) to indicate a write from the master followed by an address is fixed at 00000000.
Acknowledge bit (AK = 0 for reception of a valid chip address) • The “Repeated” Chip Address cycle begins with an I2C™
from the slave. The chip address must be transmitted MSB Start condition followed by a 9-bit cycle identical to the Chip
(A6) first. The first five bits of the A8305 chip address (A6 to Address cycle previously described for the Write Control
A2) are fixed as 00010. The remaining two bits (A1 and A0) Register sequence. It consists of A6 to A0, plus one read/write
are used to select one of four possible A8305 chip addresses. bit (R/W = 1) from the master, followed by an Acknowledge bit
The DC voltage on the ADD pin programs the chip address. from the slave.
See the Electrical Characteristics table for the ADD pin volt- • The Status Data cycle consists of a total of nine bits–eight bits
ages and the corresponding chip addresses. of status data (RD7 to RD0) from the slave, followed by an
• The Control Register Address cycle consists of a total of nine Acknowledge bit from the master. The status data is transmit-
bits–eight bits of control register address (RC7 to RC0) from ted MSB (RD7) first. The Status register bits are identified in
the master followed by an Acknowledge bit from the slave. The the Status Register section of this data sheet.
Control register address must be transmitted MSB (RC7) first.
The A8305 only has one Control register so the Control register Interrupt (IRQ) and Fault Clearing
address is fixed as 00000000.
• The Control Data cycle consists of a total of nine bits–eight The A8305 provides an interrupt request pin (IRQ), which is an
bits of control data (D7 to D0) from the master followed by open-drain, active low output. This output may be connected to
an Acknowledge bit from the slave. The control data must be a common IRQ line with a suitable external pull-up resistor and
transmitted MSB first (D7). The Control register bits are identi- can be used with other I2C™ compatible devices to request atten-
fied in the Control Registers section of this datasheet. tion from the master controller.
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The IRQ output becomes active (logic low) when the A8305 the UVLO fault before the A8305 can be re-enabled. A detailed
recognizes a fault condition. The fault conditions that will force timing diagram is shown in figure 7(A).
IRQ active include undervoltage lockout (UVLO), overcurrent • The second method uses I2C address setting (Address 1). In
protection (OCP), and thermal shutdown (TSD). The UVLO, this method the I2C port is active when VIN is above the I2C
OCP, and TSD faults are latched in the Status register and will UVLO (6 V when VIN is rising). IRQ transitions low when
not be unlatched until the A8305 Status register is successfully VIN goes above I2C UVLO (6 V, VIN rising), and the I2C Read
transmitted to the master controller (an AK bit must be received
cycle resets IRQ to logic high even if VIN is below UVLO.
from the master). See the description in the Status Register sec-
Even though IRQ is cleared below UVLO, one more Read
tion and figure 6 for further details.
cycle is required after VIN goes above UVLO, to re-enable the
The A8305 IRQ response to VIN(UVLO) is controlled by the I2C A8305. While VIN is falling, IRQ transitions low when VIN
address setting. The A8305 has two methods to control the IRQ goes below UVLO, and the I2C Read cycle resets IRQ to logic
for UVLO fault: high. A detailed timing diagram is shown in figure 7(B).
• The first method uses the I2C address setting (Address 2,
Address 3, or Address 4). In this method while VIN is below When the master device receives an interrupt, it should address
8.70 V (typ), the A8305 is disabled and the I2C port is inactive. all slaves connected to the interrupt line in sequence and read
After VIN rises above 8.70 V (typ), the I2C port becomes active the status register of each to determine which device is request-
and the IRQ pin is pulled low. An I2C Read cycle is required to ing attention. As shown in figure 6, the A8305 latches all condi-
report and clear the UVLO fault and set the IRQ pin to a logic tions in the Status register and sets the IRQ to logic low when
high before the A8305 can be enabled. If a brown-out occurs, a UVLO, OCP, or TSD event occurs. The IRQ bit is reset to
such that VIN drops below 8.35 V (typ), the A8305 will be logic high and the Status register is unlatched when the master
disabled and the I2C port will become inactive (note that the acknowledges the status data from the A8305 (an AK bit must be
IRQ pin will remain high during this time because the A8305 is received from the master).
disabled). After VIN rises above 8.70 V (typ) the I2C port reac-
tivates and the IRQ pin is pulled low to report that a brown-out The disable (DIS) and Power Not Good (PNG) conditions do not
had occurred. An I2C Read cycle is required to report and clear cause an interrupt and are not latched in the Status register.
acknowledge acknowledge acknowledge acknowledge

from LNBR (slave) from LNBR (slave) from LNBR (slave) from master
Start Chip Address W Status Register Address Stop Start Chip Address R Status Data Stop
SDA A6 A5 A4 A3 A2 A1 A0 0 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK A6 A5 A4 A3 A2 A1 A0 1 AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
IRQ STATUS
register
FAULT event, IRQ set low, Status register latched unlatched
IRQ reset
Figure 6. Fault, IRQ, and Status Register Timing. When a UVLO, OCP, or TSD event occurs, the IRQ bit is set low
and the Status register is latched. The IRQ bit is reset to high when the A8305 acknowledges it is being read. The
Status register is unlatched when the master acknowledges the status data from the A8305.
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UVLO
Thresholds 8.70 V
VIN 8.35 V
Brown Out
LNB Output
I2C Read Cycle
IRQ (active low)

I2C I2C
Inactive Inactive
ENABLE Bit
(via I2C)
t
7(A). IRQ and Fault Clearing in Response to Under Voltage at VIN (UVLO), with I2C address set to (Address 2, Address 3, or
Address 4). In this method, while VIN is below 8.70 V (typ), the A8305 is disabled and the I2C port is inactive. After VIN rises
above 8.70 V (typ), the I2C port becomes active and the IRQ pin is pulled low. An I2C Read cycle is required, to report and clear
the UVLO fault and set the IRQ pin to a logic high, before the A8305 can be enabled. If a brown-out occurs, such that VIN drops
below 8.35 V (typ), the A8305 will be disabled and the I2C port will become inactive (note that the IRQ pin will remain high during
this time because the A8305 is disabled). After VIN rises above 8.70 V (typ) the I2C port reactivates and the IRQ pin is pulled low
to report that a brown-out had occurred. An I2C Read cycle is required to report and clear the UVLO fault before the A8305 can be
re-enabled.
UVLO I2C UVLO (typ),

Thresholds rising: 6 V, falling: 4.2 V
VIN
LNB Output
I2C Read Cycle
I 2C I2C
Inactive Inactive
IRQ (active low)
ENABLE Bit
(via I2C)
t
7(B). IRQ and Fault Clearing in Response to Under Voltage at VIN (UVLO), with I2C address set to (Address 1). In this method, the
I2C port is active when VIN is above I2C UVLO (6 V when VIN is rising). IRQ transitions low when VIN goes above I2C UVLO (6 V,
VIN rising), and the I2C Read cycle resets IRQ to logic high even if VIN is below UVLO. Even though IRQ is cleared below UVLO,
one more Read cycle is required after VIN goes above UVLO, to re-enable the A8305. While VIN is falling, IRQ transitions low when
VIN goes below UVLO, and the I2C Read cycle resets IRQ to logic high.
Figure 7. IRQ and Fault Clearing in Response to Under Voltage at VIN (UVLO), showing the alternate methods, set by selection of I2C address
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45 ms 45 ms
ISET
LNB IOUT
LNB VOUT LNB shorted to GND
I2C Read Cycle
IRQ (active low)
Enable
(ENB bit, via I2C)
Figure 8. IRQ and Fault Clearing in Response to Overcurrent (OCP). If the LNB output is grounded for more than
45 ms, the LNB output will be shut off, an overcurrent fault (OCP) will be latched in the Status Register, and the IRQ
pin will transition low. After an OCP fault, the LNB output does not respond to the Enable (ENB) bit until an I2C Read
cycle is executed to report and clear the OCP fault. After a successful I2C Read, the IRQ pin transitions high and the
A8305 can be re-enabled, provided the LNB output is no longer grounded.
TSD
Threshold 165°C
TJ 145°C
Loss of cooling
or STB overload
LNB O/P
I2C Read Cycle
IRQ
(active low)
TSD Bit
(via I2C)
ENABLE Bit
(via I2C)
t
Figure 9. IRQ and Fault Clearing in Response to Thermal Shutdown (TSD). If the LNB junction temperature rises
above 165°C (typ), the LNB output will be shut off, a thermal shutdown fault (TSD) will be latched in the Status
Register, and the IRQ pin will transition low. After a TSD fault, the LNB output does not respond to the Enable
(ENB) bit until an I2C Read cycle is executed to report and clear the TSD fault. After a successful I2C Read, the
IRQ pin transitions high and the A8305 can be re-enabled, provided the junction temperature is below 145°C (typ).
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I2C™-Compatible Interface Timing Diagram

tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF
SDA
SCL
tLOW tHIGH
I2C™-Compatible Timing Requirements

Characteristics Symbol Min. Typ. Max. Unit
Bus Free Time Between Stop/Start tBUF 1.3 – – µs
Hold Time Start Condition tHD:STA 0.6 – – µs
Setup Time for Start Condition tSU:STA 0.6 – – µs
SCL Low Time tLOW 1.3 – – µs
SCL High Time tHIGH 0.6 – – µs
Data Setup Time tSU:DAT 100 – – ns
Data Hold Time* tHD:DAT 0 – 900 ns
Setup Time for Stop Condition tSU:STO 0.6 – – µs
Output Fall Time (VfI2COut(H) to VfI2COut(L)) tfI2COut – – 250 ns
*For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA
signal in order to bridge the undefined region of the SCL signal falling edge.
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Control Registers (I2C™-Compatible Write Register)

All main functions of the A8305 are controlled through the I2C™
compatible interface via the 8-bit Control register. Table 2 shows
the functionality and bit definitions of the Control register. At
power-up, the Control register is initialized to all 0s.
Table 2. Control Register Definition

Bit Name Function Description
0 VSEL0 The available voltages provide levels for all the common
LNB output voltage control standards plus the ability to add line compensation.
1 VSEL1
VSEL0 is the LSB and VSEL2 is the MSB to the internal
See Table 3 for available output voltage selections DAC.
2 VSEL2
0: Disable LNB Output

3 ENB Turns the LNB output on or off.
1: Enable LNB Output
4 –
5 –
Set to 0 Unused
6 –
7 –
Table 3. Output Voltage Selection

VSEL2 VSEL1 VSEL0 LNB (V)
0 0 0 13.333
0 0 1 13.667
0 1 0 14.333
0 1 1 15.667
1 0 0 18.667
1 0 1 19.000
1 1 0 19.667
1 1 1 20.000
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Status Registers (I2C™-Compatible Read Register) bit (ENB) via the I2C™ interface. The DIS bit is latched and is
only reset when there are no faults and the A8305 output is turned
The main fault conditions, undervoltage lockout (UVLO),
on again using the Enable (ENB) bit via the I2C™ interface. The
overcurrent (OCP), and thermal shutdown (TSD), are all indi-
Power Not Good (PNG) and Charge Pump OK (CPOK) bits are
cated by setting the relevant bits in the Status register. In all fault
set based on the conditions sensed at the LNB output and VCP
cases, after the bit is set, it remains latched until the I2C™ master
pins, respectively. These bits are not latched and, unlike the other
has successfully read the A8305, assuming the fault has been
fault bits, may become reset without an I2C™ read sequence. The
resolved.
PNG and CPOK bits are continuously updated.
The undervoltage lockout (UVLO) bit indicates either the input
There are three methods to detect when the Status register
voltage at the VIN pin is too low or the A8305 internal supply
changes: responding to the interrupt request (IRQ) pin going low,
voltage (VREG) is too low.
continuously polling the Status register via the I2C™ interface,
The Disable bit (DIS) indicates the status of the LNB output. The or detecting a fault condition external to the A8305 and perform-
DIS bitis set when either a fault occurs (UVLO, OCP, TSD, or ing a diagnostic poll of the A8305. In any case, the master should
CPOK) or when the LNB output is turned off using the Enable read and re-read the Status register until the status changes.
Table 4. Status Register Description and IRQ Operation

Bit Name Function Latched? Reset Condition Effect on IRQ Pin
0 DIS LNB output disabled Yes LNB enabled and no faults None
1 CPOK Charge pump OK No VCP > VBOOST + 5V None
2 OCP Overcurrent Yes I2C™ READ and ILOAD < ISET IRQ set low
3 TRIMS Trim bits locked Yes None None
4 PNG Power Not Good No LNB voltage within range None
5 – Not used – – –
6 TSD Thermal shutdown Yes I2C™ READ and TJ < 145°C IRQ set low
7 UVLO VIN or VREG undervoltage Yes I2C™ READ and VIN > 9.0 V IRQ set low
Table 5. Status Register Bit Descriptions

Bit Name Description
0 DIS The DIS bit is set to 1 when the A8305 is disabled, (ENB = 0) or there is a fault: UVLO, OCP, CPOK, or TSD.
1 CPOK If this bit is set low, the internal charge pump is not operating correctly (VCP). If the charge pump voltage is
too low, the LNB output is disabled and the DIS bit is set.
2 OCP This bit will be set to a 1 if the LNB output current exceeds the overcurrent threshold (IOUT(MAX)) for more than
the overcurrent disable time (tDIS). If the OCP bit is set to 1, then the DIS bit is also set to 1.
3 TRIMS Factory use only.
4 PNG Set to 1 when the A8305 is enabled and the LNB output voltage is either too low or too high (nominally ±9%
from the LNB DAC setting). Set to 0 when the A8305 is enabled and the LNB voltage is within the acceptable
range (nominally ±5% from the LNB DAC setting).
5 – Not used
6 TSD The TSD bit is set to 1 if the A8305 has detected an overtemperature condition. If the TSD bit is set to 1, then
the DIS bit is also set to 1.
7 UVLO The UVLO bit is set to 1 if either the voltage at the VIN pin or the voltage at the VREG pin is too low. If the
UVLO bit is set to 1, then the DIS bit is also set to 1.
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APPLICATION INFORMATION
Table 6. Component Selection Table for Functional Block Diagram

Component Characteristics Manufacturer Device
C1, C4, C7, C8 100 nF, 50 V, X5R or X7R, 0603
2X 4.7 µF, or
C2
1X 10 µF, 25 V, X5R or X7R, 1206
C3 220 nF, 10 VMIN, X5R or X7R, 0402 or 0603
Murata: GRM32ER71H475KA88
4X 4.7 µF, ±10%, 50 V, X7R, 1210 Taiyo Yudan: UMK325B7475KM
C5 AVX: 12105C475KAT2A
3X 10 µF, ±10%, 35 V, X7R, 1210 Murata: GCM32ER71E106K
C9 10 nF, 50 V, X5R or X7R, 0402 or 0603
C10 220 nF, 50 V, X5R or X7R, 0805
Diodes, Inc: B140HW-7
D1, D2 Schottky diode, 40 V, 1 A, SOD-123
Central Semi: CMMSH1-40
Sanken: SFPB-74
Vishay: B340A-E3/5AT
D3 Schottky diode, 40 V, 3 A, SMA
Diodes, Inc.: B340A-13-F
Central Semi: CMSH3-40MA
ST: LNBTVS6-221S,
D4 TVS, 20 VRM, 32 VCL at 500 A (8/20 µs), 3000 W
Littelfuse: 3.0SMCJ20A
L1 15 μH Cooper Bussman DR1030-150-R
R1 to R4 Determined by VDD, bus capacitance, etc.
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955 Perimeter Road
L1 D1 D3
B340A
PL1 10uH B140
Vin LX 1 2 VB 2 1
C A A C
Boost
C2 TP11
4.7uF LX
1206 TP2
VIN 25V, X7R C5 Boost
3*10uF
C4
Vcp 100nF
VCP
5V
14
15
16
1
TP1
Vin
R1 R2 R3 R4
VCP
BOOST
LX
GNDLX
C1
100nF
13
VIN
SDA
TP6
SDA SDA 6
SDA
A8305 J1
TP3 COAX-F
TP7 LNB
SCL SCL 5 U1 2 LNB 1
SCL SCL LNB
2
TP8
IRQ IRQ 4 D2 C8 C10 C9
C A
C A
IRQ IRQ B140 100nF 220nF 10nF
2
3
4
5
0805 pads
TP9
TONECNTL TONECNTL 8
1
TONECNTL TONECNTL
G2 D4
GND LNBTVS6-221S
GND
ADD 7 9 TCAP
ADD TCAP
TP15 TP4
ADD Tcap C7
100nF
GND GND
0 11 Vreg
PAD VREG
TP5
VREG C3
220nF
GND
ISET
GND
NC
PGND and GND form a single point ground at U 1 GND

3
12
10
RSET
75.6k
GND
GND
GND
See table 7 for bill of materials
Schematic 1. A8305 application circuit for LNB output currents < 350 mA.
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Table 7. Component Selection Table for Application Circuit Schematic 1

Component Characteristics Manufacturer Device
C1, C4, C7, C8 100 nF, 50 V, X5R or X7R, 0603
C2 4.7 µF, 25 V, 10%, X7R
C3 220 nF, 10 VMIN, X5R or X7R, 0402 or 0603
Murata: GRM32ER71H475KA88
4X 4.7 µF, ±10%, 50 V, X7R, 1210 Taiyo Yudan: UMK325B7475KM
C5 AVX: 12105C475KAT2A
3X 10 µF, ±10%, 35 V, X7R, 1210 Murata: GCM32ER71E106K
C9 10 nF, 50 V, X5R or X7R, 0402 or 0603
C10 220 nF, 50 V, X5R or X7R, 0805
Diodes, Inc: B140HW-7
D1, D2 Schottky diode, 40 V, 1 A, SOD-123
Central Semi: CMMSH1-40
Sanken: SFPB-74
Vishay: B340A-E3/5AT
D3 Schottky diode, 40 V, 3 A, SMA
Diodes, Inc.: B340A-13-F
Central Semi: CMSH3-40MA
ST: LNBTVS6-221S,
D4 TVS, 20 VRM, 32 VCL at 500 A (8/20 µs), 3000 W
Littelfuse: 3.0SMCJ20A
L1 10 μH Taiyo Yuden: NRS8040T100MJGJ
R1 to R4 Determined by VDD, bus capacitance, etc.
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955 Perimeter Road
Package ES 16-Pin QFN
For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000222 Rev. 4 or JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead conﬁguration at supplier discretion within limits shown
0.30
3.00 BSC
0.90 16 0.50
16
1
A 1
2
2×
3.00 BSC 1.70 3.10

0.15 C
0.15 C 2×
1.70
17× D C
3.10
0.08 C SEATING
+0.05 PLANE C PCB Layout Reference View
0.25 –0.07
0.75 ±0.05
0.50 BSC +0.03
0.02 –0.02
0.40 ±0.10
B
1
1.70 ±0.10 XXXX
2
Date Code
1 Lot Number
16
1.70 ±0.10
E Standard Branding Reference View
A Terminal #1 mark area. Lines 1, 2, 3 = 4 characters
B Exposed thermal pad (reference only, terminal #1 Line 1: Part Number

identifier appearance at supplier discretion). Line 2: 4 digit Date Code
C Reference land pattern layout (reference IPC7351 Line 3: Characters 5, 6, 7, 8 of
QFN50P300X300X80-17W4M); Assembly Lot Number
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout Pin 1 Dot top left
tolerances; when mounting on a multilayer PCB, thermal vias at the Center align
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5).
D Coplanarity includes exposed thermal pad and terminals.
E Branding scale and appearance at supplier discretion.
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Revision History
Number Date Description
4 July 9, 2018 Minor editorial updates
5 February 8, 2019 Product status changed to Pre-End-of-Life
6 July 1, 2019 Product status changed to Last Time Buy
7 September 19, 2019 Product status changed to active
8 September 15, 2021 Updated package drawing (page 22)
I2C™ is a trademark of Philips Semiconductors.

DiSEqC™ is a trademark of Eutelsat S.A.
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

23
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A8305

Single LNB Supply and Control Voltage Regulator

FEATURES AND BENEFITS DESCRIPTION

Functional Block Diagram

IRQ A D3 and D4 are used for surge protection.

8305-DS, Rev. 8 September 15, 2021

FEATURES AND BENEFITS (continued)

[1] Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL CHARACTERISTICS [5]

Terminal List Table

Continued on the next page…

RSET = 100 kΩ 250 300 350 mA

Overcurrent Disable Time tDIS – 45 – ms

Frequency fTONE ILNB = 0 to 425 mA, CLNB = 750 nF 20 22 24 kHz

Duty Cycle DCTONE ILNB = 0 to 425 mA, CLNB = 750 nF 40 50 60 %

Continued on the next page…

[1] Operation at 16 V may be limited by power loss in the linear regulator.

IOUT (MAX) IOUT (MAX)

IBOOST (mA rms)

microfarads of ceramic capacitance. However, there are two SURGE COMPONENTS

Table 1. Recommended Boost Capacitor Characteristics

acknowledge acknowledge acknowledge

SDA A6 A5 A4 A3 A2 A1 A0 0 AK RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

(A) Write to Control Register

acknowledge acknowledge acknowledge acknowledge

(B) Read from Status Register

acknowledge acknowledge acknowledge acknowledge

I2C Read Cycle

IRQ (active low)

UVLO I2C UVLO (typ),

I2C Read Cycle

LNB VOUT LNB shorted to GND

I2C Read Cycle

IRQ (active low)

I2C Read Cycle

I2C™-Compatible Interface Timing Diagram

I2C™-Compatible Timing Requirements

Control Registers (I2C™-Compatible Write Register)

Table 2. Control Register Definition

0: Disable LNB Output

Table 3. Output Voltage Selection

Table 4. Status Register Description and IRQ Operation

Table 5. Status Register Bit Descriptions

Table 6. Component Selection Table for Functional Block Diagram

PGND and GND form a single point ground at U 1 GND

See table 7 for bill of materials

Table 7. Component Selection Table for Application Circuit Schematic 1

Package ES 16-Pin QFN

For Reference Only – Not for Tooling Use

3.00 BSC 1.70 3.10

A Terminal #1 mark area. Lines 1, 2, 3 = 4 characters

B Exposed thermal pad (reference only, terminal #1 Line 1: Part Number

E Branding scale and appearance at supplier discretion.

I2C™ is a trademark of Philips Semiconductors.

For the latest version of this document, visit our website:

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