AMP Chap3 Synchronous Design Using VHDL SP2016

DTR 8431–Architecture des
Microprocesseurs et Open Core
Chapter 3
Synchronous Design using VHDL
Dr. Mohamad Mroué

Presentation Progress
1. Synchronous sequential systems

2. Designing Finite-State Machines (FSM) using VHDL
Dr. Mroué DTR 8431 – Architecture des Microprocesseurs et Open Core Chapter 3 1

Synchronous sequential systems
 Most sequential systems are synchronous; that is, they

are controlled by a clock.
 Almost all large digital systems have some concept of

state built into them. In other words, the outputs of a
system depend on past values of its inputs as well as
the present values. Past input values either are stored
explicitly or cause the system to enter a particular state.
 Such systems are known as sequential systems, as

opposed to combinational systems.
 A general model of a sequential system is shown in the

following Figure.
 The present state of the system is held in the registers – hence
the outputs of the registers give the value of the present state and
the inputs to the registers will be the next state.
 The present state of the system can be updated either as soon as

the next state changes, in which case the system is said to be
asynchronous, or only when a clock signal changes, which is
synchronous behavior.
D Latch
 A latch is a level-sensitive memory device
Edge-triggered D flip-flop with asynchronous Set and Reset
 A flip-flop is an edge-triggered device
Rising_edge and falling_edge functions
 The standard logic package provides a rising_edge and a

falling_edge function. It is strongly suggested that these
functions be used to detect clock edges.
Synchronous set and reset and clock enable
 Flip-flops may have synchronous set and reset functions as well

as, or instead of, asynchronous set or reset inputs.
 A synchronous set or reset takes effect only at a clock edge.

Thus a VHDL model of such a function must include a check on
the set or reset input after the clock edge has been checked.
 It is not necessary to include synchronous set or reset inputs in

the process sensitivity list because the process is activated only
at a clock edge.
 Similarly, a flip-flop with a clock enable signal may be modeled

with that signal checked after the edge detection
Registers and shift registers
 Multiple bit register

– A D flip-flop is a one-bit register. Thus if we want a register
with more than one bit, we simply need to define a set of D
flip-flops using vectors:
 Shift registers
– An extension of the above model of a register includes the
ability to shift the bits of the register to the left or to the right.
– For example, a sequence of bits can be converted into a word

by shifting the bits into a register, and moving the bits along
at each clock edge.
– After a sufficient number of clock edges, the bits of the word

are available as a single word. This is known as a serial-in,
parallel-out (SIPO) register.
 Shift registers
 Shift registers
– A more general shift register is the universal shift register.
This can shift bits to the left or to the right, and can load an
entire new word in parallel. To do this, two control bits are
needed.
Counters
 Binary counter
– A binary counter is a counter in the intuitive sense. It consists

of a register of a number of D flip-flops, the content of which
is the binary representation of a decimal number.
– We can easily model this in VHDL, using the

numeric_std package to provide the ‘+’ operator.
Counters
 Binary counter
Counters
 Binary counter
– Note that the contents of the counter are stored as a variable
inside a process. The variable has type unsigned (allowing
the + operator to be used).
– The contents of the counter are assigned to a signal and

converted into a std_logic_vector. Note that the +
operator does not generate a carry out.
– Thus when the counter has reached its maximum integer

value (all 1s) the next clock edge will cause the counter to
‘wrap round’ and its next value will be zero (all 0s).
Counters - Examples
Counters - Examples
Counters - Examples
 A modulo-8 Counter with an Asynchronous RESET
Counters - Examples
 A modulo-8 Counter with a Synchronous RESET
Up-Down Counter - Example
INTEGER vs. STD_LOGIC_VECTOR
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port ( x, y : in std_logic_vector (7 downto 0);
z : out std_logic_vector (7 downto 0));
end prj1;
architecture add of adder is
begin
z <= x + y;
end add;
ERROR: can't determine definition of operator ""+"" -- found 0 possible

definitions
 This problem can be solved by adding the following

Use ieee.std_logic_unsigned.all;
and the operator « + » will be recognized.
 Convert from integer c to std_logic_vector z :
process (c) is
variable tmp : integer range 0 to 255;
begin
tmp:= c;
for i in 0 to 7 loop
if (tmp rem 2 = 0) then z(i)<='0‘;
else z(i)<='1‘; end if;
tmp := tmp/2;
end loop;
end process;
 Convert from std_logic_vector x to integer a

process (x) is
variable sum : integer range 0 to 255;
begin
sum := 0;
for i in 7 downto 0 loop
sum := sum * 2;
if (x(i)='1‘) then sum := sum + 1; end if;
end loop;
a <= sum;
end process;
 By adding Use ieee.numeric_std.all; we can write:

– a <= to_integer(unsigned(x));
– z <= std_logic_vector(to_unsigned(c,8)); -- 8 bits
Typical Errors
Typical Errors
Typical Errors
Typical Errors: Two solutions
BCD Counter
BCD Counter
BCD Counter
Library ieee;
Use ieee.std_logic_1164.all;
entity counter is
port ( load : in std_logic;
data : in integer range 0 to 255;
clk : in std_logic;
up_down : in std_logic;
sum : out integer range 0 to 255
);
end counter;
architecture behavior of counter is

begin
process (clk)
variable cnt : integer range 0 to 255;
variable direction : integer;
begin
if (up_down = '1') then direction := 1;
else direction := -1;
end if;
if (clk'event and clk = '1') then
if (load = ‘1’) then cnt := data;
else cnt := cnt + direction;
end if;
end if;
sum <= cnt;
end process;
end behavior;
Memory
 Computer memory is often classified as ROM (read-only

memory) and RAM (random access memory).
 ROM is random access and RAM is better thought of as read

and write memory.
 RAM can further be divided into SRAM (static RAM) and

DRAM (dynamic RAM).
– Static RAM retains its contents while power is applied to the
system.
– Dynamic RAM uses capacitors to store bits, which means
that the capacitance charge can leak away with time. Hence
DRAM needs refreshing intermittently.
ROM
 The contents of a ROM chip are defined once. Hence we can use
a constant array to model a ROM device in VHDL. Below is the
seven-segment decoder described as a ROM.
ROM
 The contents of a ROM chip are defined once. Hence we can use
a constant array to model a ROM device in VHDL. Below is the
seven-segment decoder described as a ROM.
ROM Memory – Example 1
entity program_ROM is
port ( address : in std_logic_vector (14 downto 0);
data : out std_logic_vector (7 downto 0);
enable : in std_logic );
end entity program_ROM;
architecture behavior of program_ROM is

subtype instruction_byte is bit_vector (7 downto 0);
type program_array is array (0 to 2**15 - 1) of
instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
…
);
begin
…
end architecture behavior;
library ieee;
use ieee.std_logic_unsigned.all;
entity ROM_2 is
port (clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector (5 downto 0);
data : out std_logic_vector (19 downto 0));
end ROM_2 ;
architecture behavior of ROM_2 is

type rom_type is array (63 downto 0) of std_logic_vector (19
downto 0);
signal ROM : rom_type :=
(X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
Begin
process (clk) is
begin
if (clk'event and clk = '1') then
if (en = '1') then
data <= ROM(conv_integer(addr));
end if;
end if;
end process;
end behavior ;
Static RAM
 A static RAM may be modeled in much the same way as a

ROM.
 Because data may be stored in the RAM as well as read from it,
the data signal is declared to be of mode inout.
– In addition, three control signals are provided.
 The first, CS (Chip Select), is a general control signal to enable a

particular RAM chip.
– If the CS signal is not enabled, the data output of the RAM
chip should be in the high impedance state.
Static RAM
 The other two signals are OE (Output Enable) and WE (Write

Enable). Only one of these two signals should be asserted at one
time.
– Data is either read from the RAM chip when the OE signal is
asserted, or written to the chip if the WE signal is asserted.
– If neither signal is asserted, the output remains in the high-
impedance state.
 All the control signals are active low. Like the ROM, the
memory array is modeled as an array, this time as a variable in a
process.
Static RAM
Static RAM
Synchronous RAM
 Sometimes we wish to allocate part of an FPGA as RAM.
 In order for this to be synthesized correctly and for ease of use,

it is best to make this RAM synchronous.
 Depending on the technology, there may be a variety of possible

RAM structures, e.g. synchronous read, dual-port.
 Here, we will simply show how a basic synchronous RAM is

modeled. This parameterizable example can be synthesized in
most programmable technologies.
Synchronous RAM
Synchronous RAM
Synchronous RAM
 The structure of this code is almost identical to that of a flip-flop

with an enable – in this case, the enable signal is the WE input.
 As with the SRAM example above, the Address input is

converted into an unsigned integer to reference an array.
 This example can be extended to include an output enable and

chip select, as above.

Clocked synchronous FSM
 Clocked: all storage elements employ a clock input (i.e.

all storage elements are flip-flops)
 Synchronous: all of the flip flops use the same clock

signal
 FSM: state machine is simply another name for

sequential circuits. Finite refers to the fact that the
number of states the circuit can assume is finite
 A synchronous clocked FSM changes state only when

a triggering edge (or tick) occurs on the clock signal
Clocked synchronous FSM structure
FSM Types
 Mealy machine
 Moore machine
Comparison of Mealy and Moore FSM
 Mealy machines have less states

– outputs are on transitions (n2) rather than states (n)
 Moore machines are safer to use

– outputs change at clock edge (always one cycle later)
– in Mealy machines, input change can cause output change as
soon as logic is done – a big problem when two machines are
interconnected – asynchronous feedback may occur if one
isn’t careful
Comparison of Mealy and Moore FSM
 Mealy machines react faster to inputs

– react in same cycle – don't need to wait for clock
– outputs may be considerably shorter than the clock cycle
– in Moore machines, more logic may be necessary to decode
state into outputs – there may be more gate delays after clock
edge
FSM in VHDL
entity state_machine is
port (clk : in std_logic;
input: in std_logic;
reset: in std_logic;
output: out std_logic_vector (1 downto 0) );
end state_machine;
architecture fsm of state_machine is

type state_type is (s0, s1, s2);
/input
signal state: state_type;
begin
/input s1
input
s0 input
Behavioral description
input
s2
end fsm;
/input
Behavioral description of the FSM
CF1_Reg : process (clk, reset)

begin
if reset = '1' then
state <= s0;
elsif (clk'event and clk = '1')
then when s0=>
case state is if input = '1‘ then
state <= s1;
else
state <= s0;
end if;
when s1=>
if input = '1' then
end case; state <= s2;
end if; else
end process; state <= s1;
end if;
CF2: process (state) when s2=>
begin if input = '1' then
case state is state <= s0;
when s0 => output <= "00"; else
when s1 => output <= "01"; state <= s2;
when s2 => output <= "10"; end if;
end case;
end process;
Moore FSM: Example – 1
 Sequence detector: sequence to detect “01”

library ieee;
entity edge_detector is
port( clk, reset : in std_logic;
level : in std_logic;
tick : out std_logic
);
end edge_detect;
architecture moore_fsm of edge_detector is

type state_type is (zero, edge, one);
signal state_reg, state_next : state_type;
begin
-- state register
Register : process(clk, reset)
begin
if (reset = '1') then
state_reg <= zero,
elsif (clk'event and clk = '1') then
state_reg <= state_next;
end if;
end process Register;
Moore FSM: Example – 1
-- next state / output logic

CF1_CF2 : process(state_reg, level)
begin
state_next <= state_reg;
tick <= '0';
case state_reg is
when zero =>
if level = '1' then
state_next <= edge;
end if;
when edge =>
tick <= '1';
if level = '1' then
state_next <= one;
else
state_next <= zero;
end if;
when one =>
if level = '0' then
state_next <= zero;
end if;
end case;
end process CF1_CF2;
end moore_fsm;
Mealy FSM: Example – 2

library ieee;
entity edge_detector is
port( clk, reset : in std_logic;
level : in std_logic;
tick : out std_logic
);
end edge_detect;
architecture mealy_fsm of edge_detector is

type state_type is (zero, one);
signal state_reg, state_next : state_type;
begin
-- state register
Register : process(clk, reset)
begin
if (reset = '1') then
state_reg <= zero,
elsif (clk'event and clk = '1') then
state_reg <= state_next;
end if;
end process Register;
Mealy FSM: Example – 2
-- next state / output logic

CF1_CF2 : process(state_reg, level)
begin
state_next <= state_reg;
tick <= '0';
case state_reg is
when zero =>
if level = '1' then
state_next <= one;
tick <= '1';
end if;
when one =>
if level = '0' then
state_next <= zero;
end if;
end case;
end process CF1_CF2;
end mealy_fsm;
Moore vs. Mealy
Example – Sequential Shift/Add Multiplier
M1
Ready
M2 N-bit
Unsigned Result
Start Multiplier
clk
 Designing a N-bit Unsigned Multiplier based on Add and Shift operations.

– Such an algorithm will require n iterations but the surface of the
multiplier will be reduced.
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
generic ( nbr_bits : natural := 4);
port ( M1 : in std_logic_vector
(nbr_bits-1 downto 0) ; -- first number
M2 : in std_logic_vector
(nbr_bits-1 downto 0); -- second number
 Designing a N-bit Unsigned Multiplier based on Add and Shift operations.

– Such an algorithm will require n iterations but the surface of the
multiplier will be reduced.
Start : in std_logic; -- new operation

clk : in std_logic; -- clock
Result : out std_logic_vector
(2*nbr_bits-1 downto 0); -- result
Ready : out std_logic);
-- result is available / ready for a new operation
end multiplieur;
 The data flow can be specified by the following algorithm:
Initialize : n2 = M2 ; n1 = M1 ; accu = 0
While (n2 # 0) do
If (LSB_n2 = 1) then
accu = accu + n1
End if
Shift n1 to left, n2 to right (with 0 at MSB)
End while
 Operators: An analysis of the algorithm allows us to deduce

immediately that it requires:
– A 2n-bit accumulator for the result variable (with reset)
– A 2n-bit left shift register for the variable n1 (with parallel

load)
– A n-bit right shift register for the variable n2 (with parallel

load)
 This leads to create three control signals and 2 indicator signals

for these operators.
– Signal Add controls the opening of the accumulator

– Signal initialize commands to reset the accumulator
– Signal shift common to both shift registers
– Signal lsb is the least significant bit of n2
– Signal zero allows the decoding of the value 0 of the set of
bits of n2
 This leads to create three control signals and 2 indicator signals

for these operators.
N-bit Unsigned Multiplier
M1
initialize
Start add M2
Controller shift Operators
Ready Result
lsb
zero
clk
 This makes it very easy to generate RTL code for this part
architecture rtl of multiplieur is

signal n1 : unsigned(2*nbr_bits-1 downto 0);
signal n2 : unsigned(nbr_bits-1 downto 0);
signal accu : unsigned(2*nbr_bits-1 downto 0);
signal add, shift, initialize,
zero, lsb : boolean;
-- . . .
begin
-- . . .
operators: process
begin
wait until rising_edge(clk);
if initialize then n2 <= unsigned(M2);
n1 <= resize(unsigned(M1),n1’length);
accu <= (others => ’0’);
elsif add then accu <= accu + n1;
elsif shift then
n2 <= ’0’ & n2(nbr_bits-1 downto 1);
n1 <= n1(2*nbr_bits-2 downto 0) & ’0’;
end if;
end process operators;
result <= std_logic_vector(accu);

zero <= (n2 = 0);
lsb <= (n2(0) = ’1’);
-- . . .
 Controller
– The controller has as inputs signals zero , lsb and start and as outputs the
signals initialize, shift and add. It is treated as a Moore machine.
𝑺𝒕𝒂𝒓𝒕
St_Init 𝒛𝒆𝒓𝒐
𝒛𝒆𝒓𝒐. 𝒍𝒔𝒃
St_Shift St_Add St_End
𝒛𝒆𝒓𝒐
-- other declarations
type state_type is (St_Init, St_Add, St_Shift, St_End);

signal state: state_type;
begin
-- other process (operators)
Controller: process
begin
wait until falling_edge(clk);
if (Start = ’1’) then State <= St_Init;
else
case State is
when St_Init =>
if zero then State <= St_End;
elsif lsb then State <= St_Add;
else State <= St_Shift;
end if;
when St_Add =>
State <= St_Shift;
when St_Shift =>

if zero then State <= St_End;
elsif lsb then State <= St_Add;
end if;
when St_End =>
State <= St_End;
end case;
end if;
end process Controller;
end rtl;
 Outputs of the controller
initialize <= (State = St_Init );

add <= (State = St_Add);
Shift <= (State = St_Shift );
Ready <= ’1’ WHEN State = St_End ELSE ’0’;
END rtl;

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DTR 8431–Architecture des

Microprocesseurs et Open Core

Synchronous Design using VHDL

Dr. Mohamad Mroué

1. Synchronous sequential systems

1. Synchronous sequential systems

 Most sequential systems are synchronous; that is, they

 Almost all large digital systems have some concept of

 Such systems are known as sequential systems, as

 A general model of a sequential system is shown in the

 The present state of the system can be updated either as soon as

 A latch is a level-sensitive memory device

 A flip-flop is an edge-triggered device

 The standard logic package provides a rising_edge and a

 Flip-flops may have synchronous set and reset functions as well

 A synchronous set or reset takes effect only at a clock edge.

 It is not necessary to include synchronous set or reset inputs in

 Similarly, a flip-flop with a clock enable signal may be modeled

 Multiple bit register

– For example, a sequence of bits can be converted into a word

– After a sufficient number of clock edges, the bits of the word

– A binary counter is a counter in the intuitive sense. It consists

– We can easily model this in VHDL, using the

– The contents of the counter are assigned to a signal and

– Thus when the counter has reached its maximum integer

 A modulo-8 Counter with an Asynchronous RESET

 A modulo-8 Counter with a Synchronous RESET

ERROR: can't determine definition of operator ""+"" -- found 0 possible

 This problem can be solved by adding the following

 Convert from std_logic_vector x to integer a

 By adding Use ieee.numeric_std.all; we can write:

architecture behavior of counter is

 Computer memory is often classified as ROM (read-only

 ROM is random access and RAM is better thought of as read

 RAM can further be divided into SRAM (static RAM) and

architecture behavior of program_ROM is

architecture behavior of ROM_2 is

 A static RAM may be modeled in much the same way as a

 The first, CS (Chip Select), is a general control signal to enable a

 The other two signals are OE (Output Enable) and WE (Write

 Sometimes we wish to allocate part of an FPGA as RAM.

 In order for this to be synthesized correctly and for ease of use,

 Depending on the technology, there may be a variety of possible

 Here, we will simply show how a basic synchronous RAM is

 The structure of this code is almost identical to that of a flip-flop

 As with the SRAM example above, the Address input is

 This example can be extended to include an output enable and

1. Synchronous sequential systems

 Clocked: all storage elements employ a clock input (i.e.

 Synchronous: all of the flip flops use the same clock

 FSM: state machine is simply another name for

 A synchronous clocked FSM changes state only when

 Mealy machines have less states

 Moore machines are safer to use

 Mealy machines react faster to inputs

architecture fsm of state_machine is

CF1_Reg : process (clk, reset)

 Sequence detector: sequence to detect “01”