Antennas and Radiation Mechanism of Various Antennas and Antenna Arrays
Antennas and Radiation Mechanism of Various Antennas and Antenna Arrays
Antennas and Radiation Mechanism of Various Antennas and Antenna Arrays
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 - - - - - 2 - - - - - 2 - -
2 2 - 2 - - - - - - - - - 2 - -
3 - 2 - - - 1 1 - - - - - 1 - -
4 - - 2 - - 1 - - - - - 2 - -
5 3 1 - - - 1 1 - - - - 1 2 - -
L T P C
CODE COMPUTER NETWORKS
3 0 0 3
COURSE OBJECTIVES
1 To study and understand the basics of data communication networks
2 To understand the division of network functionalities into layers
3 To get familiarize with the up-to-date developments in switching and network technology
4 To Learn the flow control and congestion control algorithms
5 To understand the techniques involved in application layers
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
2 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
3 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
4 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
5 3 2 2 1 3 3 2 - 3 1 1 2 3 2 3
L T P C
CODE VLSI DESIGN
3 0 0 3
COURSE OBJECTIVES
1 Introduce the basics of Integrated Circuits and fabrication process.
2 Study the fundamentals of CMOS circuits and its characteristics
3 Brief knowledge on various combinational design in Verilog module.
4 Impart knowledge on various sequential logic design in Verilog module.
5 Learn the different FPGA architectures.
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
COURSE CONTENTS
UNIT-1 INTRODUCTION TO VERILOG HDL (9 Hrs)
Basics of Verilog, operators, VLSI design flow, data types hierarchy procedures and assignments, timing
controls and delays, tasks and functions, control statements. Continuous assignments, Sequential and
parallel statement groups Timing control (level and edge sensitive) and delays, tasks and functions, control
statements, Blocking & non-blocking assignments, If-else and case statements, For- while-repeat and
forever loops, Rise, f all, min, max delays.
UNIT II VERILOG MODELLING (9 Hrs)
Gate-level modelling - Realization of Combinational and sequential circuits, Compilation and simulation of
Verilog code, Test bench, Dataflow modelling - Realization of Combinational and sequential circuits-
Behavioural modelling Realization of Combinational and sequential circuits -Switch-level modelling
UNIT-III VERILOG HDL FOR COMBINATIONAL DESIGN (9 Hrs)
Design of Half and Full Adders, Half and Full Subtractors, Multiplier, Binary Parallel Adder – Carry look
ahead Adder, Carry Skip adder, Carry save adder, BCD Adder, Multiplexer, Demultiplexer, Magnitude
Comparator, Decoder, Encoder, Priority Encoder, Baugh-Wooley multiplier, Wallace Tree multiplier Booth
multiplier
UNIT -IV VERILOG HDL FOR SEQUENTIAL DESIGN (9 Hrs)
Static latches and Registers, Dynamic latches and Registers, Pulse Registers, Sense Amplifier Based
Register, Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential Circuits.
UNIT -V ULTRA FAST VLSI CIRCUITS AND PROGRAMMABLE ASIC’S (9 Hrs)
Ultra fast systems-GaAS crystal structure-GaAS fabrication-device modeling and performance
estimation(only GaAS) Antifuse and SRAM Practical issues-FPCA economics, programmable logic cells,
Actel ACT1, ACT2 and ACT3-Xilinx LCA, Ultra FLEX and Ultra MAX.
TEXT BOOKS
UNIT 1- 4 1. J. Bhasker ―A Verilog HDL Primer,‖Star Galaxy Press,1997.
UNIT 3 & 4 2. R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, Wiley, (3/e), 2010.
3. Morris Mano M, Michael D. Ciletti, Digital Design with an Introduction to the Verilog
HDL, 5th ed., Pearson, 2014
UNIT 5
4. M.J. Smith, “Application Specific Integrated Circuits” Addison Wesley, 1997
REFERENCE BOOKS
UNIT 1,2 1. Navabi, “VHDL analysis and modelling of digital systems”, Mc Graw Hill, 1993
2. Douglas A Pucknell and Kamran Eshranghian, ”Basic VLSI Design” Prentice Hall of
UNIT 3,4 India, New Delhi, 2011
3. R.Jacob Baker, Harry W.LI., David E.Boyee, ―CMOS Circuit Design, Layout and
4. Simulation‖, Prentice Hall of India 2005
WEB RESOURCES
1. https://www.tutorialspoint.com/vlsi_design/
2. http://www.vlsi-expert.com/p/vlsi-basic.html
3. https://www.youtube.com/watch?v=9SnR3M3CIm4
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 - - 3 - - - - - - - - 3 1 -
2 3 3 3 3 - - - - - - - - 3 1 -
3 3 3 3 3 3 - - - - - - - 3 1 -
4 3 3 3 3 3 - - - - - - - 3 1 -
5 3 - 3 3 3 - - - - - - - 3 1 -
L T P C
CODE INFORMATION THEORY AND CODING
3 0 0 3
COURSE OBJECTIVES
1 To describe and analyze the information source and channel capacity
2 To attain knowledge about Continuous and discrete Communication Channel
To analyze the source coding techniques such as Shanan Fano Encoding, Huffman Coding,
3
Arithmetic Coding
To Construct the various channel coding schemes such as block codes, cyclic codes and
4
convolutional codes
5 To apply statistical techniques for signal detection
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
2 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
3 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
4 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
5 3 3 3 2 1 1 1 - 1 1 - 2 3 2 1
L T P C
CODE COMPUTER NETWORKS LABORATORY
0 0 3 1.5
COURSE OBJECTIVES
1 To learn to communicate between two desktop computers
2 To learn to implement the different protocols
3 To be familiar with IP Configuration
4 To be familiar with the various routing algorithms
5 To be familiar with simulation tools
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
COURSE CONTENTS
1. Implementation of Error Detection / Error Correction Techniques
2. Implementation of Stop and Wait Protocol and sliding window
3. Implementation and study of Goback-N and selective repeat protocols
4. Implementation of High Level Data Link Control
5. Implementation of IP Commands such as ping, Traceroute, ns lookup.
6. Implementation of IP address configuration.
7. To create scenario and study the performance of network with CSMA / CA protocol and compare with
CSMA/CD protocols.
8. Network Topology - Star, Bus, Ring
9. Implementation of distance vector routing algorithm
10. Implementation of Link state routing algorithm
11. Study of Network simulator (NS) and simulation of Congestion Control Algorithms using NS
12. Implementation of Encryption and Decryption Algorithms using any programming language
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
2 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
3 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
4 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
5 3 2 3 1 3 3 2 - 2 2 3 1 3 - 3
L T P C
CODE VLSI DESIGN LABORATORY
3 0 3 1.5
COURSE OBJECTIVES
The student should be made:
1 To learn Hardware Descriptive Language (Verilog)
2 To learn the fundamental principles of VLSI circuit design in digital
3 To provide hands on design experience with professional design (EDA) platforms
4 To familiarize fusing of logical modules on FPGAs
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
CO 1 Ability to analyse and design various techniques for implementing combinational and
sequential digital circuits
CO 2 Analyzing and implementing the various combinational logic circuits and its truth table.
CO 3 Analyzing the various sequential logic circuits and its characterization.
S.No LIST OF EXPERIMENTS
1 Design an 8bit Adder using HDL. Simulate it using Xilinx/Altera Software and implement
by Xilinx/Altera FPGA
2 Design a 4bit Multiplier using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
3 Design an ALU using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
4 Design a Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
5 Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
6 Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
7 Design and simulate a MOD-10 counter using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
8 Design and simulate a 4-bit Asynchronous UP/DOWN counter using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
9 Design and simulate a 4-bit synchronous UP/DOWN counter using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
10 Design and simulate RTL and generate a waveform for combinational circuits
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 - - 3 - - - - - - - - 3 1 -
2 3 3 3 3 - - - - - - - - 3 1 -
3 3 3 3 3 3 - - - - - - - 3 1 -
4 3 3 3 3 3 - - - - - - - 3 1 -
5 3 - 3 3 3 - - - - - - - 3 1 -
CODE MINI-PROJECT L T P C
0 0 2 1
COURSE OBJECTIVES
COURSE OUTCOMES
Upon completion of the course, students shall have ability to
CO1 Identify problem faced in Society
CO2 Understand the impact of professional engineering solutions to issue
CO3 Design solutions for complex engineering problems
CO4 Demonstrate knowledge and understanding of the engineering to provide solution
CO5 Apply the innovative solution to the identified problem
COURSE CONTENTS
Preparing a project – brief proposal including
Problem Identification
A Statement of system / process specifications proposed to be developed
(Block diagram / concept tree)
List of possible solutions including alternatives and constraints
Cost benefit analysis
Time line of activities
A report highlighting the design finalization
(based on functional requirements & standards ( if any) )
A Presentation including the following
Implementation Phase ( Hardware / Software / both )
Testing and validation of the developed system
Learning in the project
Demonstration of Working Kit
COs/POs/PSOs Mapping
Program Specific
Program Outcomes (POs)
COs Outcomes (PSOs)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
2 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
3 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
4 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2
5 1 3 3 2 3 3 2 - 3 2 2 1 3 2 2